JPH0650812B2 - Switching control circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control circuit for a switching circuit used in an inverter or the like for switching an input voltage by connecting switching elements such as transistors in a bridge.

In an inverter having a switching circuit, an output voltage is generally fed back and compared with a reference voltage to form an error output, and the pulse width of a switching pulse is varied according to the magnitude of the error output. FIG. 1 is a block diagram of a conventional switching control circuit. The sawtooth wave oscillating circuit 1 forms a sawtooth wave having a constant cycle and a sawtooth wave synchronizing pulse synchronized with the sawtooth wave. The sawtooth wave synchronization pulse may be used as a dead time pulse that gives a rest period when the switching elements are turned on and off in order to prevent simultaneous conduction of the switching elements. The sawtooth wave synchronizing pulse causes the T-type flip-flop 2 to invert every cycle. The sawtooth wave is compared with the error signal by the comparator 3 to form a comparison pulse b which becomes "H" only during the period when the former exceeds the latter or during the opposite period. The NAND gates 4 and 5 logically AND the Q output d and the inverted output e of the flip-flop 2, the sawtooth wave synchronizing pulse c and the comparison pulse b to form switching pulses f and g. The switching pulses f and g are supplied to, for example, a bridge-connected switching circuit K as shown in FIG. When the switching pulse f becomes active "L", the switching element Q
When the switching pulse g becomes active "L", the switching elements Q2 and Q4 become conductive. By repeating this, excitation of the output transformer T and resetting thereof are alternately repeated, and a switching output can be obtained on the secondary side. However, as shown in FIG. 2, when the level of the error signal p is lower than the maximum level of the sawtooth wave a, the operation works without any problem, but when the error signal p exceeds the sawtooth wave a (point A), comparison is made. Since the pulse b is not formed, the switching pulse f is not formed, so that the switching pulse g is output twice in succession.
As a result, when the switching circuit of the bridge connection as shown in FIG. 1 is used, the exciting current flows to the transformer T twice continuously, and the transformer T is in the DC excitation state. In the worst case, the switching element may be destroyed.

FIG. 3 shows a main part of a switching control circuit for solving the above-mentioned drawbacks. In this circuit, the logical product of the comparison pulse b and the sawtooth wave synchronization pulse c is taken by the gate 6, and the flip-flop 2 is inverted by its output h. By doing so, the flip-flop 2 does not perform the inverting operation at the point A when the error signal p exceeds the sawtooth wave a as shown in FIG. That is, the flip-flop 2 retains the previous state and inverts the state only when the error signal p becomes equal to or lower than the sawtooth wave level. As a result, the problem of double pulses (switching pulses do not occur alternately but continuously occur on one side) as shown in FIG. 2 does not occur. However, the error signal p
Is lower than the level of the sawtooth wave twice during one cycle as shown at point B, the comparison pulse b is generated twice in succession during one cycle, which causes the switching pulses f and g to also repeat for one cycle. They occur very close to each other and occur alternately. For this reason,
If the interval t1 between the switching pulses f and g is equal to or shorter than the storage time of the switching element, a period in which both switching elements are momentarily brought into conduction occurs, and a short circuit of the power supply and destruction of the switching element or the like due to the short circuit current occur. This will cause problems.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned drawbacks and to prevent a double pulse phenomenon and alternating pulses from occurring alternately in a very short time, and to provide a highly reliable switching control circuit.

FIG. 5 is a circuit diagram of a switching control circuit according to an embodiment of the present invention. The sawtooth wave oscillating circuit 1 oscillates the sawtooth wave a and a pulse c which becomes “L” for a very short time at the rising time of the sawtooth wave a. The sawtooth wave a and a dead time control signal supplied from the outside are generated. A comparison amplifier 7 for comparison and amplification, and an AN for ANDing the output thereof and the pulse c
Due to the interaction of the D gates 8, the dead time pulse c'is obtained as a sawtooth wave synchronizing pulse at the output of the AND gate 8. The dead time control signal supplied from the outside is synchronized with the pulse c, and the comparison amplifier 7
A constant voltage E0 is intermittently supplied to. The output of the comparator 3 which compares the error signal p with the sawtooth wave a is led to the latch circuit 9. The latch circuit 9 is composed of a flip-flop, which is set when the input terminal S receives an active "L" pulse and is reset when the terminal R receives an active "L" signal. The inverted output of the latch circuit 9 is logically ANDed with the pulse c by the negative logic AND gate 10, and the output is led to the flip-flop 2. The dead time pulse c ', the outputs d and e of the flip-flop 2 and the Q output i of the latch circuit 9 are led to AND gates 4 and 5 which form a switching pulse forming circuit, and are the same as in the conventional circuit shown in FIG. Switching signals f and g are formed by ANDing the respective signals. That is, the AND gate 4 logically ANDs the dead time pulse c ′, the Q output d of the flip-flop 2 and the Q output i of the latch circuit 9.
The AND gate 5 logically ANDs the dead time pulse c ′, the inverted output e of the flip-flop 2 and the Q output i of the latch circuit 9.

With the above configuration, the latch circuit 9 is set by the comparison pulse b and reset by the pulse c generated in each cycle. Therefore, when set by the comparison pulse b, the set state is held for one cycle of the sawtooth wave. . Therefore, even if the comparison pulse b is continuously generated within one cycle of the sawtooth wave, the state of the latch circuit 9 does not change. As a result, it is possible to prevent the switching pulses from being alternately generated in a very short period at the point B in FIG.

6 and 7 are time charts showing the operation of the switching control circuit of the above embodiment. B in FIG.
At a point, when the error signal p falls below the level of the sawtooth wave a twice in one cycle, the comparison pulse b comes very close to each other in one cycle as shown in FIG. To do. This comparison pulse b is active "L". At the first falling edge of the comparison pulse b1, the latch circuit 9
Is set. However, since the latch circuit 9 is not reset until the pulse c2 of the next cycle comes, the latch circuit 9 remains set even when the comparison pulse b2 is generated next. Therefore, the flip-flop 2 is not inverted by the second comparison pulse b2.
The flip-flop 2 next inverts when the negative logic AND gate 10 receives the pulse c2 of the next cycle. Thus, by providing the latch circuit 9 that holds the set state until the next cycle of the sawtooth wave, even if the comparison pulse b is generated twice in one cycle, the inversion operation of the flip-flop 2 is prevented. can do.

FIG. 7 is a time chart showing the operation when the error signal p exceeds the level of the sawtooth wave a. The comparison pulse b is not generated at points A and A'in the figure. However, the negative logic AND gate 10 causes the pulse c and the latch circuit 9
Since it is logically ANDed with the inverted output signal of
At that point, the flip-flop 2 does not perform the inversion operation. Therefore, the double pulse phenomenon can be prevented.

As described above, according to the present invention, since the latch circuit which is set by the comparison pulse and holds the set state until the next cycle of the sawtooth wave is provided, the double pulse phenomenon and the close proximity during one cycle are achieved. As a result, it is possible to completely prevent the phenomenon in which switching pulses are alternately generated. For this reason,
Even if the error signal becomes unstable or noise is superimposed on the error signal, it is possible to reliably prevent switching element destruction due to momentary power supply short-circuit phenomenon and DC magnetic saturation of the transformer. Can be very high.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a conventional switching control circuit, FIG. 2 is a time chart showing its operation, FIG. 3 is a circuit diagram of a main part of another conventional example, and FIG. 4 is a time chart showing its operation. . FIG. 5 is a circuit diagram of a switching control circuit according to an embodiment of the present invention, and FIGS. 6 and 7 are time charts showing the operation of the switching control circuit. 1 ... Sawtooth wave oscillator, 2 ... Flip-flop, 3 ... Comparator, 4, 5 ... AND gate (switching pulse forming circuit), 9 ... Latch circuit.

Claims (1)

[Claims] 1. A saw-tooth wave oscillating circuit for oscillating a saw-tooth wave and a saw-tooth wave synchronizing pulse when the saw-tooth wave rises, and a comparison for comparing an error signal for an output to be controlled with the saw-tooth wave. A circuit, a latch circuit which is set by a comparison pulse obtained by this comparison circuit and holds the set state until the next cycle of the sawtooth wave, an inverted output signal of the latch circuit and the sawtooth wave synchronization pulse And a gate for outputting a pulse synchronized with the sawtooth wave synchronizing pulse, a flip-flop that is inverted by an output pulse of the gate, an output of the flip-flop, an output of the latch circuit, and the sawtooth wave. A switching pulse forming circuit that logically ANDs synchronizing pulses to form a switching pulse that is alternately output to each of the bridge-connected switching elements. , Comprising a switching control circuit.