JPH065237B2 - Control circuit of short-circuit detection display device - Google Patents

Description

The present invention relates to a control circuit for a short-circuit detection display device attached to a distribution line.

(Prior Art) Conventionally, a short-circuit detection display device has been used for the purpose of early detection of a short-circuit fault in a distribution line. However, it was not possible to know by regular regular inspection whether or not the display device is operating normally, that is, whether or not the circuit of the display device is defective. Therefore, the failure detection display device must be found based on the actual failure state of the power distribution line and the operating condition of the display device. For this reason, there was some uncertainties in determining the failure point of the distribution line.

(Problems to be Solved by the Invention) The present invention makes it possible to find a defective detection display device by a regular inspection, and detects an uncertain factor that a conventional display device has, that is, a defect detection that affects a fault point of a distribution line. The adverse effect of the display device is eliminated. Also, even if a distribution line failure occurs without regular inspection, whether the detection display device is operating normally or abnormally can be easily confirmed by checking the detection operation status and the failure diagnosis display. Reliability for early detection of failure points is improved.

Structure of the Invention (Means for Solving Problems) The present invention has been made to solve the above problems, and a short circuit current flows through a distribution line in the control circuit of the short circuit detection display device of the present invention. When a short-circuit detection control circuit that outputs a control signal based on the detection signal output by the current detector,
In a short-circuit detection display device having a display drive circuit that drives a short-circuit indicator based on a control signal from the control circuit, the short-circuit detection control circuit constantly generates a check signal at predetermined time intervals. A self-diagnosis circuit comprising a circuit and a check signal comparison circuit for operating a check indicator based on a comparison of the two injected signals is connected, while the check signal comparison circuit and the display drive circuit are connected between Connect a display lock circuit that locks the operation of the display drive circuit when the check signal comparison circuit operates, and the check signal generation circuit individually injects a check signal to the short circuit detection control circuit and the check signal comparison circuit to perform the check. The signal comparison circuit compares the check signal injected from the check signal generation circuit with the check signal injected into the control circuit. Then, the control signal is compared and judged with the signal output to the check signal comparison circuit.If the two signals match, the check indicator is displayed normally, and if the two signals do not match, the check signal is checked. The gist of the invention is that the display is configured to display an abnormality.

(Operation) With the above configuration, the check signal generation circuit of the self-diagnosis circuit injects the check signal into the short circuit detection control circuit. Next, the check signal comparison circuit compares and judges the signal injected into the short circuit detection control circuit and output from the control circuit with the check signal injected from the check signal generation circuit.

Then, as a result of the comparison, the check signal comparison circuit displays the check indicator normally when the two signals match each other and abnormally displays the check indicator when the two signals do not match each other.

Further, when the check signal comparison circuit is operating, the check display is prioritized even if a short circuit current flows through the distribution line, and the short circuit display is performed after the check display.

(Embodiment) First Embodiment An embodiment in which the present invention is embodied in a short-circuit ground fault direction detection display device will be described below with reference to FIGS. 1 to 5.

(Detector) In FIG. 1, first, the detector of the short-circuit ground fault direction detection display device will be described. The detectors are first and second current detectors attached and arranged to the distribution line L of each phase. Second and third current transformers CT1, CT2, CT3, a zero-phase current detector 85 for detecting a zero-phase current flowing through the distribution line L, and a zero-phase voltage detector 86 are provided.

The first, second, and third current transformers CT1, CT2, C
T3 outputs a transformation current from its secondary side when a short-circuit current flows through the distribution line.

(Control Circuit) The control circuit is roughly classified into a short-circuit detection unit 68, a no-voltage detection unit 69, and a short-circuit determination circuit 70, which constitute a short-circuit detection control circuit,
A drive circuit of the short-circuit indicator Ha for displaying and driving the short-circuit indicator Ha, and a self-diagnosis circuit 7 for diagnosing the short-circuit detection control circuit.
7, a check indicator Hc for displaying the comparison and determination result of the self-diagnosis circuit 77, and a short-circuit indicator Hc for the check signal.
The display lock circuit 76 which does not display, the phase comparison judgment circuit 84 which compares the phases of the zero phase voltage and the zero phase current at the time of the ground fault, and the ground fault indicator based on the judgment result of the phase comparison judgment circuit 84. The drive circuit of the ground fault direction indicator to be driven, the time limit circuit 93 for restoring the display of the short-circuit indicator Ha and the ground fault direction indicator, and the time period control circuit 10 for controlling the simultaneous time limit circuit.
4 and a power supply circuit 97.

Hereinafter, each unit will be described in detail with reference to the drawings.

I. Short Circuit Detection Unit The short circuit detection unit 68 is a first, second and third short circuit detection circuit X.
It is composed of a, Xb, and Xc.

First, the first short circuit detection circuit Xa will be described.

Full-wave rectifier 3 connected to the first current transformer CT1
A parallel circuit of a smoothing capacitor C1 and a resistor R1 is connected between the plus and minus terminals of the. Similarly, a diode D is placed between the positive and negative terminals of full-wave rectifier 3.
1, a series circuit including a parallel circuit of the variable resistor R2 and the variable resistor R3, a changeover switch S1, a resistor R4, and a light emitting diode LED of the photocoupler PC is connected. By switching and connecting the changeover switch S1 to the variable resistor R2 or the variable resistor R3 side, the short-circuit ground fault direction detection display device can be attached to the distribution line L through which different steady load currents flow. ing. A capacitor C2 is connected between the negative terminal of the diode D1 and the negative terminal of the full-wave rectifier 3.

A series circuit of an emitter / collector of the switching transistor Tr1 and a resistor R5 connected via the collector is connected between the output terminal P1 (plus terminal) of the power supply circuit Z described later and the ground line E1. The collector / emitter of the phototransistor PTr in the photocoupler PC is connected between the ground line E1 and the base terminal of the switching transistor Tr1.

The collector / emitter of the switching transistor Tr2 is connected between the output terminal P1 (plus terminal) of the power supply circuit Z described later and the ground line E1. A series circuit of resistors R9 and R10 is connected between both terminals of the resistor R5, and the positive terminal of the resistor R10 is connected to the base terminal of the switching transistor Tr2. A capacitor C3 is connected between both terminals of the resistor R10.

Therefore, when the short-circuit current flows through the distribution line L, the first current transformer CT1 outputs the transformed current based on the short-circuit current, and the full-wave rectifier 3 full-wave rectifies the transformed current. The photocoupler PC receives the full-wave rectified analog signal and digitally outputs it by the light emitting diode LED and the phototransistor PTr.

Further, when the level of the digital signal applied to the base terminal is a predetermined value, the switching transistor Tr1
Turns on and outputs a short-circuit current detection signal. Then, the switching transistor Tr1
Is turned on, the voltage of the resistor R10 is applied to the base terminal of the switching transistor Tr2, so that the switching transistor Tr2 is turned on.

The resistors R1 to R5, R9, R10, the photocoupler P
The current discriminating switching circuit 71 in FIG. 1 is configured by C, the switching transistors Tr1 and Tr2, the capacitors C2 and C3, and the like.

The rectifier circuit 3 and the current discrimination switching circuit 71 constitute a first short circuit detection circuit Xa.

The second short-circuit detection circuit Xb and the third short-circuit detection circuit Xc are configured in the same manner as the first short-circuit detection unit, and therefore, the same reference numerals are given to the same configurations and the description thereof will be omitted. A resistor R11 is connected between the resistor R1 and the negative terminal of the full-wave rectifier 3 in the third short circuit detection circuit Xc.

II. Non-voltage detection unit Next, the non-voltage detection unit will be described.

In the third short circuit detection circuit Xc, a diode array Da is connected between the negative terminal of the resistor R1 and the negative terminal of the full-wave rectifier 3, and between the positive terminal side of the diode array Da and the negative terminal of the full-wave rectifier 3. Is resistance R
A series circuit of 12 and R13 is connected. The collector / emitter of the transistor Tr3 is connected between the output terminal P1 of the power supply circuit described later and the negative terminal of the full-wave rectifier 3, and the positive terminal of the resistor R13 is connected to the base terminal of the transistor Tr3. Further resistance R1
Capacitors C4 and C5 are connected between both terminals of 3.

A series circuit of a knot circuit 5 and an inverter 6 is connected to the collector of the transistor Tr3.

Then, when the distribution line L is in a steady state, the voltage between the diode arrays Da is divided by the resistors R12 and R13, and the transistor Tr3 is turned on by applying the voltage of the resistor R13 to the base terminal.
The signal between a is voltage-amplified and applied to the input terminal of the knot circuit 5.

When the circuit breaker at the substation trips due to a short-circuit fault or the like on the distribution line L, the voltage across the diode array Da becomes no voltage, so the voltage of the resistor R13 (that is, no voltage) is applied to the base terminal of the transistor Tr3. Therefore, the transistor Tr3 is turned off. Then, the transistor Tr3 is turned off, and the potential between the collector and the emitter of the transistor Tr3 rises, so that the knot circuit 5 receives the signal corresponding to the logical value 1.

Therefore, a signal corresponding to the logical value 0 is output from the output terminal of the knot circuit 5, the inverter 6 rectangularizes the waveform based on the signal corresponding to the logical value 0, and the signal corresponding to the logical value 1 (no voltage Detection signal) is output.

The diode array Da, the resistors R11 to R14, the capacitors C4 and C5, and the transistor Tr3 constitute a no-voltage detection circuit 72, and the knot circuit 5 and the inverter 6 constitute a second waveform manipulation circuit.

III. Short Circuit Discrimination Circuit Next, the first to third short circuit detection circuits Xa, Xb. The short-circuit current detection signal, which is a digital signal output from Xc, and the non-voltage detection circuit 72 to the second waveform manipulation circuit 7
Short circuit determination circuit 70 for inputting a no-voltage detection signal via 3
Will be described.

The collector terminal of the switching transistor Tr2 in each of the short circuit detection circuits Xa, Xb, and Xc is connected to the OR circuit 8 via the knot circuit 7. A knot circuit 9 is connected to the output terminal of the OR circuit 8,
The output terminal of the knot circuit 9 is connected to one input terminal of the NAND circuit 10.

Also, the output terminal of the knot circuit 9 and the NAND circuit 10
A series circuit of resistors R15 and R16 and the knot circuit 11 is connected between the other input terminals of the above, and a capacitor C6 is connected between the positive terminal of the resistor R16 and the ground line E2.

Between the output terminal of the NAND circuit 10 and one input terminal of the AND circuit 13 as a short circuit detection gate circuit, a series circuit of a knot circuit 12 as a first waveform manipulating circuit 74, a diode D2, a resistor R17 and a resistor R18. Are connected. The output terminal P1 of the power supply circuit 97 is connected to the positive terminal of the diode D2 via a resistor R19. A parallel circuit of a resistor R20 and a capacitor C7 is connected between the positive terminal of the resistor R18 and the earth line E2, and the input terminal of the AND circuit 13 is connected to the input terminal of the AND circuit 13 for a predetermined time depending on the time constant of the CR circuit. It is designed to apply a voltage.

A signal memory circuit 75 is constituted by the resistor R20 and the capacitor C7.

The knot circuit 12 (first waveform manipulation circuit), the signal memory circuit 75, the AND circuit 13 (short circuit detection gate circuit)
The short-circuit discrimination circuit 70 is constituted by and.

IV. Driving Circuit of Short-circuit Indicator Next, the driving circuit of the short-circuit indicator Ha will be described. The output terminal of the AND circuit 13 is connected to one input terminal of the NAND circuit 15.

Further, the output terminal of the AND circuit 13 and the NAND circuit 1
A series circuit of resistors R21 and R22 and a knot circuit 16 is connected between the other input terminal of the resistor 5, and a capacitor C8 is connected between the positive terminal of the resistor R22 and the ground wire E2.

A knot circuit 18 is connected to the output terminal of the NAND circuit 15, and the output terminal of the knot circuit 18 is an AND circuit 1.
7 is connected to one input terminal. Same AND circuit 1
The output terminal of 7 is connected to the input terminal of an OR circuit 55 described later. Further, a switching transistor Tr is provided between the output terminal P1 of the power supply circuit 97 and the negative terminal of the full-wave rectifier 3.
A series circuit of the collector / emitter 4 and the set terminal 19 / common terminal 20 of the short-circuit indicator Ha is connected.

The output terminal of the AND circuit 17 is connected to the base terminal of the switching transistor Tr4 via a resistor R23, and a resistor R24 is connected between the negative terminal of the resistor R23 and the earth line E2.
The voltage of 24 is applied to the base terminal of the switching transistor Tr4.

Therefore, while the signal corresponding to the logical value 1 from the signal memory circuit 75 is being applied, the AND circuit 13 outputs the signal corresponding to the logical value 1 from the second waveform operating circuit 73 of the non-voltage detection unit (no When a voltage detection signal) is applied, a signal corresponding to a logical value 1 is applied to the short circuit display switching circuit 98 based on both signals.

The knot circuits 16 and 18, the NAND circuit 15, the AND circuit 17, and the resistors R21 to R24 the capacitor C8 constitute a short circuit display switching circuit 98 as a display drive circuit.

Further, the output terminal P1 of the power supply circuit 97 described later and the short-circuit indicator Ha
Between the reset terminals 21 of the switching transistor T
The collector and emitter of r11 are connected. The output terminal of the OR circuit 60 is connected to the base terminal of the switching transistor Tr11, and a resistor R is provided between the base terminal and the negative terminal of the full-wave rectifier 3.
65 is connected, and the voltage of the resistor R65 is applied to the base terminal of the switching transistor Tr11.

Then, the OR circuit 60 outputs the signal S corresponding to the logical value 1
When ig6 (display recovery signal) is applied, a signal corresponding to the logical value 1 is applied to the next stage, thereby applying the voltage of the resistor R65 to the base terminal and turning on the switching transistor Tr11. As a result, the display recovery drive current is supplied from the switching transistor Tr11 to the reset terminal 21 of the short-circuit indicator Ha.

The OR circuit 60, the resistor 63, the switching transistor Tr11, etc. are used to restore the display recovery switching circuit 99.
And the drive circuit of the short-circuit indicator Ha together with the short-circuit display switching circuit 98.

V. Short Circuit Indicator Here, the short circuit indicator Ha will be described with reference to FIG.

The short-circuit indicator Ha is composed of a plurality of magnetic reversal indicators. In each magnetic reversal display, when a short-circuit display drive current flows through the set terminal 19, each drive coil 25 is excited,
A polarity opposite to that shown in FIG. 3, that is, the magnetic pole portion 24.
a is magnetized to the S pole and the magnetic pole portion 24b is magnetized to the N pole, and each disk 22 is inverted so that the N pole faces the magnetic pole portion 24a (S pole) and the S pole faces the magnetic pole portion 24b (N pole). As the discs are rotated, the marks on the back surface 22b of each disk 22 are displayed all at once to the outside (short-circuit display).

On the contrary, when a return drive current flows through the reset terminal 21 to the short-circuit indicator Ha, each return drive coil 21 is excited, and the magnetic pole portion 24a becomes the N pole and the magnetic pole portion 24b becomes the magnetic pole portion 24b as shown in FIG. Each disk 22 is magnetized to the S pole, and the N pole of each disk 22 is the magnetic pole portion 24a (N pole) and the S pole is the magnetic pole portion 24b.
Each disc 2 is rotated so as to face the (S pole).
The markers attached to the surface 21a of No. 2 are constantly displayed to the outside all at once.

VI. Self-Diagnosis Circuit Next, the self-diagnosis circuit 77 will be described.

This self-diagnosis circuit 77 is provided for each short circuit detection circuit Xa, Xb, x.
The first to third check signal generating circuits 78 to 80 for injecting the check signals Sig1, Sig2 and Sig3 (check current) into c, and the short circuit detecting circuits Xa, Xb and Xc through the short circuit judging circuit based on the check signal. Check signal comparison circuit 81 for comparing the signal applied from the check signal with the check signal, and a check indicator switching circuit 82.
It consists of and.

Since the check signal generating circuits 78 to 80 connected to the short circuit detecting circuits Xa, Xb, and Xc have the same configuration, the first check signal generating circuit 78 connected to the first short circuit detecting circuit Xa will be described. The other second and third check signal generation circuits 79 and 80 are denoted by the same reference numerals and the description thereof will be omitted.

The IC 27 that constitutes the first check signal generation circuit 78 is connected to the output terminal P1 of the power supply circuit 97 and also includes the oscillator circuit 2 including the resistor R25, the capacitor C9 and the resistor 26.
8 is connected, and the IC 27 divides the number of oscillations of the oscillation circuit 28. Further, the clear terminal 31 of the IC 27 is connected to the negative terminal of the full-wave rectifier via the resistor R29. Therefore, the IC 27 always divides the oscillation number of the oscillation circuit 28.

Further, one input terminal of the NAND circuit 29 is connected to the output terminal of the IC 27, and resistors R27 and R2 are provided between the other terminal of the NAND circuit 29 and the output terminal of the IC 27.
8 and the knot circuit 30 are connected in series, and the resistor R2
A capacitor C10 is connected between the positive terminal of 8 and the negative terminal of the full-wave rectifier 3.

A switching transistor T is connected to the output terminal P1 of the power supply circuit 97 described later and the positive terminal of the light emitting diode LED in the photocoupler PC of the first short circuit detection circuit Xa.
The collector and emitter of r5 are connected. And
A knot circuit 32 is connected between the base terminal of the switching transistor Tr5 and the output terminal of the NAND circuit 29. In addition, the switching transistor Tr
A resistor R32 is connected between the base terminal of 5 and the negative terminal of the full-wave rectifier 3.

Therefore, the IC 27 constantly divides the number of oscillations of the oscillation circuit 28 and applies a signal corresponding to the logical value 1 from its output terminal to one terminal of the NAND circuit 29 at predetermined time intervals. Further, a signal corresponding to the logical value 1 is applied to the knot circuit 30 after being delayed by the time constant of the resistor R27 and the capacitor C10, and the knot circuit 30 outputs the other signal of the NAND circuit 29 based on the signal corresponding to the logical value 1. A signal corresponding to a logical value of 0 is applied to the terminal. Then, the NAND circuit 29 applies one pulse signal corresponding to the logical value 0 to the knot circuit 32 based on the signals applied to both terminals.

Then, the knot circuit 32 applies the signal corresponding to the logical value 1 to the next stage based on the pulse signal corresponding to the logical value 0. Then, the switching transistor Tr5 is turned on (conducted) by applying the voltage of the resistor R32 based on the signal corresponding to the logical value 1. As a result, the check signal Sig1 (check current) is injected into the one short circuit detection circuit Xa through the switching transistor Tr5.

The second and third check signal comparison circuits 79 and 80
Is the same as the first check signal generation circuit 78, and Sig2 and Sig3 are respectively connected to the second and third short circuit detection circuits X.
b, Xc.

Next, the check signal comparison circuit 81 will be described.

The output terminals of the knot circuits 32 in the first to third check signal generating circuits 79 to 80 are connected to the input terminals of the OR circuit 33. Further, a resistor R is provided between the output terminal P1 of the power supply circuit 97 and the negative terminal of the full-wave rectifier 3 described later.
The series circuit of 33 to R35 and the series circuit of the resistor R36 and the collector / emitter of the switching transistor Tr6 are connected in parallel with each other.

The output terminal of the OR circuit 33 is connected to the positive terminal of the resistor R34, and the positive terminal of the resistor R35 is connected to the base terminal of the switching transistor Tr6. A capacitor C11 is connected between both terminals of the resistor R35.

The capacitor C11 is connected to the short circuit detection circuits Xa, Xb,
Xc and short circuit determination circuit check signals Sig1 to Sig
3 flows, so that the short circuit detection circuits Xa, Xb, X
The capacitance is set so that the time delay determined based on the photocoupler PC of c, the capacitor C3, and the like and the time delay of the check signal flowing through the check signal comparison circuit 81 match each other.

A series circuit of knot circuits 34 and 35 is connected to the collector terminal of the switching transistor Tr6, and the output terminal of the knot circuit 35 is connected to one input terminal of a NAND circuit 36.

Further, the output terminal of the knot circuit 35 and the NAND circuit 3
A series circuit of resistors R37, R38 and a knot circuit 37 is connected between the other input terminal of 6, and a capacitor C is provided between the positive terminal of the resistor R38 and the negative terminal of the full-wave rectifier 3.
12 are connected.

A knot circuit 39 is connected between the output terminal of the NAND circuit 36 and one input terminal of the AND circuit 38.
An AND circuit 40 is connected to the output terminal of the knot circuit 39.
One of the input terminals is connected, and the other input terminal of the AND circuit 38 is connected to the other input terminal of the knot circuit 1 in the short circuit determination circuit.
2 output terminals are connected. Further, a knot circuit 41 is connected between the output terminal of the AND circuit 38 and the other input terminal of the AND circuit 40.

One input terminal of the AND circuit 43 is connected to the output terminal of the knot circuit 39 via the knot circuit 42, and the other input terminal of the AND circuit 43 is connected to the output terminal of the AND circuit 38. There is. Further, both output terminals of the AND circuit 40 and AND circuit 43 are connected to the input terminal of the OR circuit 44.

The knot circuits 41, 42, AND circuits 38, 40, 4
3 and the OR circuit 44 constitute a mismatch circuit 83.

Therefore, the check signal comparison circuit 81 uses the OR circuit 33.
A check signal corresponding to the logical value 1 is applied to and the signal corresponding to the logical value 1 is output. With this output, the switching transistor Tr6 is turned on because the voltage of the resistor R35 is applied to the base terminal. Then, the signal corresponding to the logical value 0 is applied to the knot circuit 34 at the next stage, and the knot circuit 34 applies the signal corresponding to the logical value 1 to the knot circuit 35 based on the signal corresponding to the logical value 0. .

The knot circuit 35 applies the signal corresponding to the logical value 0 to one terminal of the NAND circuit 36 based on the signal corresponding to the logical value 1. A signal corresponding to a logical value 0 is applied to the knot circuit 37 after being delayed by the time constant of the resistor R37 and the capacitor C12, and the knot circuit 37 outputs the other signal of the nut circuit 36 based on the signal corresponding to the logical value 0. A signal corresponding to the logical value 1 is applied to the terminal of.

Then, the NAND circuit 36 applies one pulse signal corresponding to the logical value 0 to the knot circuit 39 based on the signals applied to both terminals. Then, the knot circuit 39 applies the signal corresponding to the logical value 1 to one terminal of the AND circuit 38 and the AND circuit 40 based on the pulse signal corresponding to the logical value 0.

Thus, when the signal corresponding to the logical value 1 is applied to the OR circuit 33, the knot circuit 39 applies the signal corresponding to the logical value 1 to the next stage.

Further, at this time, when the short circuit detection circuits Xa, Xb, Xc and the short circuit determination circuit are normal, the AND circuit 38 inputs the check signal injected into the short circuit detection circuits Xa, Xb, Xc and the short circuit determination circuit to the other input terminal. The signal corresponding to the logical value 1 is input based on Sig1 to Sig3, and the signal corresponding to the logical value 1 is applied to one input terminal of the knot circuit 41 and the AND circuit 43 at the next stage.

The knot circuit 41 outputs the signal corresponding to the logical value 0 based on the signal corresponding to the logical value 1 to the AND circuit 40 of the next stage.
The AND circuit 40 applies a signal corresponding to the logical value 0 to one input terminal of the OR circuit 44.

On the other hand, when the knot circuit 39 applies a signal corresponding to a logical value of 1 from the knot circuit 39, the knot circuit 42 applies a signal corresponding to a logical value of 0 to one input terminal of the AND circuit 43. The result AND circuit 43 applies the signal corresponding to the logical value 0 to the other input terminal of the OR circuit 44 based on the signal corresponding to the logical value 1 and the signal corresponding to the logical value 0 from the AND circuit 38. .

Since a signal corresponding to a logical value 0 is applied to both input terminals of such an OR circuit 44, a signal corresponding to a logical value 0 is applied to the AND circuit 45 of the next stage described later.

Therefore, in the mismatch circuit 83, the AND circuit 38
When a signal corresponding to the logical value 1 from the knot circuit 39 is applied to one input terminal and a signal corresponding to the logical value 1 is applied to the other input terminal of the AND circuit 38, that is, both inputs. When the signals corresponding to both logical values 1 applied to the terminals have the same pulse width, the OR circuit 44 applies the signal corresponding to the logical value 0 to the next stage to display the check indicator Hc described later. It is designed not to let you.

On the contrary, when the short-circuit detection circuits Xa, Xb, Xc and the short-circuit discrimination circuit are in an abnormal state, that is, in the case of disconnection, the AND circuit 38 inputs the switch signal injected into the short-circuit detection circuit and the short-circuit discrimination circuit to the other input terminal. The signal corresponding to the logical value 0 is input to the knot circuit 41 and the AND circuit 43 at the next stage to one input terminal by inputting the signal corresponding to the logical value 0 based on

Then, the knot circuit 41 applies the signal corresponding to the logical value 1 to the AND circuit 40, and the AND circuit 40 applies the signal corresponding to the logical value 1 to one terminal of the OR circuit 44. Further, at this time, the AND circuit 43 applies the signal corresponding to the logical value 0 to both input terminals, and thereby applies the signal corresponding to the logical value 0 to the other input terminal of the OR circuit 44.

As a result, the OR circuit 44 applies the signal corresponding to the logical value 1 to the AND circuit 45 described later.

That is, in the mismatch circuit 83, the AND circuit 3
When a signal corresponding to the logical value 1 from the knot circuit 39 is applied to one of the input terminals of 8 and a signal corresponding to the logical value of 0 is applied to the other input terminal of the AND circuit 38, the OR circuit 44 A signal corresponding to the logical value 1 is applied to the next stage to display the check indicator Hc described later.

Further, the pulse width of the signal corresponding to the logical value 1 applied from the knot circuit 12 to one input terminal of the AND circuit 38 of the mismatch circuit 83 and the signal corresponding to the logical value 1 applied from the knot circuit 39. If the pulse width is different from the pulse width of the above, the non-coincidence circuit 83 applies the signal corresponding to the logical value 1 from the OR circuit 44 to the next stage in the same manner as described above.

When the check signal (check current) is not applied to the check signal comparing circuit 81 from the check signal generating circuits 78 to 80, the logic circuits 33 to 37 are operated when the check current is injected to the check signal comparing circuit 81. In order to apply a signal corresponding to a logical value opposite to that to the next stage, the knot circuit 39 applies a signal corresponding to a logical value 0 to one input terminal of the AND circuit 38.

Therefore, in this state, whichever of the signal corresponding to the logic value 1 or the signal corresponding to the logic value 0 is applied to the other input terminal of the AND circuit 38, the AND circuit 38 is set to the logic value 0 in the next stage. Apply the corresponding signal. As a result, a signal corresponding to a logical value of 0 is applied to both knot circuits 41 and 42 of the mismatch circuit 83, and a signal corresponding to a logical value of 1 is applied to one input terminal of both AND circuits 40 and 43 in the next stage. Apply.

At this time, a signal corresponding to a logical value 0 is applied from the knot circuit 39 to the other input terminal of the AND circuit 40, and a signal corresponding to a logical value 0 is applied to the other input terminal of the AND circuit 43. Both AND circuits 4
0 and 43 apply a signal corresponding to a logical value 0 to the OR circuit 44. As a result, the OR circuit 44 applies the signal corresponding to the logical value 0 to the next stage.

Next, the check indicator switching circuit 82 will be described.

A series circuit of the collector / emitter of the switching transistor Tr7 and the set terminal 19 / common terminal 20 of the short-circuit control circuit check indicator Hc is connected between the output terminal P1 of the power supply circuit 97 and the negative terminal of the full-wave rectifier 3. .

A resistor R39, between the base terminal of the switching transistor Tr7 and the output terminal of the OR circuit 44,
A series circuit of R40, an AND circuit 45, and a resistor R41 is connected, and a series circuit of a diode D6 and a resistor R42 in opposite directions is connected between both terminals of the resistor R39.

Further, a capacitor C13 is connected between the negative terminal of the resistor R39 and the negative terminal of the full-wave rectifier 3, a resistor R43 is connected between the negative terminal of the resistor R41 and the negative terminal of the full-wave rectifier 3, and the resistor R43. Is applied to the base terminal of the switching transistor Tr7.

The AND circuit 45, resistors R39 to R43, diode D6 capacitor C13 and switching transistor T
The check display switching circuit 82 is configured by r7.

A drive flywheel diode D7 is connected between the set terminal 19 and the common terminal 20 of the check indicator Hc, and a return drive flywheel diode D8 is connected between the reset terminal 21 and the common terminal 20. .
Further, the P1 terminal of the power supply circuit 97 and the check indicator H
A series circuit of a resistor R45 and a switch S2 is connected between the reset terminals of c, and a capacitor C14 is connected between both terminals of the return drive flywheel diode D8.

By turning on the switch S2, the chuck display Hc in the abnormal display state can be reset and the normal display state can be restored.

Therefore, when the AND circuit 45 receives the signal corresponding to the logical value 0 from the OR circuit 44, it applies the signal corresponding to the logical value 0 to the resistor R43, and the switching transistor Tr7 is turned off.

On the contrary, when the AND circuit 45 receives a signal corresponding to the logical value 1 from the OR circuit 44, the AND circuit 45 outputs the logical value 1
Is applied to the next stage, and the voltage of the resistor R43 is applied to the base terminal of the switching transistor T.
The r7 is turned on, and the display drive current is supplied to the check display Hc via the set terminal 19.

VII. Check indicator Hc has almost the same structure as the short-circuit indicator Ha, and when a display drive current flows through the set terminal 19 and the common terminal 20, a drive coil (not shown) is displayed.
Is excited, a mark attached to the back surface of the disk is displayed on the outside to indicate that the short-circuit detection circuit or the short-circuit determination circuit is abnormal.

On the contrary, when the display return drive current flows through the common terminal 20 and the reset terminal 21, the check display Hc causes the return drive coil (not shown) to be excited, so that the mark attached to the surface of the disk is exposed to the outside. Displayed, indicating that the status is normal.

VIII. Display Lock Circuit Next, the display lock circuit 76 will be described.

A series circuit of an OR circuit 46, resistors R46 and R47, and an AND circuit 47 is connected between the output terminal of the knot circuit 35 and the other input terminal of the AND circuit 17 which constitutes the drive circuit of the short-circuit indicator Ha.

In addition, a series circuit of a diode D9 and a resistor R48 in opposite directions is connected in parallel between both terminals of the resistor R46, and a capacitor C is provided between the positive terminal of the resistor R47 and the earth line E2.
15 is connected. The resistor R46 and the capacitor C15 form a CR integrator circuit.

Therefore, when the check signal (check current) does not flow to the check signal comparison circuit 81, the knot circuit 3
Since the signal corresponding to the logical value 1 from 5 is applied to the OR circuit 46, the OR circuit 46 outputs the signal corresponding to the logical value 1 and based on the time constant from the CR integrating circuit of the resistor R46 and the capacitor C15. AND circuit 47 has a logical value of 1
The signal corresponding to is applied. As a result, the AND circuit 4
7 applies a corresponding signal with a logical value of 1 to the other input terminal of the AND circuit 17.

On the other hand, when a check signal (check current) is flowing to the check signal comparison circuit 81, the signal corresponding to the logical value 0 is applied from the knot circuit 35 to the OR circuit 46, so that the OR circuit 46 outputs the logical value. A signal corresponding to 0 is output, and a signal corresponding to a logical value 0 is applied to the AND circuit 47 based on the time constant from the CR integrating circuit of the resistor R46 and the capacitor C15. As a result, the AND circuit 47 applies a signal corresponding to the logical value 0 to the other input terminal of the AND circuit 17.

IX. Phase Comparison Discrimination Circuit Next, the phase comparison discrimination circuit 84 will be described.

The phase comparison / discrimination circuit 84 is connected to the output terminals P2 and P3 of the zero-phase current transformer 85 and to the output terminals P4 and P5 of the zero-phase voltage detector 86.

In FIG. 2, the in-phase comparison / discrimination circuit 84 includes a zero-phase current detection signal output via the surge absorbing circuit 87 when the zero-phase current transformer 85 detects a zero-phase current, and the zero-phase voltage detector 8
When 6 receives the zero-phase voltage detection signal output via the surge absorbing circuit 88 when the zero-phase voltage is detected, the phase comparison circuit 89 compares the phases of the zero-phase current and the zero-phase voltage based on both signals. I am supposed to do it.

The phase discriminating circuit 90 determines that the ground fault point is on the right side of the display when it is on the right side according to the direction of the phase comparison by the phase comparison circuit 89, or the ground fault is on the left side. A control signal is output assuming that the failure point is on the left side of the display.

The switching circuit 91 is turned on based on the control signal of the phase discrimination circuit 90. Further, the signal memory circuit 92 responds to the ON operation of the switching circuit 91, and outputs the discrimination signal corresponding to the logical value 1 from the right side display output terminal P6 for a certain period of time in the case of the right side display depending on the direction. ing. Further, the signal memory circuit 92 responds to the ON operation of the switching circuit 91, and in the case of the left side display, the ground fault fault point indicates that the display is on the left side and the discrimination signal corresponding to the logical value 1 from the left side display output terminal P7. Is output for a certain period of time.

The surge absorption circuits 87, 88, the phase comparison circuit 89, the phase discrimination circuit 90, the switching circuit 91 and the signal memory circuit 92 constitute a phase comparison discrimination circuit 84.

X. Drive Circuit for Ground Fault Direction Indicator The drive circuit for the ground fault direction indicator is composed of a drive circuit for driving the right direction indicator Hb1 and a drive circuit for driving the left direction indicator Hb2.

Since the driving circuits for driving and displaying the respective directional indicators Hb1 and Hb2 have the same configuration, the driving circuit of the right directional indicator Hb1 will be described for convenience of explanation, and the left directional indicator Hb will be described.
Regarding the circuit elements and the logic circuit forming the driving circuit of No. 2, 100 is added to the reference numerals assigned to the circuit elements and the logic circuit forming the driving circuit of the right direction indicator Hb1, and the description thereof is omitted.

An input terminal of an AND circuit 48 as a ground fault detection gate circuit is connected to the right side display output terminal P6, and when a judgment signal corresponding to the logic ground 1 is input from the right side evaluation output terminal P6, the logic ground is output from the output terminal. A switch signal corresponding to 1 is applied.

The output terminal of the AND circuit 48 is connected to one input terminal of the NAND circuit 50. Also, the AND circuit 4
A series circuit of resistors R49, R50 and a knot circuit 51 is connected between the output terminal of No. 8 and the other input terminal of the NAND circuit 50, and a capacitor C16 is provided between the positive terminal of the resistor R50 and the negative terminal of the full-wave rectifier 3. Are connected. A knot circuit 52 is provided at the output terminal of the NAND circuit 50.
Are connected.

Further, between the output terminal P1 of the power supply circuit 97 and the negative terminal of the full-wave rectifier 3, the collector / emitter of the switching transistor Tr8 and the set terminal 1 of the right direction indicator Hb1.
9. A series circuit of the common terminal 20 is connected. Further, the drive flywheel diode D10 is connected between the set terminal 19 and the common terminal 20 of the right direction indicator Hb1, and the return drive flywheel diode D11 is connected between the reset terminal 21 and the common terminal 20. .

The output terminal of the knot circuit 52 is connected to the base terminal of the switching transistor Tr8 via a resistor R51, and a resistor R52 is connected between the negative terminal of the resistor R51 and the negative terminal of the full-wave rectifier 3. The voltage of the resistor R52 is applied to the base terminal of the switching transistor Tr8.

The knot circuits 50 and 52, the NAND circuit 50, and the resistor R4
9 to R52 and the switching transistor Tr8 constitute a right side display switching circuit 100.

The voltage amplifier circuit 101 will be described. An output terminal P1 (plus terminal) of a power supply circuit 97 and a full-wave rectifier 3 described later.
A resistor R53 and a transistor Tr9 are connected between the negative terminals of
A series circuit of collector and emitter of is connected. A resistor R54 is connected between the base terminal of the transistor Tr9 and the collector terminal of the switching transistor Tr8.

Further, the negative terminal of the resistor R54 and the full-wave rectifier 3
A resistor R55 is connected between the negative terminals of the resistor R55 and the voltage of the resistor R55 is applied to the base terminal of the transistor Tr9.

The resistors R53 to R55, the knot circuit 53, and the transistor Tr9 form a voltage amplifier circuit 101.

Next, the display restoration switching circuit 102 for driving the direction indicator Hb1 for the restoration display will be described.

Between the output terminal P1 of the power supply circuit 97 and the negative terminal of the full-wave rectifier 3, the collector / emitter of the switching transistor Tr10 is reset to the right display Hb1 by the reset terminal 2
Connected to 1. Same switching transistor Tr
Between the base terminal of 10 and the knot circuit 56 of the timing circuit 93 described later, one input terminal of the OR circuit 54 and the resistor R56.
The series circuit of is connected.

A resistor R57 is connected between the negative terminal of the resistor R56 and the negative terminal of the full-wave rectifier 3, and the voltage of the resistor R57 is applied to the base terminal of the switching transistor Tr10. The other terminal of the OR circuit 54 is a knot circuit 153 for the left direction indicator Hb2.
Is connected to the output terminal of.

Further, a knot circuit 53 is connected to the collector terminal of the transistor Tr9, the knot circuit 53 is connected to one input terminal of an OR circuit 154 for the left direction indicator Hb2, and an OR circuit in a time limit circuit 93 described later. 55 to one input terminal.

The output terminal of the knot circuit 153 for the left direction indicator Hb2 is connected to the other input terminal of the OR circuit 55 in the time limit circuit 93.

The OR circuit 54, the resistors R56 and R57, and the switching transistor Tr10 constitute a display restoration switching circuit 102.

Therefore, when the signal Sig6 corresponding to the logical value 1 as the display return signal is applied from the knot circuit 56 of the time limit circuit 93 to the OR circuit 64, the OR circuit 54 outputs the logical value 1 to the next stage.
The signal corresponding to is applied. Then, the voltage of the resistor R57 is applied to the base terminal of the switching transistor Tr10, so that the switching transistor Tr1
0 is turned on, and the display recovery drive current is supplied from the switching transistor Tr10.

In the drive circuit for the left direction indicator Hb2, when the switching transistor Tr108 is turned on, the voltage of the resistor R155 in the voltage amplification circuit 201 is applied to the base terminal of the transistor Tr109 so that the transistor Tr109 is turned on. To do. Then, since the signal corresponding to the logical value 0 is applied to the knot circuit 153, the knot circuit 153 applies the signal corresponding to the logical value 1 to the other input terminal of the OR circuit 54, thereby performing the same operation as described above. The OR circuit 54 applies a signal corresponding to the logical value 1 to the next stage.

Thereafter, the switching transistor Tr1 operates similarly.
A display return drive current is supplied from 0.

XI. Ground fault direction indicator A pair of right direction direction indicator Hb1, which constitutes the ground fault direction indicator.
The left direction indicator Hb2 has the same structure as the short-circuit indicator Ha, and when a ground fault display drive current flows to both the indicators Hb1 and Hb2 via the set terminal 19, each drive coil (not shown) is turned on. By being excited, the marks attached to the back surface of each disk are simultaneously displayed to the outside (ground fault direction display).

On the contrary, the reset terminal 21 is attached to both the indicators Hb1 and Hb2.
When a display return drive current flows through the display drive coils, the return drive coils (not shown) are excited, so that the markers attached to the surface of each disk are constantly displayed all at once outside.

XII. The time limit control circuit and the time limit circuit time limit control circuit 104 will be described.

The oscillation holding circuit 105 shown in FIG. 1B is an OR circuit 55.
When a signal corresponding to the logical value 0 is input via the, the signal corresponding to the logical value 1 is output to the next stage based on the signal corresponding to the logical value 0. Logical value 0 → 1 via 55 (Sig4, Sig
5, when a signal corresponding to Sig7) is input, a signal corresponding to the logical value 1 → 0 is input to the IC 57 based on the signal.
The output signal is output to the clear terminal 96 of the IC 57 to cause the IC 57 to start oscillating.

Further, when the oscillation holding circuit 105 inputs a signal corresponding to the logical value 1 from the holding release circuit 106 described later while outputting the signal corresponding to the logical value 0 as described above, the logical value is output from the output side. A signal corresponding to 1 is output.

Further, when the oscillation holding circuit 105 inputs a signal corresponding to the logical value 1 from the holding release circuit 106 described later while outputting the signal corresponding to the logical value 0 as described above, the logical value is output from the output side. A signal corresponding to 1 is output.

Specifically, the oscillation holding circuit 105 is as shown in FIG. 2 (c).

That is, one input terminal of the OR circuit 107 is connected to the output terminal of the OR circuit 55, and the output terminal of the OR circuit 107 is connected to one input terminal of the AND circuit 108. The other input terminal of the AND circuit 108 is connected to an output terminal of an AND circuit 112 of a holding release circuit 106 described later via an inverter 109. The output terminal of the AND circuit 108 is connected to the clear terminal 96 of the IC 57 via the knot circuit 110.

The OR circuit 107, the AND circuit 108, the inverter 1
09 and the knot circuit 110, the oscillation holding circuit 10
5 are configured.

Next, the holding release circuit 106 shown in FIG.
The output side outputs a signal corresponding to a logical value of 0 to the oscillation holding circuit 105 when the oscillation maintaining state continues. Further, when the signal Sig6 (display restoration signal) corresponding to the logical value 1 is input from the knot circuit 56, the signal corresponding to the logical value 1 is output from the output side thereof.

Specifically, the holding release circuit 106 is as shown in FIG. 2 (c). That is, the output terminal of the knot circuit 56 is connected to the input terminal of the AND circuit 111, and the output terminal of the AND circuit 111 is connected to the output terminal of the AND circuit 112 via the series circuit of the resistors R105 and R106. Further, a series circuit of a diode D100 and a resistor R107 in opposite directions is connected between both terminals of the resistor R105, and the negative terminal of the resistor R105 is a capacitor C.
It is connected to the ground wire E3 via 100.

AND circuits 111 and 112, resistors R105 and R10
6, R107, diode D100 and capacitor C1
00 together constitute a holding release circuit 106.

Next, the time limit circuit 93 will be described.

The IC 57 has a resistor R58, a capacitor C17, and a resistor 59.
Is connected to the IC circuit 57, and the IC 57 divides the number of oscillations of the oscillation circuit 95. IC
One input terminal of a NAND circuit 58 is connected to the output terminal of 57, and the output terminal of the IC 57 and the NAND circuit 58 are connected.
A series circuit of resistors R62, R63 and a knot circuit 62 is connected between the other input terminals of the capacitor R1 and a capacitor C1 between the positive terminal of the resistor R62 and the negative terminal of the full-wave rectifier 3.
8 is connected. A knot circuit 56 is connected to the output terminal of the NAND circuit 58, and the output terminal of the knot circuit 56 is connected to the OR circuit 60.

The resistors R62 and R63, the capacitor C18, the knot circuits 56 and 62, and the NAND circuit 58 form a display restoration signal generation circuit 103.

When the IC 57 receives a signal corresponding to a logical value 0 from the oscillation holding circuit 105, the IC 57 starts oscillating the oscillation circuit 95. If the IC 57 is divided into a predetermined number,
The signal corresponding to the logical value 1 is applied to one terminal of the NAND circuit 58 from the output terminal.

Further, a signal corresponding to the logical value 1 is applied to the knot circuit 62 after being delayed by the time constant of the resistor R62 and the capacitor C18, and the knot circuit 62 outputs the other signal of the NAND circuit 58 based on the signal corresponding to the logical value 1. A signal corresponding to a logical value of 0 is applied to the terminal. Then, the NAND circuit 58 applies one pulse signal corresponding to the logical value 1 to the knot circuit 56 based on the rising signal applied to both terminals.

Then, the knot circuit 56 applies the signal Sig6 (display restoration signal) corresponding to the logical value 1 to the OR circuits 54, 154 and 60 based on the signal corresponding to the logical value 0.

Therefore, the time-limit circuit T is retransmitted in the case where the distribution line L is in a failure accompanied by a trip of the circuit breaker in the substation, and is a fixed time after the ground fault is displayed in the case of a ground fault which is not accompanied by the trip. An output signal is output via the output terminal of the IC 57.

XIII. Power Supply Circuit Next, the power supply circuit 97 will be described.

A full-wave rectifier 63 is connected to the secondary side of the current transformer 62 whose primary side is connected to another power source. A smoothing capacitor C19 is provided between the plus and minus terminals of the full wave rectifier 63.
And a capacitor C20 are connected. A three-terminal regulator 64 is connected between the plus and minus terminals of the full-wave rectifier 63, and a capacitor C21, a diode D101, and a capacitor C21 are provided between the output terminal of the three-terminal regulator 64 and the minus terminal of the full-wave rectifier 63. C10
A parallel circuit with one serial circuit is connected. And
The positive terminal of the capacitor C101 is connected to the time period control circuit 104, so that the capacitor C101 serves as the power source of the time period control circuit 104. The capacitor C101 applies a voltage to the simultaneous limit section control circuit 104 even when the distribution line L is in a no-voltage state. A drive current is output from the output terminal of the three-terminal regulator 64 to each circuit via the output terminal P1.

A surge absorber 65 is connected between the primary side of the current transformer 62.

Operation of the Embodiment The operation of the control circuit of the short-circuit ground fault direction detection display device configured as described above will be described.

Now, when a steady load current is flowing through the distribution line L, the first to second short circuit detection circuits Xa, Xb, and Xc are slightly separated from the first to second current transformers CT1, CT2, and CT3. The transformation current is output, and the transformation current is the full-wave rectifier 3
After being full-wave rectified by the resistor R1, most of it is consumed by the resistor R1, while in the third short circuit detection circuit Xc, the resistor R1
1, consumed by the resistor R11 and the diode array Da.

Then, if no check signal (check current) is flowing from the check signal comparison circuit 81 at this time, in the display lock circuit 76, the signal corresponding to the logical value 1 from the knot circuit 35 of the check signal comparison circuit 81 is the OR circuit 46.
Since it is applied to the AND circuit 46, a signal corresponding to the logical value 1 is output, and the AND circuit 4 outputs the signal from the CR integration circuit of the resistor R46 and the capacitor C15 based on the time constant.
A signal corresponding to the logical value 1 is applied to 7. As a result, the AND circuit 47 is in a state in which the signal corresponding to the logical value 1 is applied to the other input terminal of the AND circuit 17.

In this state, for example, when a short-circuit current that can trip the circuit breaker of the substation flows in the distribution line L to which the first current transformer CT1 is attached, the first current transformer CT1 causes a first short-circuit detection circuit. The transformation current is output to Xa. The transformed current is full-wave rectified by the full-wave rectifier 3, and the photocoupler PC inputs the full-wave rectified analog signal.
Digital output is performed by the light emitting diode LED and the phototransistor PTr.

Further, when the level of the digital signal applied to the base terminal is a predetermined value, the switching transistor Tr1
Turns on and outputs the short-circuit current detection signal. And
When the switching transistor Tr1 is turned on, the voltage of the resistor R10 changes to the switching transistor Tr1.
The switching transistor Tr2 is turned on by being applied to the base terminal of No. 2.

Then, the collector of the switching transistor Tr2
Since the potential between the emitters drops, the knot circuit 7 has a logical value of 0.
Is applied to the knot circuit 7 and the knot circuit 7 has a logical value of 1
The signal corresponding to is applied to the OR circuit 8.

Further, the OR circuit 8 applies the signal corresponding to the logical value 0 to the knot circuit 9 in the next stage, and the knot circuit 9 outputs the signal corresponding to the logical value 0 based on the signal corresponding to the logical value 1 to the NAND circuit 10. Apply to one terminal. Also, the knot circuit 11 is delayed by the time constant of the resistor R15 and the capacitor C9.
A signal corresponding to a logical value of 0 is applied to the same knot circuit 1
1 applies the signal corresponding to the logical value 1 to the other terminal of the NAND circuit 10 based on the signal corresponding to the logical value 0. Then, the NAND circuit 10 applies one pulse signal corresponding to the logical value 0 to the knot circuit 12 based on the falling signals applied to both terminals.

Then, the knot circuit 12 applies a signal corresponding to the logical value 1 to the signal memory circuit 75 based on the pulse signal corresponding to the logical value 0, and the signal memory circuit 75 causes the resistor R to have a resistance R.
20, a signal corresponding to a logical value of 1 is applied to the AND circuit 13 for a certain period of time based on the time constant of the capacitor C7.

On the other hand, when the circuit breaker of the substation trips due to the short-circuit current and, as a result, the distribution line L becomes non-voltage, the voltage between the diode arrays Da in the third short-circuit detection circuit Xc becomes non-voltage. The voltage of the resistor R13 (that is, no voltage) is applied to the terminal, and the transistor Tr3 is turned off. Then, the transistor Tr
Since the 3 is off, the knot circuit 5 has a transistor T.
Since the collector-emitter potential of r3 rises, a signal corresponding to the logical value 1 is applied.

Therefore, a signal corresponding to the logical value 0 is output from the output terminal of the knot circuit 5, the inverter 6 rectangularizes the waveform based on the signal corresponding to the logical value 0, and the signal corresponding to the logical value 1 (no voltage Detection signal) is output.

Therefore, the AND circuit 13 applies the signal corresponding to the logical value 1 (non-voltage detection signal) from the non-voltage detection unit while the signal corresponding to the logical value 1 from the signal memory circuit 75 is applied. Then, a signal corresponding to a logical value 1 is applied to one terminal of the NAND circuit 15 based on both signals.

Also, the signal corresponding to the logical value 1 is applied to the knot circuit 16 after being delayed by the time constant of the resistor R21 and the capacitor C8, and the knot circuit 16 outputs the other signal of the NAND circuit 15 based on the signal corresponding to the logical value 1. A signal corresponding to a logical value of 0 is applied to the terminal. Then, the NAND circuit 15 applies one pulse signal corresponding to the logical value 1 to the knot circuit 18 based on the rising signals applied to both terminals. Then, the knot circuit 18 applies the signal corresponding to the logical value 1 to the AND circuit 17 based on the signal corresponding to the logical value 0.

At this time, the AND circuit 17 outputs the switch signal corresponding to the logical value 1 because the signal corresponding to the logical value 1 is applied to the other input terminal from the display lock circuit 76 described later. Then, the voltage of the resistor R24 is applied to the base terminal of the switching transistor Tr4 based on the switch signal, so that the switching transistor Tr4 is turned on (conducted) and the short-circuit display drive current is supplied to the short-circuit display Ha. To do.

As a result, the short-circuit indicator Ha is driven by the short-circuit display drive current.
Displays a short circuit.

On the other hand, the circuit breaker in the substation of the distribution line L goes into a non-voltage state due to the trip, the AND circuit 17 outputs the signal Sig7 corresponding to the logical value 0 → 1, and the OR circuit 55 outputs the same Sig.
Based on 7, the signal corresponding to the logical value 0 → 1 is output to the oscillation holding circuit 105. Then, the oscillation holding circuit 105 outputs a signal corresponding to the logical value 1 → 0 to the IC5 based on the signal.
7 to the clear terminal 96, and the IC 57 outputs 95
Oscillation is started, and re-division of the oscillation number is started.

Then, when the IC 57 divides by a predetermined number, a signal corresponding to the logical value 1 is applied to one terminal of the NAND circuit 58 from its output terminal. Also, a signal corresponding to a logical value 1 is applied to the knot circuit 62 after being delayed by the time constant of the resistor R62 and the capacitor C18, and the knot circuit 62 outputs the logical value 1
A signal corresponding to a logical value of 0 is applied to the other terminal of the NAND circuit 58 based on the signal corresponding to. Then, the NAND circuit 58 outputs one pulse signal corresponding to the logical value 1 based on the rising signals applied to both terminals of the knot circuit 56.
Apply to.

Then, the knot circuit 56 applies the signal Sig6 (display restoration signal) corresponding to the logical value 1 to the OR circuit 60 based on the signal corresponding to the logical value 0. Then OR circuit 6
0 is a signal Sig6 corresponding to a logical value 1 (display restoration signal)
By applying a signal corresponding to the logical value 1 to the next stage based on the above, the voltage of the resistor R65 is applied to the base terminal of the switching transistor Tr11, and the switching transistor Tr11 is turned on. As a result, the display recovery drive current is supplied from the switching transistor Tr11 to the reset terminal of the short-circuit indicator Ha.

The display return drive current resets the short-circuit indicator Ha and returns to the steady display state.

On the other hand, when the holding release circuit 106 inputs a signal corresponding to the logical value 1 from the knot circuit 56, the holding release circuit 106 outputs the logical value 1 from the output side based on this signal.
To the oscillation holding circuit 105. Then, the oscillation holding circuit 105 has a logical value of 1 based on the signal.
Output a signal corresponding to. As a result, the IC 57 stops the oscillation of the oscillation circuit 95. That is, the oscillation holding circuit 105 and the IC 57 return to the original state.

When the tripping short-circuit current flows through the distribution line L and the knot circuit 12 applies a signal corresponding to the logical value 1 to the AND circuit 38, the OR circuit 44 of the disagreement circuit 83.
Since the signal corresponding to the logical value 0 is applied to the AND circuit 45, the signal corresponding to the logical value 0 is applied to the AND circuit 45. Therefore, since the AND circuit 45 applies the signal (low potential) corresponding to the logical value 0 to the next stage, the switching transistor Tr7 remains in the OFF state and the check display Hc does not perform the display operation.

Also, when a short-circuit current capable of tripping the circuit breaker of the substation flows through the distribution line L to which the second and third current transformers CT2 and CT3 are attached, the short-circuit indicator Ha is similar to the above. A short-circuit is displayed and the time limit circuit 93 returns to the steady display state after a predetermined time.

Next, the operation of the self-diagnosis circuit 83 will be described.

When applied from the knot circuit 32 of the check signal generating circuit connected to the first short-circuit detection circuit Xa to the next stage of the signal corresponding to the logical value 1 every predetermined time, the switching transistor Tr5 causes the signal corresponding to the logical value 1 to be applied. ON operation (conduction) by applying the voltage of the resistor R32 based on
To do. As a result, this switching transistor Tr5
The check signal Sig1 (check current) is injected into the plus terminal of the light emitting diode LED of the photocoupler PC in the first short circuit detection circuit Xa via.

Now, when the first short-circuit detection circuit Xa is normal, the respective circuit elements and logic circuits operate in the same manner as when the short-circuit current is detected, so the knot circuit 12 is the AND circuit 38 of the check signal comparison circuit 81. A signal corresponding to a logical value of 1 is applied to one terminal.

In addition, the knot circuit 32 of the first check signal generation circuit 78
Since the signal corresponding to the logical value 1 is applied to the OR circuit 33 of the check signal comparison circuit 81, the OR circuit 33 applies the signal corresponding to the logical value 1 to the next stage. Then, the knot circuit 39 applies a signal corresponding to the logical value 1 to one terminal of the AND circuit 38 and the AND circuit 40 based on the operation of each circuit element and the logic circuit.

As described above, the AND circuit 38 outputs the signal corresponding to the logical value 1 to the knot circuit 12 based on the check signal Sig1 injected into the short circuit detection circuit Xa and the short circuit determination circuit at the other input terminal (that is, the one input signal). A signal having the same pulse width as the signal corresponding to the logical value 1 applied to the terminal)
Is applied. Then, the OR circuit 44 of the mismatch circuit 83
Applies a signal corresponding to a logical value 0 to the next stage.

As a result, the AND circuit 45 outputs the logical value 0 from the OR circuit 44.
Is applied to the resistor R43, the switching transistor Tr7 is in the OFF state, and the check indicator H
c does not display.

When the check signal Sig1 is injected into the first short circuit detection circuit Xa, the AND circuit 47 of the display lock circuit 76 sets the logical value 0 to the other input terminal of the AND circuit 17 in the drive circuit of the short circuit indicator Ha. Apply the corresponding signal. Therefore, regardless of whether the signal corresponding to the logical value 1 or the signal corresponding to the logical value 0 is applied to the other input terminal of the AND circuit 17, the AND circuit 17 outputs the signal corresponding to the logical value 0 to the next stage. Therefore, the switching transistor Tr4 remains off.

Therefore, the check signal Sig1 injected into the first short circuit detection circuit Xa does not cause the short circuit indicator Ha to perform a display operation.

On the contrary, when the circuit elements from the light emitting diode LED in the first short-circuit detection circuit Xa to the knot circuit 12 of the short-circuit determination circuit, and the logic circuit are disconnected, the signal corresponding to the logic value 0 from the knot circuit 12 is a mismatch circuit. Since it is applied to one input terminal of 83, the OR circuit 44 of the mismatch circuit 83 applies a signal corresponding to the logical value 1 to the next stage.

In addition, the light emitting diode L in the first short circuit detection circuit Xa
The pulse width of the signal corresponding to the logical value 1 applied from the knot circuit 12 and the check signal injected into the check signal comparison circuit 81 due to a defect in the circuit element and logic circuit from the ED to the knot circuit 12 of the short circuit determination circuit. If the pulse width of the signal corresponding to the logical value 1 applied from the knot circuit 39 to the other input terminal of the AND circuit 38 based on the above does not match, the mismatch circuit 83 operates as in the above case. The signal corresponding to the logical value 1 is applied from the circuit 44 to the next stage.

As described above, since the signal corresponding to the logical value 1 is applied to the AND circuit 45 from the OR circuit 44, the signal corresponding to the logical value 1 is applied to the resistor R43, so that the switching transistor Tr7 is turned on. The display drive current is supplied to the check display Hc via the set terminal 19.

As a result, when the drive coil (not shown) is excited in the check display Hc, a mark attached to the back surface of the disk is displayed to the outside to indicate that the short circuit detection circuit Xa or the short circuit determination circuit 70 is abnormal. Show.

The switch S2 may be turned on to restore the normal display of the check indicator Hc which is abnormally displayed as described above. Then, when a display recovery drive current is supplied from the power supply circuit 97 through the reset terminal 21, the check display Hc externally displays a mark attached to the surface of the disk by exciting the recovery drive coil (not shown). Is shown, indicating a normal state.

Although the case where the check signal Sig1 is injected into the first short circuit detection circuit Xa and the short circuit determination circuit 70 has been described above, the second check signal generation circuit 79 or the third check signal generation circuit 80 respectively checks. The same applies when the signals Sig2 and Sig3 are injected into the second short circuit detection circuit Xb or the third short circuit detection circuit Xc.

Next, the operation at the time of a ground fault will be described.

When a ground fault occurs in the distribution line L, the phase comparison / determination circuit 8
Reference numeral 4 detects the zero-phase current and the zero-phase voltage flowing through the distribution line L via the zero-phase current transformer 85 and the zero-phase voltage detector 86, and compares the phases of the zero-phase current and the zero-phase voltage.

Then, the phase comparison / determination circuit 84 determines that the ground fault point is on the right side when the phase of the zero-phase current is close to leading by, for example, 0 to 110 degrees with reference to the phase of the zero-phase voltage, and the logic from the right display output terminal P6. The judgment signal corresponding to the ground 1 is applied to the AND circuit 48 for a certain period of time.

Then, the AND circuit 48 applies a signal corresponding to the logical value 1 to one terminal of the NAND circuit 50. Further, a signal corresponding to the logical value 1 is applied to the knot circuit 51 after being delayed by the time constant of the resistor R49 and the capacitor C16, and the knot circuit 51 outputs the other signal of the NAND circuit 50 based on the signal corresponding to the logical value 1. A signal corresponding to a logical value of 0 is applied to the terminal. Then, the NAND circuit 50 applies one pulse signal corresponding to the logical value 1 to the knot circuit 52 based on the rising signals applied to both terminals.

Then, the knot circuit 52 applies the signal corresponding to the logical value 1 to the next stage based on the signal corresponding to the logical value 0,
The switching transistor Tr8 has a resistor R at its base terminal.
The ON operation is performed by applying the voltage of 52. As a result, the switching transistor Tr8 outputs the right direction display drive current as the ground fault direction display signal to the right direction display Hb1.

As a result, the rightward direction display drive current causes the rightward direction indicator Hb1 to display a ground fault.

Further, when the switching transistor Tr8 is turned on, the voltage of the resistor R55 is applied to the base terminal of the transistor Tr9, so that the transistor Tr9 is turned on and the signal applied to the base is amplified and applied to the next stage. To do. Then, the signal corresponding to the logical value 0 is applied to the knot circuit 53, and the knot path 53 applies the signal Sig4 corresponding to the logical value 1 to the next stage.

As a result, the logical value 1 is applied to the other input terminal of the OR circuit 154.
Is applied to the OR circuit 15 by applying a signal corresponding to
4 applies a signal corresponding to the logical value 1 to the next stage. Further, the OR circuit 154 applies a signal corresponding to the logical value 1 to the next stage. Then, the voltage of the resistor R157 is applied to the base terminal of the switching transistor Tr110, so that the switching transistor Tr110 is turned on. As a result, the switching transistor Tr1
10 through the reset terminal 21 to the left direction indicator Hb
A display return drive current is supplied to 2.

At this time, when the left side indicator Hb2 is normally displayed, even if the return drive coil is excited by the display return drive current, the magnetic pole portion of the stator does not change its magnetic pole, so the disk maintains the steady display state. to continue.

On the contrary, when the left direction indicator Hb2 is in the ground fault direction display state, the magnetic pole portion of the stator has a magnetic pole opposite to that in the normal display state, so the return drive coil is excited by the return drive current. At this time, the magnetic pole portion of the stator is replaced by the opposite magnetic pole, and as a result, the disk is returned to the normal display.

When the knot circuit 53 applies the signal Sig4 corresponding to the logical value 1 to the next stage, the signal corresponding to the logical value 1 is applied to the input terminal of the OR circuit 55, so that the OR circuit 55 holds the oscillation. A signal corresponding to a logical 1 is applied to the circuit 105. As a result, as in the case of the short circuit failure, I
C57 clears the division of the number of oscillations of the oscillation circuit and starts re-division of the number of oscillations.

Then, the IC 57 applies a signal corresponding to a logical value of 0 from one of its output terminals to one terminal of the NAND circuit 58 after a predetermined time division, that is, after a lapse of a predetermined time.

Thereafter, the display restoration signal generation circuit 103 operates in the same manner as when the short-circuit indicator Ha is restored and the knot circuit 56 is operated.
Applies the signal Sig6 (display return signal) corresponding to the logical value 1 to the OR circuit 54. Then, the OR circuit 54 applies a signal corresponding to the logical value 1 to the next stage, and the voltage of the resistor R57 is applied to the base terminal of the switching transistor Tr10, whereby the same switching transistor Tr1 is applied.
0 is turned on.

As a result, from the transistor Tr10 to the reset terminal 21
The display return drive current is output to the right direction indicator Hb1 via the, and the right direction indicator Hb1 returns to the display.

On the other hand, in the phase comparison / determination circuit 84, the phase of the zero-phase current is, for example, 1
When the difference is 80 to 290 degrees, the ground fault point is on the left side, and the determination signal corresponding to the logical value 1 is applied to the AND circuit 148 from the left side display output terminal P106 for a certain period of time.

Similarly to the drive circuit of the right direction indicator Hb1, the circuit elements and logic elements of the left direction indicator Hb2 operate to turn on the switching transistor Tr108, so that the left direction indicator drive current is supplied to the left direction indicator Hb2. Is output.

As a result, the left direction indicator Hb2 displays the left direction.

On the other hand, when the switching transistor Tr108 is turned on, the transistor Tr109 is turned on similarly to the drive circuit for returning the right direction indicator Hb1, and the signal applied to the base is amplified and applied to the next stage. As a result, the knot circuit 153 applies a signal corresponding to the logical value 1 to the next stage.

As a result, the OR circuit 54 forming the return drive circuit of the right direction indicator Hb1 applies the signal corresponding to the logical value 1 to the next stage to turn on the switching transistor Tr10. Then, the display return drive current is supplied from the switching transistor Tr10 to the left direction indicator Hb2 via the reset terminal 21.

At this time, when the right direction indicator Hb1 is normally displayed, even if the return drive coil is excited by the display return drive current, the magnetic pole portion of the stator does not change its magnetic pole, so the disk maintains the normal display state. to continue.

On the contrary, when the right direction indicator Hb1 is in the ground fault direction display state, the magnetic pole portion of the stator has a magnetic pole opposite to that in the normal display state, so the return drive coil is excited by the return drive current. At this time, the magnetic pole portion of the stator is replaced by the opposite magnetic pole, and as a result, the disk is returned to the normal display.

When the knot circuit 153 applies the signal Sig5 corresponding to the logic 1 to the next stage, the OR circuit 5 of the time limit circuit 93.
5 applies a signal corresponding to a logical value 1 to the clear terminal 96 of the IC 57. As a result, in the time limit circuit 93, the knot circuit 56 applies the signal Sig6 (display restoration signal) corresponding to the logical value 1 to the OR circuit 154 after a predetermined time.

Then, the OR circuit 154 applies a signal corresponding to the logical value 1 to the next stage, and the voltage of the resistor R157 is applied to the base terminal of the switching transistor Tr110, so that the switching transistor Tr110 is turned on.

As a result, the display return drive current is output from the switching transistor Tr110 to the left direction indicator Hb2 via the reset terminal 21, and the left direction indicator Hb2 returns to the display.

In this embodiment, in the short-circuit detection circuits Xa, Xb, and Xc, the photocoupler PC is used for analog input of a signal based on the short-circuit current, and the photocoupler PC is for digital output. Therefore, the phototransistor PTr of the photocoupler PC is used. It is possible to reduce the resistance value of the resistor R1 due to its high sensitivity and high speed performance.
The heat generation of No. 1 can be reduced.

Second Embodiment Next, a second embodiment will be described with reference to FIG.

The same or corresponding components as those of the first embodiment are designated by the same reference numerals and the description thereof will be omitted.

In this embodiment, in the first embodiment, the right direction indicator H
b1 and the left-side direction indicator Hb in the structure of the drive circuit for the return display drive, the resistors R53, R54, R55, the transistor Tr9 and the knot path 53, and the resistors R153, R153.
154, R155, switching transistor Tr10
9 and the knot circuit 153 are omitted. Instead, the output terminal of the knot circuit 52 in the drive circuit for display driving is connected to one input terminal of the OR circuit 154, and the output terminal of the knot circuit 152 is connected to the OR circuit 5.
4 is connected to one of the input terminals.

Therefore, in this embodiment, in the drive circuit of the right direction indicator Hb1, when the knot circuit 52 applies the signal Sig4 corresponding to the logical value 1 to the next stage, the IC 57 of the time limit circuit 93.
Starts subdividing the number of oscillations of the oscillation circuit 95. further,
In the drive circuit of the left direction indicator Hb2, when the knot circuit 152 applies the signal Sig5 corresponding to the logical value 1 to the next stage, the IC 57 of the time-limit circuit 93 starts re-dividing the oscillation number of the oscillation circuit 95.

Further, in this embodiment, the power supply circuit 9 in the configuration of the first embodiment is used.
The difference is that 7 is not provided as a separate power source but is provided in the third short circuit detection circuit Xa.

That is, the collector-emitter diode D2 of the transistor Tr20 is provided between both terminals of the diode array Da.
A series circuit of 0 and a rechargeable battery 65 is connected. A resistor R65 is connected between the collector and the base of the transistor Tr20, and a zener diode ZD is connected between the base terminal of the transistor Tr20 and the negative terminal of the full-wave rectifier 3.

The power supply circuit 97 further makes the forward voltage across the diode array Da constant by the transistor Tr20 and the Zener diode ZD, and charges the battery 65.

When a steady load current is supplied to the distribution line L, the back-up battery 65 is not consumed and the drive current is supplied to each circuit by the load current. When the circuit breaker at the substation trips and the load current no longer flows through the distribution line L, the backup battery 65 supplies the drive current required for each circuit from the output terminal P1.

Further, in the check signal generating circuits 78 to 80, a plurality of ICs 57 are used for each phase in the above embodiment,
In this embodiment, a common IC 57 is used, and resistors R66, R67 and an AND circuit are respectively provided at one input terminal of the AND circuit 29 for the second and third short circuit detection circuits Xb, Xc and a pair of output terminals of the IC 57. Sixty-six serial circuits are connected. A capacitor C22 is connected between the positive terminal of the resistor R67 and the negative terminal of the full-wave rectifier 3, and a series circuit of a diode D21 and a resistor R68 in the opposite direction is connected between both terminals of the resistor R66.

The difference from the first embodiment is that the positive terminal of the resistor R27 is connected to the output terminal of the AND circuit 66.

Therefore, in this embodiment, the number of ICs 57 used can be reduced.

In this embodiment, in the third short-circuit detecting circuit Xc, the digital output and the diode array Da connected in series to the short-circuit detecting circuit are isolated by the photocoupler PC, so that one current transformer is provided. A configuration in which the short circuit detection circuit Xc, the power supply circuit 97, and the no-voltage detection circuit 72 are connected to CT is possible.

Third Embodiment Next, a third embodiment will be described with reference to FIGS. 5 and 6.

In this embodiment, the same or corresponding components as those of the first and second embodiments are designated by the same reference numerals, and the description thereof will be omitted. Only the major differences will be described.

The detectors are first, second and third current transformers CT1, CT2 and CT3 as current detectors for the distribution line L of each phase.
And a current transformer CT for a power source are respectively attached, and the secondary side terminals of the first to third current transformers CT1, CT2 and CT3 are connected to each other to form a star circuit.
A resistor R for detecting a zero-phase current combined for three phases is connected in the star circuit, and the zero-phase detector 85 together with the first to third current detectors CT1, CT2 and CT3.
And a zero-phase voltage detector 86 for detecting the zero-phase voltage.

In the short-circuit detector, the primary side of the auxiliary current transformer CTa1 is connected between one secondary side terminal of the first current transformer CT1 and the terminal of the resistor R, and between the secondary sides thereof. Zener diode ZD, resistor R1, smoothing capacitor C
1 and the parallel circuit of the diode D are connected,
A series circuit of the diode D1 and the capacitor C2 is connected. The rectifier circuit 3 is composed of the Zener diode ZD, the resistor R1, the smoothing capacitor C1, the diode D, the diode D1 and the capacitor C2.

Therefore, when a short-circuit current flows through the distribution line L, the first current transformer CT1 outputs a transformation current via the auxiliary current transformer CTa1 based on the short-circuit current, and the rectifying circuit 3 rectifies the transformation current. . Then, the photocoupler PC inputs the rectified analog signal, and the light emitting diode L
Digital output is performed by the ED and the phototransistor PTr.

The second short-circuit detection circuit Xb and the third short-circuit detection circuit Xc are the same as the first short-circuit detection unit, and the second auxiliary current transformer CTa.
Second and third auxiliary current transformer CTa3 are provided. In the third short circuit detection circuit Xc, the phototransistor PTr, the resistors R5 and R10, the capacitor C3 are included.
And the switching transistor Tr1 is the rectifier circuit 3
Instead of being connected to the negative terminal of the full-wave rectifier 2 described later.

Next, the no-voltage detector will be described.

The full-wave rectifier 2 is connected to the secondary-side terminals P20 and P21 of the power supply detector CT, and the positive terminal of the full-wave rectifier 2
A smoothing capacitor C30 and a capacitor C31 are connected between the negative terminals. Further, the place where the series circuit of the resistors R12 and R13 is connected between the positive terminal and the negative terminal of the full-wave rectifier 2 is the first in the no-voltage detector.
This is different from the configuration of the embodiment.

Therefore, in this embodiment, the short circuit detection circuits Xa, Xb, Xc
In the above, since the photocoupler PC tries to input an analog signal based on the short-circuit current and the photocoupler PC outputs a digital signal, the auxiliary transformers CTa1 and CTa2 are provided due to the high sensitivity and high speed performance of the phototransistor PTr of the photocoupler PC. , CTa3 can output the transformed current without fail.

The control circuit of the short-circuit ground fault detection and display device has primary insulation for the distribution line L by the first current transformer CT1 to the third current transformer CT3 and the current transformer CT for power supply, and the auxiliary current transformer. Secondary insulation is achieved by the devices CTa1 to CTa3, and further tertiary insulation is achieved by the photocoupler PC. Therefore, the reliability of the insulating property of the control circuit can be improved.

As described above, in this embodiment, the auxiliary transformers (CTa) are inserted in the star circuits respectively, and the auxiliary current transformers (CTa) are inserted in the star circuits respectively. Side converted impedance Z = Z '/ n 2 n; CTa turn ratio Z'; Secondary side impedance The secondary side impedance of CTa can be increased and the star circuit can be insulated, so that it wraps around. The influence of electric current can be eliminated. Therefore, the circuit configuration is simplified and the insulation reliability of the control circuit is improved.

It should be noted that the present invention is not limited to the above-mentioned embodiment, and can be arbitrarily modified within a range not departing from the spirit of the present invention.

As described in detail above, according to the present invention, the self-diagnosis circuit self-diagnoses the short-circuit detection control circuit, and when the short-circuit detection control circuit has a defect, the check indicator abnormally displays. The device can be found in regular inspections. Therefore, it is possible to eliminate the uncertain factor that the conventional display device has, that is, the adverse effect of the defect detection display device on finding the failure point of the distribution line. Moreover, while the self-diagnosis circuit is diagnosing a circuit failure, the operation of the display drive circuit is locked by the display lock circuit even if a short circuit current flows through the distribution line, and the check display is given priority before the short circuit display. It is possible to reduce the probability that a short-circuit display is made while the circuit failure check is omitted, and it is possible to improve the reliability of the short-circuit display by the short-circuit indicator. Moreover, even if a distribution line failure occurs without regular inspection, whether the detection display device is operating normally or abnormally can be easily confirmed by checking the detection operation status and the failure diagnosis display. The excellent effect of improving the reliability for early detection of a failure point is achieved.

[Brief description of drawings]

FIG. 1 is an electric block circuit diagram of a short-circuit ground fault direction detection display device embodying the present invention. (A) is an electric block circuit diagram of a main part of the present invention, and (b) is an electric block circuit of a time circuit. 2 (a), 2 (b), and 2 (c) are electric circuit diagrams of the short-circuit ground fault direction detection display device, FIG. 2 (a) is an electric circuit diagram of a main part of the present invention, and FIG. Power supply circuit diagram,
(C) is a time section control circuit diagram, FIG. 3 is a schematic view of a short-circuit indicator, FIG. 4 is an electric circuit diagram of the second embodiment, FIG. 5 is a block circuit diagram of the third embodiment, and a sixth. Similarly, FIGS. (A) and (b) are an electric circuit diagram of a main part and a power circuit diagram, respectively. 68 ... Short-circuit detector, 69 ... No-voltage detector, 70 ... Short-circuit discriminating circuit, 71 ... Current discriminating switching circuit, 72 ... No-voltage detecting circuit, 73 ... Second waveform operating circuit, 74 ... First waveform operating circuit , 76 ... Display lock circuit, 77 ... Self-diagnosis circuit, 78 ... First check signal generating circuit, 79 ... Second check signal generating circuit, 80 ... Third check signal generating circuit, 81 ... Check signal comparing circuit, 82 ... Check indicator drive circuit, 83 ... Mismatch circuit, 93 ... Time circuit, 95 ... Oscillation circuit, 97 ... Power supply circuit, 98 ... Short circuit display switching circuit as display drive circuit, 99 ... Display recovery switching circuit, Xa … First short circuit detection circuit, X
b ... second short-circuit detection circuit, Xc ... third short-circuit detection circuit,
Ha ... Short-circuit indicator, Hb1 ... Right direction indicator, Hb2 ...
Left direction indicator, Hc ... check indicator, CT1 ... first current transformer, CT2 ... second current transformer, CT3 ... third current transformer, L ... distribution line.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Katsunori Aoki No.1 Kamikonee, Inuyama City, Aichi Prefecture Takamatsu Denki Seisakusho Co., Ltd. (72) Inventor, Mitsuharu Kutomi No.1 Kamikonee Needle, Inuyama City, Aichi Takamatsu Denki Works Ltd. 56) References Japanese Unexamined Patent Publication No. 58-33330 (JP, A) Actually developed 58-72670 (JP, U)

Claims (1)

[Claims] 1. A short circuit detection control circuit which outputs a control signal based on a detection signal output from a current detector when a short circuit current flows through a distribution line, and a short circuit indicator based on a control signal from the control circuit. In a short-circuit detection display device including a display drive circuit for driving, a check signal generation circuit that constantly generates a check signal every predetermined time is injected into the short-circuit detection control circuit.
A self-diagnosis circuit including a check signal comparison circuit that operates a check indicator based on two signal comparisons is connected, while the check signal comparison circuit and the display drive circuit are connected when the check signal comparison circuit operates. A display lock circuit that locks the operation of the display drive circuit is connected, the check signal generation circuit individually injects a check signal to the short circuit detection control circuit and the check signal comparison circuit, and the check signal comparison circuit determines the check signal. The check signal injected from the generation circuit is compared with the signal output from the control circuit to the check signal comparison circuit based on the check signal injected into the short-circuit detection control circuit, and the two match. When the two signals do not match, the check indicator is displayed normally, and when the two signals do not match, the check indicator is displayed abnormally. A control circuit for a short-circuit detection display device, characterized in that