JPH0646208B2 - Control circuit for signal injection type short-circuit / ground fault detector - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention displays a short-circuit when a short-circuit current flows through a distribution line, and when a ground fault occurs in the distribution line. The present invention relates to a control circuit for a signal injection type short-circuit / ground fault detection device that displays a ground fault based on a search signal injected from a search signal injection device into a distribution line so as to detect a ground fault point that has occurred in the distribution line. It is a thing.

(Prior Art) Conventionally, when a ground fault occurs in a distribution line, first open a substation circuit breaker, and then open a substation circuit breaker from the viewpoint of early detection of an accident section, separation of a failure section and early transmission of a sound section. The substation circuit breakers are re-closed when a ground fault fault area is reached by reclosing the power supply line and re-closing the power supply side section switches sequentially. Then, when the circuit breaker of the substation is closed again, the division switch that divides the ground fault section is locked in the open state, only the ground fault section is separated, and power is retransmitted only in the sound section. , Searching for a ground fault section. When a ground fault fault section can be searched, the ground fault point is detected by repeatedly executing the insulation resistance measurement of the related distribution equipment provided on each utility pole in the fault section.

As described above, in the past, after the ground fault fault section was known, the related distribution equipment installed on the utility pole or the like existing in the ground fault fault section was subjected to sequential insulation resistance measurement for each utility pole. There is a work problem that it takes time,
There is a drawback that it takes time to detect the ground fault point.

Therefore, the present applicant has filed a patent application No. 6 in order to solve the above problems.
No. 0-8087 of the signal injection type short-circuit / ground fault detector is proposed.

This signal injection type short-circuit / ground fault detector detects the short-circuit current through the current detector when a short-circuit current flows through the distribution line, outputs the short-circuit current detection signal, and when the breaker of the substation trips. A short circuit detection circuit that detects a no-voltage state of the distribution line via a current detector and outputs a no-voltage detection signal, the short-circuit current detection signal, and the switch signal when the non-voltage detection signal is input together. A gate circuit that outputs, a search signal detection circuit that outputs a detection signal when a search signal injected into a distribution line at the time of a ground fault is detected via the current detector, and a switch signal output by the gate circuit or An ON operation is performed based on a detection signal output from the search signal detection circuit, a display drive current is output, and a display switching circuit that causes a failure display on the display, and the display performs a failure display. And a timing circuit for outputting a display return signal for causing the constant display return the display after the lapse of the rear predetermined time display.

Then, the signal injection type short circuit / ground fault detection device is always switched to a standby state for detecting a short circuit, and when the circuit breaker of the substation trips at the time of a ground fault and the distribution line has no voltage, The first relay drive circuit closes the normally open contact to switch the circuit to the search signal detection circuit side which detects the search signal.

Further, after switching to the search signal detection circuit side, the second relay drive circuit is driven again based on the signal from the time-limit circuit for returning the display to the normal display or the steady load current flowing in the distribution line. It is designed to switch to the short-circuit detection circuit side.

(Problems to be Solved by the Invention) The short-circuit / ground-fault detection device configured as described above performs a circuit check at the time of product inspection. The circuit state after the circuit check is the first relay drive circuit. Is operated and switched to the side of the search signal detection circuit, the state of being switched to the side of the search signal detection circuit continues until the detection device is attached to the distribution line. Therefore, in order to consume static current consumption in the state of the search signal detection circuit, if it takes a long time to install on the distribution line, the drive power supply (capacitor or battery) for the second relay drive circuit that switches the circuit is Even if the detector in the discharged state is attached to the power distribution line where a normal load current flows in the power distribution line, the second relay drive circuit may not operate and may not switch to the short circuit detection circuit side. Therefore, there is a possibility that the detection function may be hindered.

Configuration of the Invention (Means for Solving Problems) The present invention has been made to solve the above problems, and switches the current detector from the search signal detection circuit side to the short circuit detection circuit side. The second relay drive circuit is provided with a timer circuit for driving the second relay drive circuit after a predetermined time has passed since the distribution line was put into a non-voltage state.

(Operation) With the above configuration, when a short-circuit current flows in the distribution line, the display unit displays a failure, and when a ground fault occurs in the distribution line and the distribution line is in a no-voltage state, the first relay drive circuit. Switches the current detector from the short-circuit detection circuit side to the search signal detection circuit side, the search signal detection circuit detects the search signal via the current detector, based on the detection signal from the search signal detection circuit. Display the fault on the display.

Furthermore, the timer circuit drives the second relay drive circuit after a predetermined time has passed from the time when the distribution line is in a non-voltage state,
The connection of the current detector is switched from the search signal detection circuit to the short-circuit current detection circuit side.

(Embodiment) Hereinafter, a first embodiment embodying the present invention will be described with reference to FIGS.
It will be described with reference to the drawing.

The outline of the short-circuit / ground-fault detection device H attached for each phase will be described. The short-circuit / ground-fault detection device 1 detects a short-circuit current and a search signal, and a current detector detects the short-circuit current and the search signal. The control circuit that inputs various signals and outputs the display drive current and the return drive current based on the signals, and from the steady display to the fault display and from the fault display to the steady display by the drive current and the return drive current from the control circuit It is composed of a display unit H for returning.

(Current Detector) The current detector is composed of a current transformer CT, and when a short circuit current and a search signal flow in the distribution line, the transformer current is output from the secondary side thereof.

(Control Circuit) Each circuit constituting the control circuit will be described in detail with reference to the drawings.

I. Short Circuit Detection Circuit Explaining from the short circuit detection circuit X, a b contact RYb of a reset relay RY2, which will be described later, is connected between the plus and minus terminals of the full-wave rectifier 2 connected to the current transformer CT, and further the b contact. A series circuit of resistors R1 and R2 is connected between the negative terminal of RYb and the negative terminal of full-wave rectifier 2. The light emitting diode LED of the photocoupler PC is connected between the negative terminal of the b-contact RYb and the positive terminal of the resistor R2.

Between the output terminal P1 (plus terminal) of the power supply circuit Z and the minus terminal of the full-wave rectifier 2 described later, a series circuit of an emitter / collector of the switching transistor Tr1 and a resistor R4 connected through the collector is connected. ing. A series circuit of the emitter and collector of the phototransistor PTr in the photocoupler PC is connected between the output terminal P1 and the negative terminal of the full-wave rectifier 2.

A series circuit of the collector and emitter of the transistor Tr3 is connected between the output terminal P1 of the power supply circuit Z and the negative terminal of the full-wave rectifier 2 described later. A series circuit of a resistor R10 and a resistor R11 is connected between both terminals of the resistor R4, and a base terminal of the transistor Tr3 is connected to a plus terminal of the resistor R11.

Therefore, when the short-circuit current flows through the distribution line L, the current transformer CT outputs the transformed current based on the short-circuit current, and the full-wave rectifier 2 full-wave rectifies the transformed current. Then, the photo coupler PC inputs the full-wave rectified analog signal, and the light emitting diode LED and the phototransistor P.
The digital output is made by Tr. Further, when the level of the digital signal applied to the base terminal is a predetermined value, the switching transistor Tr1 is turned on and outputs a short circuit detection signal.
When the switching transistor Tr1 is turned on, the voltage of the resistor R11 is applied to the base terminal of the transistor Tr3, so that the transistor Tr3 is turned on.
Is supposed to work on.

The resistors R1, R2, R4, R10, R11, the photocoupler PC, the switching transistor Tr1, the transistor Tr3, etc. constitute a current discrimination switching circuit 42 in FIG.

In the short circuit detection circuit X, a diode array Da is connected between both terminals of the resistor R2, and the diode array D
A series circuit of resistors R7 and R8 is connected between the positive terminal side of the diode in the middle of forming a and the negative terminal of the full-wave rectifier 2.

Further, a series circuit of the collector and emitter of the transistor Tr2 is connected between the output terminal P1 of the power supply circuit described later and the negative terminal of the full-wave rectifier 2, and the positive terminal of the resistor R8 is connected to the base terminal of the transistor Tr2. ing.

The collector of the transistor Tr2 has an inverter 4A.
Of the inverter 4A is connected to the output terminal of the inverter 4A.

Then, when the distribution line L is in a steady state, the voltage between the diode arrays is divided by the resistors R7 and R8, and the transistor Tr2 becomes conductive when the voltage of the resistor R8 is applied to the base terminal. Signal is applied to the input terminal of the inverter 4A.

When the transistor Tr2 is in the conductive state, the voltage between the collector and the emitter becomes almost 0, so that the signal corresponding to the logical value 0 is applied to the input terminal of the inverter 4A and the output terminal thereof corresponds to the logical value 1. The signal is output. Then, the inverter 4B outputs a signal corresponding to the logical value 0 based on the signal corresponding to the logical value 1.

On the contrary, when the circuit breaker of the substation trips due to a short circuit or the like in the distribution line L, the voltage between the diode arrays Da becomes no voltage, so that the voltage of the resistor R8 (that is, no voltage) is applied to the base terminal of the transistor Tr2. ) Is applied,
The transistor Tr2 is turned off. Then, since the transistor Tr2 is in the off state, the voltage between the collector and the emitter rises, and the signal corresponding to the logical value 1 is applied to the inverter 4A.

Therefore, the signal corresponding to the logical value 0 is output from the output terminal of the inverter 4A, and the inverter 4B outputs the logical value 0.
The waveform is made rectangular based on the signal corresponding to, and the signal corresponding to the logical value 1 (no-voltage detection signal) is output.

The diode array Da, the resistors R7 and R8, the transistor Tr2, etc. constitute a no-voltage detection circuit 46, and the inverter 4A and the inverter 4B constitute a second waveform manipulation circuit 47.

Then, the rectifier circuit 2, the current discrimination switching circuit 42, the no-voltage detection circuit 46, and the second waveform manipulation circuit 47.
A short circuit detection circuit X is constituted by and.

II. Short Circuit Discrimination Circuit Next, the short circuit discrimination circuit 43 for inputting a short circuit detection signal which is a digital signal output from the short circuit detection circuit X will be described.

An inverter 9 is connected to the collector of the transistor Tr3, and the output terminal of the inverter 9 is the NAND circuit 1
0 is connected to one input terminal. A series circuit of resistors R12 and R13 and an inverter 11 is connected between the output terminal of the inverter 9 and the other input terminal of the NAND circuit 10, and a capacitor is provided between the positive terminal of the resistor R13 and the negative terminal of the full-wave rectifier 2. C5 is connected.

Between the output terminal of the NAND circuit 10 and one input terminal of the AND circuit 13 as a gate circuit, a series circuit of the inverter 12, the resistor R14 and the resistor R15 as the first waveform operating circuit 44 is connected. A resistor R is provided between the positive terminal of the resistor R15 and the negative terminal of the full-wave rectifier 2.
16 and the capacitor C6 are connected in parallel, and the voltage of the resistor R16 corresponding to the logical value 1 is applied to one input terminal of the AND circuit 13 for a predetermined time by the time constant of the CR circuit.

A signal memory circuit 45 is configured by the resistor R16 and the capacitor C6.

Therefore, when the signal corresponding to the logical value 0 is applied to the inverter 9, the inverter 9 applies the signal corresponding to the logical value 1 to one terminal of the NAND circuit 10. Also, the resistor R1
2 is delayed by the time constant of the capacitor C5 and the signal corresponding to the logical value 1 is applied to the inverter 11, and the inverter 11 outputs the logical value to the other terminal of the NAND circuit 10 based on the signal corresponding to the logical value 1. A signal corresponding to 0 is applied. Then, the NAND circuit 10 applies one pulse signal corresponding to the logical value 0 to the inverter 12 based on the signals applied to both terminals.

Then, the inverter 12 applies the signal corresponding to the logical value 1 to the signal memory circuit 45 based on the pulse signal corresponding to the logical value 0, and the signal memory circuit 45 causes the resistor R
16, a signal corresponding to the logical value 1 is applied to the AND circuit 13 for a certain period of time based on the time constant of the capacitor C6.

The inverter 12 (first waveform manipulation circuit), the signal memory circuit 45, the AND circuit 13 (gate circuit), and the like constitute a short circuit determination circuit 43.

III. Drive Circuit of Display Unit Next, the drive circuit of the display unit ID will be described. The output terminal of the AND circuit 13 is connected to one input terminal of the NAND circuit 15. A series circuit of resistors R17 and R18 and an inverter 16 is connected between the output terminal of the AND circuit 13 and the other input terminal of the NAND circuit 15, and the positive terminal of the resistor R18 and the negative terminal of the full-wave rectifier 2 are connected. A capacitor C7 is connected to.

An inverter 18 is connected to the output terminal of the NAND circuit 15, and the output terminal of the inverter 18 is connected to one input terminal of the OR circuit 14. Between the output terminal P1 of the power supply circuit Z and the negative terminal of the full-wave rectifier 2, a series circuit of the collector / emitter of the switching transistor Tr4 and the set terminal 19 / common terminal 20 of the display ID is connected.

The output terminal of the OR circuit 14 is connected to the base terminal of the switching transistor Tr4, and a resistor R20 is connected between the base terminal and the negative terminal of the full-wave rectifier 2 to switch the voltage of the resistor R20. The voltage is applied to the base terminal of the transistor Tr4.

A display drive power supply charging circuit 48 including a capacitor C8 is connected between the output terminal P1 of the power supply circuit Z and the negative terminal of the full-wave rectifier 2 to be described later so that the capacitor C8 is constantly charged. The positive terminal of the capacitor C8 is connected to the collector of the switching transistor Tr4. Also, the set terminal 1 for the display ID
A drive flywheel diode D3 is connected between the 9 and the common terminal 20.

Therefore, while the signal corresponding to the logical value 1 from the signal memory circuit 45 is being applied, the AND circuit 13 receives the signal corresponding to the logical value 1 (non-voltage detection signal) from the second waveform manipulation circuit 47. When applied, the NAND circuit 1 outputs a signal corresponding to a logical value 1 as a switch signal based on both signals.
5 to one terminal.

Further, a signal corresponding to the logical value 1 is applied to the inverter 16 after being delayed by the time constant of the resistor R17 and the capacitor C7, and the inverter 16 outputs the other terminal of the NAND circuit 15 based on the signal corresponding to the logical value 1. A signal corresponding to a logical value of 0 is applied to. Then, the NAND circuit 15 applies one pulse signal corresponding to the logical value 0 to the inverter 18 based on the signals applied to both terminals.

Then, the inverter 18 applies the signal corresponding to the logical value 1 to the OR circuit 14 based on the signal corresponding to the logical value 0, and the OR circuit 14 outputs the logical value 1 based on the signal corresponding to the logical value 1. The signal corresponding to is applied to the next stage.

As a result, when the voltage of the resistor R20 is applied to the base terminal of the switching transistor Tr4, the switching transistor Tr4 turns on (conducts),
The electric charge of the capacitor C8 is discharged, and the display drive current is output to the display ID.

A display switching circuit 49 is composed of the inverters 16 and 18, the NAND circuit 15, the OR circuit 14, the resistors R17, R18 and R20, the capacitor C7 and the like.

The collector / emitter of the switching transistor Tr5 is connected between the output terminal P1 of the power supply circuit Z and the reset terminal 21 of the display ID. The output terminal of the knot circuit 25 of the time limit circuit T, which will be described later, is connected to the base terminal of the switching transistor Tr5, and a resistor R23 is connected between the base terminal and the negative terminal of the full-wave rectifier 2, and the resistor R23. Is applied to the base terminal of the switching transistor Tr5.

Then, when the signal corresponding to the logical value 0 is applied to the knot circuit 25, by applying the signal corresponding to the logical value 1 as the display restoration signal to the next stage, the resistor R23 is applied to the base terminal of the switching transistor Tr5. Is applied to turn on the switching transistor Tr5. As a result, the display recovery drive current is supplied from the switching transistor Tr5 to the reset terminal 21 of the display ID.

The resistors R22 and R23 and the switching transistor Tr5 constitute a display restoration switching circuit 49, and together with the display switching circuit 50, a display ID drive unit.

IV. Display Device The display device ID will be described with reference to FIG.

This display ID is composed of a plurality of magnetic reversal displays,
In each porcelain inversion display, when a short-circuit display drive current flows through the set terminal 19, each drive coil 8 is excited and the polarity opposite to that shown in FIG. 3, that is, the magnetic pole portion 7a is S.
The magnetic pole part 7b is magnetized to the pole, and the N pole of each disk 5 is the magnetic pole part 7a (S pole) and the S pole is the magnetic pole part 7b.
Each disc 5 is rotated so as to face the (N pole).
The signs attached to the back surface 5b of the are simultaneously displayed to the outside.

On the contrary, when a return drive current flows to the display ID through the reset terminal 21, each return drive coil 14 is excited, and the magnetic pole portion 7a becomes the N pole and the magnetic pole portion 7 as shown in FIG.
b is magnetized to the S pole, and each disk 5 is inverted and rotated so that the N pole faces the magnetic pole portion 7a (N pole) and the S pole faces the magnetic pole portion 7b (S pole). The markers attached to the surface 5a are constantly displayed to the outside all at once.

V. Time Circuit Next, the time circuit T will be described.

An oscillator circuit 51 including a resistor R24, a capacitor C9, and a resistor 25 is connected to the IC22, and the IC22 divides the oscillation number of the oscillator circuit 51.

The output terminal of the OR circuit 14 is connected to the clear terminal 26 of the IC 22, and the signal corresponding to the logical value 1 from the OR circuit 14 is applied to the clear terminal 26.

One input terminal of the NAND circuit 24 is connected to the output terminal of the IC 22, and a series circuit of resistors R26, R27 and a knot circuit 23 is connected between the output terminal of the IC 22 and the other input terminal of the NAND circuit 24. A capacitor C10 is connected between the positive terminal of the resistor R27 and the negative terminal of the full-wave rectifier 2.

The resistors R26 and R27, the capacitor C10, the knot circuits 23 and 25, and the NAND circuit 24 constitute a display restoration signal generating circuit 52.

When a signal corresponding to a logical value of 1 is applied to the clear terminal 26, the IC 22 clears the division of the oscillation number of the oscillation circuit 51 and starts re-division of the oscillation number.
Further, when the IC 22 is divided into a predetermined number, that is, after a predetermined time has elapsed, a signal corresponding to a logical value 0 is applied to one terminal of the NAND circuit 24 from its output terminal.

Further, the signal corresponding to the logical value 0 is applied to the knot circuit 23 after being delayed by the time constant of the resistor R26 and the capacitor C10, and the knot circuit 23 outputs the other signal of the NAND circuit 24 based on the signal corresponding to the logical value 0. A signal corresponding to the logical value 1 is applied to the terminal of. Then, the NAND circuit 24 applies one pulse signal corresponding to the logical value 0 to the knot circuit 25 based on the signals applied to both terminals.

Then, the knot circuit 25 applies the signal corresponding to the logical value 1 as the display restoration signal to the next stage based on the signal corresponding to the logical value 0.

VI. Power Supply Circuit Here, the power supply circuit Z will be described.

A series circuit of the collector / emitter of the transistor Tr6, the diode D5, and the capacitor C11 as the driving power source 43 is connected between both terminals of the diode array Da. A Zener diode ZD1 is connected between the base terminal of the transistor Tr6 and the negative terminal of the full-wave rectifier 2 to form the first and second constant voltage circuits 53 and 54 in FIG.

The power supply circuit Z applies a forward voltage between the diode array Da2 to the transistor Tr6 and the Zener diode Z.
The voltage is further made constant at D1 or the like to charge the capacitor C11.

When a steady load current is flowing in the distribution line L, the capacitor C11 is not consumed, and the drive current is supplied to each of the above parts by the load current. And
When the circuit breaker at the substation trips and the load current no longer flows through the distribution line L, the capacitor C11 supplies the drive current required for each part from the output terminal P1.

VII. First Relay Drive Circuit Next, the first relay drive circuit 55 will be described.

One input terminal of the NAND circuit 27 is connected to the output terminal of the inverter 4B of the second waveform manipulation circuit 47, and a resistor R30, is provided between the output terminal of the inverter 4B and the other input terminal of the NAND circuit 27. R31 and inverter 2
A series circuit of 8 is connected, and a capacitor C12 is connected between the positive terminal of the resistor R31 and the negative terminal of the full-wave rectifier 2.

A series circuit of a diode D6, a charging resistor R32, and a capacitor C13 is connected between the positive terminal of the diode D5 and the negative terminal of the full-wave rectifier 2 to constantly charge the capacitor C13. The diode D6, the charging resistor R32, and the capacitor C13 form a relay driving power source charging circuit 56.

A collector / emitter of a switching transistor Tr7 and a set relay RY are provided between both terminals of the capacitor C13.
1 series circuit is connected. Further, an inverter 29 is connected between the base terminal of the switching transistor Tr7 and the output terminal of the NAND circuit 27, and a resistor R34 is provided between the base terminal and the negative terminal of the full-wave rectifier 2.
Are connected. A flywheel diode D7 is connected between both terminals of the set relay RY1.

When the set relay RY1 is excited, the b contact R
Yb is opened, and a search signal detecting section 59 described later is provided.
The a-contact RYa is closed.

The inverters 28 and 29, the NAND circuit 27, the resistor R3
The first relay drive circuit 55 is composed of 0, R31, R34, the capacitor C12, the set relay RY1, and the like.

Therefore, when the signal corresponding to the logical value 1 is applied from the inverter 4B to the next stage, the signal corresponding to the logical value 1 is applied to one terminal of the NAND circuit 27, and the resistor R30 is used.
The signal corresponding to the logical value 1 is applied to the inverter 28 after being delayed by the time constant of the capacitor C12, and the inverter 28 outputs the logical value 0 to the other terminal of the NAND circuit 27 based on the signal corresponding to the logical value 1. The signal corresponding to is applied. Then, the NAND circuit 27 applies one pulse signal corresponding to the logical value 0 to the inverter 29 based on the signals applied to both terminals.

Then, the inverter 29 applies the signal corresponding to the logical value 1 to the next stage based on the signal corresponding to the logical value 0. Then, since the voltage of the resistor R34 is applied to the gate terminal of the switching transistor Tr7, the switching transistor Tr7 is turned on and the capacitor C is turned on.
The charge of 13 is discharged and the set relay RY1 is excited.

VIII. Search Signal Detection Unit The search signal detection unit 59 will be described. A set relay RY is provided between the plus and minus terminals of the full-wave rectifier 2.
1 a contact RYa, Zener diode ZD2, resistor R
43 series circuits are connected.

A resistor R44 and a switching transistor T are provided between the output terminal P1 of the power supply circuit Z and the negative terminal of the full-wave rectifier 2.
A series circuit of the collector and emitter of r9 is connected, and the base terminal of the switching transistor Tr9 is connected to the plus terminal of the resistor R43. The collector terminal of the switching transistor Tr9 is the inverter 3
It is connected to one input terminal of the OR circuit 36 via 7.

The Zener diode ZD2 is designed so that the transformation current output from the current transformer CT based on the normal load current flowing through the distribution line L is broken down by the full-wave rectified signal by the full-wave rectifier 2.

The Zener diode ZD2, the resistor R43, the switching transistor Tr9 and the like constitute a voltage discrimination circuit 62.

A series circuit of a resistance R48 and a resistance R49 is connected in parallel between both terminals of the series circuit of the Zener diode ZD2 and the resistance R43. Further, the collector / emitter of the switching transistor Tr11 is connected between the output terminal P1 of the power supply circuit Z and the negative terminal of the full-wave rectifier 2, and the collector terminal of the switching transistor Tr11 is connected to the other of the OR circuit 14 via an inverter 38. Is connected to the input terminal of.

Then, the a-contact RYa is closed, and the voltage of the resistor R49 corresponding to the search signal is applied to the switching transistor T.
When applied to the base terminal of r11, the switching transistor Tr11 is rendered conductive, and a signal corresponding to a logical value 0 is applied to the inverter. Further, the inverter 38 outputs the signal (detection signal) corresponding to the logical value 1 based on the signal corresponding to the logical value 0 to the OR circuit 14.
It is designed to be applied to.

A search signal detection circuit 64 is configured by the resistors R48, R49, the switching transistor Tr11, the inverter 38, and the like.

The search signal detector 59 is set so that the search signal detection time in the search signal detection circuit 64 is longer than the retransmission current detection time in the voltage determination circuit 62. Therefore, when the voltage discrimination circuit 62 detects the retransmission current immediately after the search signal is injected, the same voltage discrimination circuit 6 is detected.
2 operates so that the display ID does not malfunction.

IX. Second Relay Drive Circuit Next, the second relay drive circuit 61 will be described.

A series circuit of a diode D8, a charging resistor R45, and a capacitor C18 is connected between the output terminal P1 of the power supply circuit Z and the negative terminal of the full-wave rectifier 2 to constantly charge the capacitor C18.

The diode D8, the resistor R45 and the capacitor C1
A relay driving power supply charging circuit 60 is configured by 8 and.

A series circuit of a collector / emitter of the switching transistor Tr10 and a reset relay RY2 is connected between the negative terminal of the charging resistor R45 and the negative terminal of the full-wave rectifier 2. A flywheel diode 9 is connected between both terminals of the reset relay RY2.

When the reset relay RY2 is excited, it closes the b-contact RYb of the short-circuit detection circuit X and also makes the a-contact R
It is designed to open Ya.

The base terminal of the switching transistor Tr10 is connected to the output terminal of the OR circuit 36, and a resistor R47 is connected between the base terminal and the negative terminal of the full-wave rectifier 2.

Inverter 37, OR circuit 36, resistors R44, R46,
The R47, the switching transistor Tr10, and the reset relay RY2 form a second relay drive circuit 61.

Therefore, when the switching transistor Tr9 becomes conductive, the signal corresponding to the logical value 0 is applied to the inverter 37, and the signal corresponding to the logical value 1 is applied to the input terminal of the OR circuit 36. Then, the OR circuit 36 outputs the logical value 1
The signal corresponding to the logical value 1 is applied to the next stage based on the signal corresponding to the switching transistor Tr10.
The voltage of the resistor R47 is applied to the base terminal of the switching transistor Tr10, and the switching transistor Tr10 becomes conductive.

As a result, the electric charge of the capacitor C18 is discharged and the reset relay RY2 is excited.

X. Relay return time limit circuit The relay return time limit circuit 57 as a timer circuit will be described.

A series circuit of a resistor R35 and a collector / emitter of a switching transistor Tr8 is connected between the output terminal P1 of the power supply circuit Z and the negative terminal of the full-wave rectifier 2. The base terminal of the switching transistor Tr8 is connected to the emitter terminal of the switching transistor Tr7, and the resistor R37 is connected between the base terminal and the negative terminal of the full-wave rectifier 2.

The IC30 has a resistor R38, a capacitor C14, and a resistor R3.
The oscillation circuit 58 of 9 is connected, and the IC 30 divides the oscillation number of the oscillation circuit 58.

The collector terminal of the switching transistor Tr8 is connected to the clear terminal 31 of the IC 30 via an inverter 32, and a signal corresponding to a logical value 1 from the inverter 32 is applied to the clear terminal 31.

One input terminal of the NAND circuit 33 is connected to the output terminal of the IC 30, and a series circuit of resistors R40 and R41 and an inverter 34 is connected between the output terminal of the IC 30 and the other input terminal of the NAND circuit 33. A capacitor C15 is connected between the positive terminal of the resistor R41 and the negative terminal of the full-wave rectifier 2. Further, the NAND circuit 33 is connected via an inverter 35 to one input terminal of an OR circuit 36 of a search signal detecting section 59 described later.

The resistors R40 and R41, the capacitor C15, the inverters 34 and 35, and the NAND circuit 33 constitute a relay return signal generation circuit 63.

When a signal corresponding to a logical value of 1 is applied to the clear terminal 31, the IC 30 clears the division of the oscillation number of the oscillation circuit 58 and starts the division of the oscillation number again.
When the IC 30 is divided into a predetermined number, that is, when a predetermined time elapses, a signal corresponding to a logical value 0 is applied to one terminal of the NAND circuit 33 from its output terminal.

Further, the signal corresponding to the logical value 0 is applied to the inverter 34 after being delayed by the time constant of the resistor R40 and the capacitor C15, and the inverter 34 outputs the other terminal of the NAND circuit 33 based on the signal corresponding to the logical value 0. Logical value of 1
The signal corresponding to is applied. Then, the NAND circuit 33 applies one pulse signal corresponding to the logical value 0 to the inverter 35 based on the signals applied to both terminals.

Then, the inverter 35 applies a signal corresponding to the logical value 1 as a return signal to the next stage based on the signal corresponding to the logical value 0.

Operation of the Embodiment The operation of the signal injection type short-circuit / ground fault detection device configured as described above will be described.

Now, when a steady load current is flowing in the distribution line L, the b contact RYb is closed in the short circuit detection circuit X, and a small amount of the transformation current is output from the current transformer CT, and the transformation current is the whole. Full-wave rectified by the wave rectifier 2,
The capacitor C11 of the power supply circuit Z is charged. Further, the power supply circuit Z uses capacitors C8 and C as driving power supplies for each circuit.
Charge C13 and C18. Most of the full-wave rectified by the full-wave rectifier 2 is consumed by the resistors R1 and R2 and the diode array Da.

At this time, in the search signal detector 59, the a contact R
Ya is open circuit.

In this state, for example, if a short circuit that allows the circuit breaker in the substation to trip occurs in the distribution line L, the current transformer CT outputs a transformation current to the short circuit detection circuit X. The transformed current is full-wave rectified by the full-wave rectifier 2, and the photocoupler PC receives the full-wave rectified analog signal and digitally outputs the light-emitting diode LED and the phototransistor PTr.

Then, the switching transistor Tr1 is turned on when the level of the digital signal applied to the base terminal is equal to or higher than a predetermined value. When the switching transistor Tr1 is turned on, the voltage across the resistor R4 is divided by the resistors R10 and R11, and the voltage of the resistor R11 is applied to the base terminal of the transistor Tr3 to turn on the transistor Tr3. Operate.

Then, the signal corresponding to the logical value 0 is applied to the inverter 9, and the inverter 9 applies the signal corresponding to the logical value 1 to one terminal of the NAND circuit 10. Further, the inverter 1 is delayed by the time constant of the resistor R12 and the capacitor C5.
A signal corresponding to the logical value 1 is applied to 1, and the inverter 11 applies a signal corresponding to the logical value 0 to the other terminal of the NAND circuit 10 based on the signal corresponding to the logical value 1. Then, the NAND circuit 10 applies one pulse signal corresponding to the logical value 0 to the inverter 12 based on the signals applied to both terminals.

Then, the inverter 12 applies the signal corresponding to the logical value 1 to the signal memory circuit 45 based on the pulse signal corresponding to the logical value 0, and the signal memory circuit 45 causes the resistor R
16, a signal corresponding to the logical value 1 is applied to the AND circuit 13 for a certain period of time based on the time constant of the capacitor C6.

On the other hand, when the circuit breaker of the substation trips due to the short circuit, resulting in no voltage on the distribution line L, the voltage across the diode array Da becomes no voltage.
The voltage (that is, no voltage) of the resistor R8 is applied to the base terminal of the transistor, and the transistor Tr2 is turned off.
Then, the collector-emitter voltage of the transistor Tr2 rises, and the signal corresponding to the logical value 1 is applied to the inverter 4A.

Therefore, the signal corresponding to the logical value 0 is output from the output terminal of the inverter 4A, and the inverter 4B outputs the logical value 0.
The waveform is made rectangular based on the signal corresponding to, and the signal corresponding to the logical value 1 (no-voltage detection signal) is output.

The AND circuit 13 receives the signal corresponding to the logic value 1 from the voltageless detection circuit 46 (the voltageless detection signal) while the signal corresponding to the logic value 1 from the signal memory circuit 45 is applied. Then, a signal corresponding to the logical value 1 as a switch signal is applied to one terminal of the NAND circuit 15 based on both signals.

Further, a signal corresponding to the logical value 1 is applied to the inverter 16 after being delayed by the time constant of the resistor R17 and the capacitor C7, and the inverter 16 outputs the other terminal of the NAND circuit 15 based on the signal corresponding to the logical value 1. A signal corresponding to a logical value of 0 is applied to. Then, the NAND circuit 15 applies one pulse signal corresponding to the logical value 0 to the inverter 18 based on the signals applied to both terminals.

Then, the inverter 18 applies the signal corresponding to the logical value 1 to the OR circuit 14 based on the signal corresponding to the logical value 0. As a result, the OR circuit 14 applies the signal corresponding to the logical value 1 to the next stage. Then, the voltage of the resistor R20 is applied to the base terminal of the switching transistor Tr4, so that the switching transistor Tr4
Turns on (conducts), the charge of the capacitor C8 is discharged, and a display drive current is output to the display ID.

The display drive current causes the display ID to be short-circuited.

When the signal corresponding to the logical value 1 is applied from the OR circuit 14 to the next stage, the IC 22 clears the division of the oscillation number of the oscillation circuit 51 and starts the division of the oscillation number again. Then, after a lapse of a predetermined time, the IC 22 applies a signal corresponding to the logical value 1 to one terminal of the NAND circuit 24 from its output terminal.

Further, the signal corresponding to the logical value 1 is applied to the knot circuit 23 after being delayed by the time constant of the resistor R26 and the capacitor C10, and the knot circuit 23 outputs the other signal of the NAND circuit 24 based on the signal corresponding to the logical value 1. Logical value 0 at the terminal
The signal corresponding to is applied. Then, the NAND circuit 24 applies one pulse signal corresponding to the logical value 0 to the knot circuit 25 based on the signals applied to both terminals.

Then, the knot circuit 25 applies the signal corresponding to the logical value 1 as the display restoration signal to the next stage based on the signal corresponding to the logical value 0. Then, since the voltage of the resistor R23 is applied to the base terminal of the switching transistor Tr5, the switching transistor Tr5 is turned on and the return drive current is output to the display ID.

The display drive ID is reset by this return drive current, and the display returns to the steady display state.

On the other hand, when the inverter 4B applies the signal corresponding to the logical value 1 to the next stage, the signal corresponding to the logical value 1 is applied to one input terminal of the NAND circuit 27 in the relay drive circuit 55, and A signal corresponding to the logical value 1 is applied to the inverter 28 after being delayed by the time constant of the resistor R30 and the capacitor C12, and the inverter 28 outputs the logical value 1
A signal corresponding to a logical value of 0 is applied to the other terminal of the NAND circuit 27 based on the signal corresponding to. Then, the NAND circuit 27 outputs a logical value of 0 based on the signals applied to both terminals.
One pulse signal corresponding to is applied to the inverter 29.

Then, the inverter 29 applies the signal corresponding to the logical value 1 to the next stage based on the signal corresponding to the logical value 0. As a result, the voltage of the resistor R34 is applied to the base terminal of the switching transistor Tr7,
The switching transistor Tr7 is turned on (conducted).
Then, the electric charge of the capacitor C13 is discharged and the set relay RY1 is excited. By exciting the set relay RY1, the b contact RYb of the short circuit detection circuit X is opened and the a contact RYa of the search signal detection unit 59 is closed. At this time, however, the distribution line L is in a non-voltage state, so the search signal is not detected. The detector 59 does not operate.

When the switching transistor Tr7 is turned on, the voltage of the resistor R37 changes to the switching transistor T7.
Applied to the base terminal of r8, the switching transistor Tr8 is turned on. As a result, the signal corresponding to the logical value 0 is applied to the inverter 32, thereby applying the signal corresponding to the logical value 1 to the clear terminal 31 of the IC 30.

Then, the IC 30 clears the division of the number of oscillations of the oscillation circuit 58 and starts the division of the number of oscillations again, and when a predetermined time elapses, the IC 30 outputs a signal corresponding to the logical value 1 from one of its output terminals to one of the NAND circuits 33. Apply to the terminal of.

Further, the signal corresponding to the logical value 1 is applied to the inverter 34 after being delayed by the time constant of the resistor R40 and the capacitor C15, and the inverter 34 outputs the other terminal of the NAND circuit 33 based on the signal corresponding to the logical value 1. Logical value 0
The signal corresponding to is applied. Then, the NAND circuit 33 applies one pulse signal corresponding to the logical value 0 to the inverter 35 based on the signals applied to both terminals.

Then, the inverter 35 applies a signal corresponding to the logical value 1 as the relay return signal to the next stage to the OR circuit 36 based on the signal corresponding to the logical value 0. As a result, since the signal corresponding to the logical value 1 from the OR circuit 36 is applied to the next stage, the voltage of the resistor R47 is applied to the base terminal of the switching transistor Tr10, the switching transistor Tr10 becomes conductive, and the reset relay RY2.
To excite.

By exciting the reset relay RY2, the b contact RYb of the short-circuit detection circuit X is closed and the a contact RYa is closed.
Is opened, and the short-circuit / ground-fault detection device waits for the detection of a short-circuit current accident.

Next, a case where a ground fault occurs in the distribution line L will be described.

When a ground fault occurs in the distribution line L and the circuit breaker at the substation trips, the distribution line L becomes a no-voltage as in the case where the short-circuit current flows and the circuit breaker at the substation trips. Then,
The non-voltage detection circuit 46 and the second waveform manipulation circuit 47 operate and the switching transistor Tr7 turns on.

Then, the electric charge of the capacitor C13 is discharged and the set relay RY1 is excited. By exciting the set relay RY1, the b contact RYb of the short circuit detection circuit X is opened and the a contact RYa of the search signal detection unit 59 is closed.

Then, when the search signal is injected into the distribution line L in this state, the search signal detection unit 59 detects the search signal via the current transformer CT.

That is, when the a-contact RYa is closed and the search signal is injected, the voltage of the resistor R49 is applied to the base terminal of the switching transistor Tr11, and the switching transistor Tr11 becomes conductive. Then inverter 3
A signal corresponding to a logical value of 0 is applied to 8, and the inverter 38 applies a signal corresponding to a logical value of 1 to the OR circuit 14 based on the signal. Then, as in the case of detecting the short-circuit current, the switching transistor Tr4 becomes conductive, the charge of the capacitor C8 is discharged, and the display drive current is output to the display ID. As a result, the display unit ID performs a display operation and a failure display is performed.

On the other hand, when the OR circuit 14 applies the signal corresponding to the logical value 1 based on the signal corresponding to the logical value 1, the time circuit T operates in the same manner as when the short circuit current is detected, and after a predetermined time, the display device The return drive current is output to the ID after a fixed time.

The display drive ID is reset by this return drive current, and the display returns to the steady display state.

When the non-voltage detection circuit 46 and the second waveform manipulation circuit 47 operate and the switching transistor Tr7 is turned on, the voltage of the resistor R37 is applied to the base terminal of the switching transistor Tr8 and the switching transistor Tr8 is turned on. Operate. As a result, the signal corresponding to the logical value 1 is applied from the inverter 32 to the clear terminal 31 of the IC 30 in the relay recovery time limit circuit 57.

Then, the relay recovery time limit circuit 57 outputs a signal corresponding to the logical value 1 to the OR circuit 36 after a predetermined time after a predetermined time. As a result, since the signal corresponding to the logical value 1 is applied to the next stage from the OR circuit 36, the voltage of the resistor R47 is applied to the base terminal of the switching transistor Tr10,
The switching transistor Tr10 is turned on to excite the reset relay RY2.

By exciting the reset relay RY2, the b contact RYb of the short-circuit detection circuit X is closed and the a contact RYa is closed.
Is opened, and the short-circuit / ground-fault detection device waits for the detection of a short-circuit current accident.

When a ground fault occurs in the distribution line L, the circuit breaker of the substation trips, and the search signal is not detected thereafter, and the re-transmission of the substation succeeds thereafter, a of the search signal detection unit 59 is detected.
Power is retransmitted with the contact RYa closed. At this time, a normal load current flows through the distribution line L.

Then, the voltage determination circuit 46 in the search signal detection unit 59.
The Zener diode ZD2 of is broken down and the voltage of the resistor R43 is applied to the base terminal of the switching transistor Tr9.
Conducts. Then, the second relay drive circuit 61 operates, the switching transistor Tr10 becomes conductive, the electric charge of the capacitor C18 is discharged, and the reset relay RY2.
To excite.

By exciting the reset relay RY2, the b contact RYb of the short-circuit detection circuit X is closed and the a contact RYa is closed.
Is opened, and the short-circuit / ground-fault detection device waits for the detection of a short-circuit current accident.

Further, in this short-circuit / ground fault detection device, when a circuit check is performed when the product is completed, the current discrimination switching circuit 42,
The short circuit determination circuit 43, the signal memory circuit 45, and the like operate, and the display switching circuit 49 operates to display the display ID. Then, at this time, the first relay drive circuit 55 operates to excite the set relay RY1 and the circuit is switched to the search signal detection unit 59 side, but the relay return time limit circuit 57 causes the second relay drive circuit 61 to pass after a predetermined time. Is activated to excite the reset relay RY2, the circuit is switched to the short-circuit detection circuit X side, and the short-circuit current fault detection is on standby.

Further, the short-circuit detection circuit X is intended to input a signal based on the short-circuit current by the photo coupler PC and to be digitally output by the photo coupler PC, so that the photo transistor PTr of the photo coupler PC has high sensitivity and high speed performance. The resistance value of the resistor R1 can be reduced, which can reduce the heat generation of the resistor R1.

In addition, the short circuit detection circuit X can isolate the digital output and the diode array Da connected in series to the short circuit detection circuit by the photocoupler PC, whereby the short circuit detection circuit X for one current transformer CT, The power supply circuit Z and the no-voltage detection circuit 31 can be connected.

Further, in the short-circuit detection circuit X, the display ID is driven for display by discharging the capacitor C8, so that almost no current for driving is consumed.

Further, in this embodiment, since the display ID is constituted by electrically connecting the magnetic reversal display in parallel, the circuit impedance is lowered and the discharge efficiency of the capacitor C8 used as the drive power source is improved, Ensure display drive. Further, since the control circuit employs the IC timer as described above, there is an advantage that the current consumption of the control circuit can be small.

Further, in this embodiment, the capacitor C13 as the driving power source of the first relay driving circuit 55 is the diode D5 before charging.
Since it is taken from the positive terminal of No. 1, even if the non-voltage state of the distribution line L continues, once it is switched to the original short circuit detection circuit X side, the circuit will not be switched to the search signal detection circuit side again.

Application Example Next, an example in which the signal injection type short-circuit / ground fault detection device is applied to a ground fault point detection system will be described with reference to FIGS.

In the figure, reference numeral 70 indicates a power transmission line, 71 indicates a circuit breaker (hereinafter referred to as CB) of a substation, the distribution line L is connected to the power transmission line 70 via the CB 71, and each phase is as shown in FIG. L
Represented by a, Lb, and Lc.

Reference numeral 72 is a zero-phase current transformer (hereinafter, referred to as ZCT) of the substation provided on the closest load side of the CB 71, and 73 is a grounding transformer (hereinafter, referred to as GPT) provided on the power transmission line 70. 73 detects the one-line ground fault that occurs in the distribution line L, operates the directional ground fault relay 74 to trip the CB 71, and disconnects the distribution line L from the power transmission line 70.

A large number of classification switches SS are arranged on the distribution line L,
A number of sections An (n = 1, 2,
3 ...) are classified.

This section switch SS is a conventionally known section switch,
As shown in FIG. 8, when a ground fault occurs in a certain section (at T1), the substation CB71 selectively cuts off the fault line (at T2), and when the fault line becomes unvoltage, the delay open time Z is set. After that, each section switch SS is opened (at T6). Then, the reclosing of CB71 (at T3)
When voltage is applied by CB, CB will be reached after X hours (at T7).
When the first section switch SS adjacent to 71 is closed, and voltage is sequentially applied to the load side section switch SS,
The same circuit is closed after X hours.

In this way, power is sequentially supplied from the partition switch SS on the power source side to re-transmit power to the healthy section, and when the ground fault section is reached, the substation CB71 is re-blocked (at T4). And
When the CB 71 of the substation is closed again (at T5), the partition switch SS for partitioning the ground fault section is locked in an open state so that only the ground fault section is separated.

Reference numeral 75 denotes a search signal injection device connected to the distribution line L of each set on the closest load side of the ZCT 72 and is grounded (see FIG. 6). The search signal output from the search signal injection device 75 has a full-wave current waveform (see FIG. 9). The reason why the full-wave current waveform is adopted as the search signal is that the current transformer CT of the short-circuit / ground fault detector H can detect both the short-circuit current and the search signal. This is also because the loss current due to the distribution line stray capacitance is small (only the leakage current due to the CR time constant) when the search signal of this full-wave current waveform is injected into the high-voltage distribution line.

This search signal injection device 75 inputs the trip signal from the CB71 when the substation CB71 is cut off (at T2),
When the CB71 shuts down based on the trip signal (T2
From when the first section switch SS opens (T6)
The search signals are collectively injected in three phases by using the delay open time Z up to the time.

In addition, the injection of the search signal is performed by the first section switch SS.
Is set to finish before the circuit opens (8th
(Time from T8 to T9 shown in the figure). The drive power supply of the search signal injection device 75 is composed of a transformer Tr connected to the power supply side of the CB 71.

A plurality of short circuit / ground fault detection indicators H are attached to each phase in each section An of the distribution line L as shown in FIG.
They are spaced apart from each other by a predetermined distance.

In FIG. 7, AS is a normally closed switch.

Next, the operation of the system configured as described above will be described.

Now, in FIG. 7, it is assumed that a line-to-ground fault has occurred at point m of phase a in section A3 of distribution line L (at T1). It should be noted that in the description as appropriate, in FIG. 7, the a phase La of the distribution line L is
Is only illustrated.

Then, the ZCT72 of the substation gives a zero-phase current to the GPT73.
Outputs a zero-phase voltage as a ground fault signal, a trip signal is sent to CB71 via relay 74, and substation CB71 is opened (at T2).

Then, the search signal injecting device 75 inputs the trip signal from the CB71, and based on the trip signal, the delay opening time Z from when the CB71 is cut off (at T2) to when the sectional switch SS is opened (at T6). Is used to inject the search signal into each phase La, Lb, Lc of the distribution line (8th
(Time from T8 to T9 shown in the figure).

Then, the search signal injection device 75, the distribution line La, and the ground fault point m
And a circulating current flows in a closed loop path through the search signal injection device 75, and as a result, the detection device, that is, the A1 section and A2, arranged between the injection point of the search signal injection device 75 and the ground fault point P. The detection devices H1 and the like in the section and the detection devices H2 and H3 in the section A3 are displayed.

On the other hand, regarding the b and c phases, a closed loop including the ground capacitance of the distribution line L is formed instead of the ground fault point m, but the impedance of this loop is high and the level of the search signal flowing is low, so that the other two phases Lb , Lc, the detection devices H are still in the steady display.

Further, even if the detection device is attached to the a-phase, the search signal does not reach a certain level or higher, so that the detection device H4 and the like provided on the load side from the ground fault point m remain in the steady display.

Thus, the search signal injection device 75 displays the ground fault on the detection devices up to the ground fault point m, but the injection of the search signal ends before the section switch SS is opened (at T9).

As described above, after the search signal injection device 75 injects the search signal (that is, after Z time has passed since the substation CB71 was cut off), the sectional switch SS is opened (T6).
Time). Then, when a voltage is applied by reclosing the CB71 (at T3), the first section switch SS adjacent to the substation CB71 is closed after X hours (at T7), and the section switching on the load side is performed sequentially. When voltage is applied to the container SS, X
It also closes after a time.

In this way, power is sequentially supplied from the division switch SS on the power source side to re-transmit power to the healthy section, and when the ground fault section is reached, the substation CB71 is re-blocked (at T4). And
When the CB71 of the substation is closed again (at T5), the division switch SS that divides the ground fault section A3 is locked in an open state and only the ground fault section A3 is separated.
Re-transmission is performed only in the healthy section.

As described above, the ground fault section A3 can be detected by the division switch SS being locked in the open state, and then the worker departs from the power supply side toward the load side in the ground fault section. And then the accident (ground fault)
By searching for the detection device H in the display state, between the point where the detection device H3 is displayed and the detection device H4 is displayed, which is one before the detection device H4 that is not performing the failure display. It can be determined that there is a ground fault point m at.

When searching for the ground fault point m, at the branch point α, the detection device H5 provided on one of the load side branch lines and the detection device H3 provided on the other load side branch line are compared and detected. The device H may proceed along the branch line on the side displaying the accident (ground fault).

Next, a second embodiment will be described with reference to FIGS.

In this embodiment, in the configuration of the first embodiment, the time circuit T is provided with a time section control signal holding circuit 81, an AND circuit 82, a first oscillation holding circuit 83 and a first holding release circuit 84, and The difference lies in that the relay recovery time limit circuit 57 is provided with a second oscillation holding circuit 95 and a second holding release circuit 96.

Hereinafter, each of the circuits will be described in detail. The same or corresponding components as those of the first embodiment are designated by the same reference numerals and the description thereof will be omitted.

As shown in FIG. 10 (a), the time section control signal holding circuit 8
1 outputs a signal corresponding to a logical value of 0 from its output terminal when the distribution line L is in a steady state, and when a time period control signal is input at the time of detecting a fault current, it outputs a logical value of 1 from its output side. The corresponding signal is continuously output to the next stage.

Also, the time limit control signal holding circuit 81 outputs the signal corresponding to the logical value 1 from the first holding release circuit 84 described later while continuously outputting the signal corresponding to the logical value 1 as described above. When input, a signal corresponding to a logical value 0 is output from the output side.

The time limit part control signal holding circuit 81 is specifically as shown in FIG.

That is, the output terminal of the OR circuit 86 for inputting the time period control signal to one input terminal is connected to one input terminal of the AND circuit 87. Further, the output terminal of the AND circuit 87 is connected to the other input terminal of the OR circuit 86 and is also connected to one input terminal a of the AND circuit 82. The other input terminal of the AND circuit 87 is connected to the first holding release circuit 84 described later via the inverter 110.
Is connected to the output terminal of the AND circuit 93.

The OR circuit 86, the AND circuit 87, and the inverter 11
With 0, the time section control signal holding circuit 81 is formed.

The other input terminal b of the AND circuit 82 is connected to the output terminal of the inverter 4A of the second waveform operation circuit 47.

Next, when the AND circuit 82 outputs the signal corresponding to the logical value 0, the first oscillation holding circuit 83 shown in FIG. 10 (a) changes the logical value to 1 based on the signal corresponding to the logical value 0. It outputs the corresponding signal to the next stage,
When the AND circuit 82 outputs a signal corresponding to the logical value 0 → 1, a signal corresponding to the logical value 1 → 0 is output to the clear terminal 26 of the IC22 based on the signal, and the IC2
2 starts to oscillate.

Further, when the first oscillation holding circuit 83 inputs the signal corresponding to the logical value 1 from the first holding release circuit 84 described later while outputting the signal corresponding to the logical value 0 as described above, A signal corresponding to the logical value 1 is output from the output side.

Specifically, the first oscillation holding circuit 83 is as shown in FIG.

That is, the output terminal of the AND circuit 82 is the OR circuit 8
8 is connected to one input terminal of the AND circuit 88, and the output terminal of the OR circuit 88 is connected to one input terminal of the AND circuit 89. The other input terminal of the AND circuit 89 is the knot circuit 1
It is connected via 11 to the output terminal of the AND circuit 93 of the first holding release circuit 84 described later. The output terminal of the AND circuit 89 is connected to the IC 22 via the knot circuit 90.
Is connected to the clear terminal 26 of.

The OR circuit 88, the AND circuit 89, and the knot circuit 9
The first oscillation holding circuit 83 is composed of 0 and 111.

Further, when the IC 22 inputs a signal corresponding to the logical value 0 from the first oscillation holding circuit 83, the oscillation of the oscillation circuit 51 is started. Then, when the signal corresponding to the logical value 1 is output from the IC 22 after a predetermined time, one pulse signal corresponding to the logical value 0 is output from the NAND circuit 24, whereby the signal corresponding to the logical value 1 is output from the knot circuit 25. It is supposed to be output.

Next, the first hold release circuit 84 outputs a signal corresponding to a logical value 0 from the output side of the IC 22 to the time period control hold circuit 81 and the first oscillation hold circuit 83 while the IC 22 continues the oscillation stop state. It is supposed to do. Further, when a signal corresponding to the logical value 1 is input from the knot circuit 25, a signal corresponding to the logical value 1 is output from the output side.

Specifically, the first holding release circuit 84 is as shown in FIG. That is, the output terminal of the knot circuit 25 is connected to the input terminal of the AND circuit 92, and the output terminal of the AND circuit 92 is connected to the output terminal of the AND circuit 93 via the series circuit of the resistors R102 and R103. A series circuit of a resistor R104 and a diode D100 is connected in parallel to both terminals of the resistor R102.

The AND circuits 92 and 93, the resistors R102 and R103,
The R104 and the diode D100 form a first holding release circuit 84.

Next, when the second oscillation holding circuit 95 shown in FIG. 10 (b) is inputting the signal corresponding to the logical value 0, the signal corresponding to the logical value 1 is generated based on the signal corresponding to the logical value 0. It is designed to output to the next stage, and logical value 0 → 1
When inputting a signal corresponding to, the signal corresponding to the logical value 1 → 0 is input to the clear terminal 3 of the IC 30 based on the signal.
It outputs to 1 and makes IC30 start oscillation.

Further, when the second oscillation holding circuit 95 inputs a signal corresponding to a logical value 1 from a second holding release circuit 96 described later while outputting a signal corresponding to a logical value 0 as described above, A signal corresponding to the logical value 1 is output from the output side.

Specifically, the second oscillation holding circuit 95 is as shown in FIG.

That is, the input terminal of the OR circuit 97 is connected to the negative terminal of the resistor R35 via the inverter 98, and the output terminal of the OR circuit 97 is connected to one input terminal of the AND circuit 99. The other input terminal of the AND circuit 99 is connected to the output terminal of the AND circuit 103 of the second holding release circuit 96 described later via the knot circuit 100.
The output terminal of the AND circuit 99 is a knot circuit 101.
Is connected to the clear terminal 31 of the IC 30 via.

The OR circuit 97, the AND circuit 99, and the knot circuit 10
A second oscillation holding circuit 95 is constituted by 0 and 101.

Further, when the IC 30 inputs a signal corresponding to the logical value 0 from the second oscillation holding circuit 95, the oscillation of the oscillation circuit 58 is started. Then, when a signal corresponding to the logical value 1 is output from the IC 30 after a predetermined time, one pulse signal corresponding to the logical value 0 is output from the NAND circuit 33, whereby the signal corresponding to the logical value 1 is output from the knot circuit 35. It is supposed to be output.

Next, the second holding release circuit 96 shown in FIG.
When C30 continues the oscillation stopped state, a signal corresponding to the logical value 0 is output from the output side thereof to the second oscillation holding circuit 95. Further, when a signal corresponding to the logical value 1 is input from the knot circuit 35, a signal corresponding to the logical value 1 is output from the output side thereof.

Specifically, the second holding release circuit 96 is as shown in FIG. That is, the output terminal of the knot circuit 35 is connected to the input terminal of the AND circuit 102, and the output terminal of the AND circuit 102 is connected to the output terminal of the AND circuit 103 via the series circuit of the resistors R105 and R106. A capacitor 100 is connected to the negative terminal of the resistor R105 and the negative terminal of the full-wave rectifier 2.

AND circuits 102 and 103, resistors R105 and R10
A second holding release circuit 96 is configured by 6 and the capacitor C100.

A series circuit of a diode D101 and a capacitor C102 is connected via a resistor R28 between the emitter of the transistor Tr6 of the power supply circuit Z and the negative terminal of the full-wave rectifier 2, and the positive terminal of the capacitor C102 is connected to the time section control signal. By being connected to each circuit of the holding circuit 81, the capacitor C102 is connected to the time section control signal holding circuit 81.
And power. The capacitor C102 is adapted to apply a voltage to the simultaneous limit section control signal holding circuit 81 even when the distribution line L is in a no-voltage state.

In the short-circuit ground fault detection device of the second embodiment, when the distribution line L is in a steady state, the inverter 4A of the second waveform manipulation circuit 47 outputs the signal corresponding to the logical value 1, but the AND circuit 82 Since the signal corresponding to the logical value 0 is input to the one input terminal a from the time period control circuit 81, the AND circuit 82 outputs the signal corresponding to the logical value 0 to the next stage.

Therefore, since the first oscillation holding circuit 83 inputs the signal corresponding to the logical value 0, the output side thereof outputs the signal corresponding to the logical value 1 to the clear terminal 26 of the IC 22. As a result, the IC 22 Continues the oscillation stop state.

Next, for example, a short-circuit fault occurs in the distribution line L in which the substation circuit breaker can trip, and as a result, the drive circuit of the display unit ID operates and the display unit H displays as in the first embodiment. The signal corresponding to the logical value 1 as the timed part control signal output from the circuit 14 is supplied to the timed part control signal holding circuit 81.
Is input, the time section control signal holding circuit 81 continues to output the signal corresponding to the logical value 1 from the output side of the AND circuit 8
2 to the input terminal a. When the substation circuit breaker trips due to the short-circuit fault and the distribution line L goes into a non-voltage state, a signal corresponding to a logical value 0 is output from the inverter 4A of the second waveform operation circuit 47. Reference numeral 82 outputs a signal corresponding to a logical value of 0 to the first oscillation holding circuit 83 based on the signals input to both input terminals a and b.

Furthermore, when the re-transmission of the substation to the distribution line L succeeds, a signal corresponding to the logical value 1 is output from the inverter 4A of the second waveform operation circuit 47, so that the AND circuit 82 operates as the input terminal a. , B, the signal corresponding to the logical value 0 → 1 is output from the output terminal to the next stage.

As a result, the AND circuit 82 is included in the first oscillation holding circuit 83.
Since a signal corresponding to the logical value 0 → 1 is input from the first oscillation holding circuit 83, the first oscillation holding circuit 83 outputs the logical value 1 based on the signal.
→ A signal corresponding to 0 is output to the clear terminal 26 of the IC 22 to cause the oscillation circuit 51 to start oscillation.

Then, the IC 22 outputs a signal corresponding to a logical value 1 from its output terminal after a predetermined time has elapsed. As a result, the NAND circuit 24 of the display restoration signal generation circuit 52 outputs one pulse signal corresponding to the logical value 0, whereby the knot circuit 25 outputs the logical value 1 as the display restoration signal.
The signal corresponding to is applied to the next stage. As a result, the display ID is returned to the display as in the first embodiment.

Further, at the same time, when the first holding release circuit 84 inputs the signal corresponding to the logical value 1 from the knot circuit 25, the first holding release circuit 84 changes its logical value to 1 from the output side based on this signal. The corresponding signal is sent to the time section control signal holding circuit 8
1 and the first oscillation holding circuit 83. Then, the time period control signal holding circuit 81 outputs a signal corresponding to the logical value 0 from the output side based on the signal, while the first oscillation holding circuit 83 corresponds to the logical value 1 based on the signal. To output the signal.

As a result, the IC 22 stops the oscillation of the oscillator circuit 51. That is, the fault current holding circuit 81 and the first oscillation holding circuit 83 return to their original states.

Further, if the distribution line L becomes a non-voltage state due to the trip of the substation circuit breaker for a reason other than the short-circuit fault current, and then the re-transmission to the distribution line L succeeds, the second terminal is provided to the input terminal b of the AND circuit 82. Logical value 1 → 0 → 1 by the waveform operation circuit 47 of
A signal corresponding to is input. However, since the time limit part control signal is not input to the time part control signal holding circuit 81, the output side of the time part control signal holding circuit 81 outputs the signal corresponding to the logical value 0 as in the steady state of the distribution line L. . Therefore, the AND circuit 82 outputs the signal corresponding to the logical value 0, and the first oscillation holding circuit 83 outputs the signal corresponding to the logical value 1, so that the IC 22 remains in the oscillation stopped state. .

Further, the relay recovery time limit circuit 57 operates as follows.

That is, when the fault current such as the short circuit flows, the set relay RY1 is excited as in the first embodiment, the b contact RYb of the short circuit detection circuit X is opened, and the a contact RYa of the search signal detection unit 59 is opened. Is closed, and at this time, the switching transistor Tr7 is turned on. Then, the voltage of the resistor R37 changes to the switching transistor Tr.
8 is applied to the base terminal of the switching transistor Tr8, and the switching transistor Tr8 is turned on. As a result, the signal corresponding to the logical value 0 is applied to the inverter 98, and the signal corresponding to the logical value 1 is output to the second oscillation holding circuit 95.

Then, the second oscillation holding circuit 83 outputs the signal corresponding to the logical value 0 from the knot circuit 101 to the clear terminal 31 of the IC 30 based on the signal corresponding to the logical value 1 to cause the oscillation circuit 58 to start the oscillation. .

Then, after a lapse of a predetermined time, the IC 30 outputs a signal corresponding to a logical value 0 from its output terminal. As a result, one pulse signal corresponding to a logical value 0 is output from the NAND circuit 33 of the relay return signal generating circuit 63, whereby the inverter 35 outputs a signal corresponding to a logical value 1 to the OR circuit 36 as a relay return signal. Apply to the stage.
As a result, since the signal corresponding to the logical value 1 is applied to the next stage from the OR circuit 36, the reset relay RY2 is excited in the same manner as in the above and the first embodiment.

By exciting the reset relay RY2, the b contact RYb of the short-circuit detection circuit X is closed and the a contact RYa is closed.
Is opened, and the short-circuit / ground-fault detection device waits for the detection of a short-circuit current accident.

On the other hand, when the second holding release circuit 96 inputs the signal corresponding to the logical value 1 from the inverter 35, the second holding release circuit 96 responds to the logical value 1 from the output side based on this signal. The signal for performing the output is output to the second oscillation holding circuit 95. Then, the second oscillation holding circuit 95 outputs a signal corresponding to the logical value 1 based on the signal. As a result, the IC 30 stops the oscillation of the oscillation circuit 58.
That is, the second oscillation holding circuit 95 and the IC 30 return to the original state.

The above description is for a short-circuit fault, but the same applies to a ground fault.

As described above, in the second embodiment, the IC 22 is operated by the timer under the signal output by the AND condition of the fault current and the non-voltage of the distribution line L, and the AND condition when the substation re-transmits power, and after a certain time. The oscillation of the oscillation circuit 51 is stopped by the signal output from the IC 22.

Other functions and effects are similar to those of the first embodiment.

It should be noted that the present invention is not limited to the above-mentioned embodiment, and can be arbitrarily modified within a range not departing from the spirit of the present invention.

EFFECTS OF THE INVENTION As described in detail above, the present invention does not require a grounding transformer, and has a simple configuration of a short circuit detection circuit, a search signal detection circuit and a time limit circuit. Therefore, the entire device can be made compact, lightweight and low cost. In addition, since it is configured to operate in response to a search signal, an operator only needs to temporarily make a temporary patrol from the power supply side to the load side in a ground fault fault section, and the ground fault point can be established without time. There is a great practical advantage that it can be easily identified.By arranging many short-circuit / ground fault detectors on the distribution line, it is effective in shortening the fault point search time, and in the early recovery. Can be done.

Furthermore, the timer circuit drives the second relay drive circuit after a predetermined time has passed from the time when the distribution line is in a non-voltage state,
Since the current detector is switched from the search signal detection circuit to the short-circuit current detection circuit side, the drive power supply of the control circuit may have a capacity determined by the time until switching, and has an excellent effect of being small and compact. .

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an electric block circuit diagram of a short circuit / ground fault direction detection device according to an embodiment of the present invention, and FIG. 2 is an electric circuit diagram of a short circuit / ground fault direction detection device. 3 is a schematic view of the display, FIG. 4 is a bottom view of the display, FIG. 5 is a bottom view of the display in the same failure display state, FIG. 6 is a distribution line system diagram, and FIG. Distribution line diagram for explanation, FIG. 8 is a time chart, FIG. 9 is a waveform diagram of a search signal, and FIGS. 10 (a) and 10 (b) are electrical block diagrams of essential parts of the second embodiment, and FIG. Is also an electric circuit diagram. 2 ... Full wave rectifier, 13 ... Gate circuit (AND circuit), 22 ... IC, 42 ... Current discrimination switching circuit, 43 ... Short circuit discrimination circuit, 44 ... First waveform operation circuit, 46 ... No-voltage detection circuit, 49 ... Switching circuit for display, 50 ... Switching circuit for display restoration, 55
...... First relay drive circuit, 56 …… Relay drive power supply,
57 ...... Timer circuit (relay return time circuit), 61 ...
… Second relay drive circuit, 64 …… Search signal detection circuit,
81 ... Timer control signal holding circuit, 83 ... First oscillation holding circuit, 84 ... First holding release circuit, 95 ... Second oscillation holding circuit, 96 ... Second holding release circuit, CT ...
… Current transformer, ID …… Display, L …… Distribution line, T ……
Time circuit, X ... Short circuit detection circuit, Z ... Power supply circuit.

Front Page Continuation (72) Inventor Katsunori Aoki No. 1 Upper Ko Needle, Inuyama City, Aichi Prefecture Takamatsu Electric Works Ltd. (72) Inventor Mitsuharu Kutomi No. 1 Upper Hand Needle, Inuyama City, Aichi Prefecture Takamatsu Electric Works Co., Ltd. (56) References JP-A-61-83974 (JP, A)

Claims (1)

[Claims] 1. A short-circuit current is detected through a current detector when a short-circuit current flows through the distribution line, a short-circuit current detection signal is output, and no voltage is applied to the distribution line when the breaker of the substation trips. A short-circuit detection circuit that detects a state and outputs a no-voltage detection signal, a gate circuit that outputs a switch signal when both the short-circuit current detection signal and the no-voltage detection signal from the short-circuit detection circuit are input, and a ground fault When a search signal injected into a distribution line is detected through the current detector, a search signal detection circuit that outputs a detection signal, and a switch signal output by the gate circuit or a detection output by the search signal detection circuit ON operation based on the signal, output the display drive current, display switching circuit to display the fault in the display, and the current detector short-circuited when the distribution line is in no voltage state The first relay drive circuit that switches from the detection circuit side to the search signal detection circuit side; the second relay drive circuit that switches the current detector from the search signal detection circuit side to the short circuit detection circuit side; A control circuit for a signal injection type short-circuit / ground fault detection device, comprising: a timer circuit for driving the second relay drive circuit after a predetermined time has elapsed from the time when the state has entered.