JPH0652741B2 - Method for manufacturing insulated gate transistor - Google Patents

Description

The present invention relates to an insulated gate (MIS) type transistor, and more particularly to an amorphous silicon MIS type transistor, in which film slippage of a channel portion is prevented to secure an operating current in an on state. With the goal. Another object of the present invention is to provide a highly reliable MIS transistor.

Amorphous silicon, which is formed by containing a few percent of hydrogen in its composition to compensate for the imperfections of atomic bond pairs, can be formed at low temperature, and it is easy to increase the area. It is attracting attention as a low-cost solar cell. However, compared to single crystal silicon, the mobility of free electrons is 0.
A semiconductor device having a performance of 1 to 1 cm ² / V · sec, which is smaller than three digits, and which is worth integration, cannot be obtained. Still high speed and big
on Does not require current. For example, it is possible to obtain a switching array of MIS transistors constituting an image display device by combining with a liquid crystal cell.

1 and 2 are plan views of an amorphous silicon MIS transistor developed to achieve the above object, A-
It is a process sectional view on the A'line. First, as shown in FIG. 2A, a first metal layer 2 to be a gate electrode is selectively deposited on an insulating substrate such as a glass plate 1. Then, a first gate insulating layer made of, for example, silicon nitride is formed on the entire surface.
Then, the insulating layer 3, the amorphous silicon layer 4 containing no impurities, and the amorphous silicon layer 5 containing impurities are deposited. In these deposition methods, plasma deposition by glow discharge of a silane-based gas is simple, and ammonia is used to obtain silicon nitride in the gate insulating layer 3 and amorphous silicon containing impurities is used to obtain silicon nitride in the gate insulating layer 3. For example, diborane or phosphine may be added.

After that, as shown in FIG. 2 (b), the amorphous silicon layers 4 and 5 are formed.
Are selectively removed to form island-shaped amorphous silicon layers 4'and 5 '.
To form. Further, although not shown in FIG. 2, an opening 6 is formed in the first insulating layer 3 on the first metal layer 2 to partially expose the first metal layer 2 and then shown in FIG. 2 (c). First to be a gate electrode so that it does not have an offset gate structure
1 of a second metal layer that partially overlaps the metal layer 2 of
A pair of source and drain wirings 7 and 8 are selectively deposited. Of course, at this time, the first wiring 9 made of the second metal layer is also formed on the first insulating layer 3 including the opening 6. Finally, as shown in FIG. 2 (d), the impurity-containing amorphous silicon layer 5'on the impurity-free amorphous silicon layer 4'is removed by using the source / drain wirings 7 and 8 as a mask. Amorphous silicon MIS type transistor having the above structure is completed.

Amorphous silicon layers 10 and 1 containing impurities interposed between the source / drain wirings 7 and 8 and the amorphous silicon layer 4 '.
1 is necessary to form a good ohmic contact, and MI is required even if the amorphous silicon layers 10 and 11 are not present.
Operation as an S-transistor is possible, but the tendency for the operating voltage to increase becomes unavoidable. In that case, attention must be paid to the material and deposition method of the source / drain wirings 7 and 8. Amorphous silicon layers 10 and 1 containing impurities
When 1 is interposed, the source / drain wirings 7 and 8 are made of general aluminum.

Now, as shown in FIG. 2 (c), the amorphous silicon layer 5'containing impurities is selectively removed by using the source / drain wirings 7 and 8 as a mask. It has been found that the presence of the amorphous silicon layers 10 and 11 electrically connects the amorphous silicon layers 10 and 11 with each other due to the remaining amorphous silicon layer, thereby increasing the leak current between the source and the drain. However, there is no etching material having a large selection ratio between the amorphous silicon containing impurities and the amorphous silicon not containing impurities, in other words, a large etching speed difference, and hydrofluoric acid: nitric acid = 1: 30. Even if an appropriate amount of acetic acid is added to the liquid, the selection ratio is about 5 at best. That is, it is extremely difficult to selectively remove only the amorphous silicon layer containing impurities.

Therefore, normally, as shown in FIG. 2 (d), when removing the amorphous silicon layer 5'containing impurities, the amorphous silicon layer 4'containing no impurities is also partially removed by over-etching to form a concave shape. It is generally set to 12. As a result, although the increase of the leak current can be suppressed, the film thickness of the amorphous silicon layer 4'which does not contain the impurity and becomes the channel of the MIS transistor is surely reduced. Certain combination, first
Is amorphous when molybdenum is used for the metal layer 2, amorphous silicon layer 5 containing phosphorus as an impurity, aluminum is used for the source / drain wirings 7 and 8 and the etching solution is hydrofluoric acid: nitric acid = 1: 30. The etching rate of the silicon layer is multiplied by about 5 to 10 times, and the amorphous silicon layer 4'containing no 5000 liters of impurities disappears in only 4 to 5 seconds.

If the channel section becomes too thin, the MIS transistor will turn on.
It is not uncommon for the current to decrease significantly and to be less than 1/10 of the case of proper etching. To complicate matters, in FIG. 2 (d) of the conventional structure example, since the opposite side of the channel is exposed to the outside air, it is easy to adsorb moisture in the atmosphere. Since the OH ^- group in the adsorbed water turns the channel part into p-type, n
The threshold voltage of the channel operation MIS transistor increases with time. That is, if the operating voltage is constant, the on-current between the source and drain decreases with the passage of time. However, it was found that the moisture adsorbed by heating in a dry nitrogen gas at about 150 ° C. was lost, and the characteristics immediately after production were restored.

Thus, the MIS of amorphous silicon according to the conventional structure example
In the case of the n-type transistor, the unevenness of the characteristics due to the film slip in the channel part cannot be avoided, and the reliability is extremely unstable. The present invention has been made in view of such a situation,
The main point lies in the introduction of an insulating layer that shields the channel portion from the outside air, and an embodiment of the present invention will be described below with reference to FIG. It should be noted that each part having the same function is given the same number as in FIGS.

First, as shown in FIG. 3 (a), a first metal layer 2 to be a gate is selectively deposited on the insulating substrate 1. Then, a first insulating layer 3 to be a gate insulating layer, an amorphous silicon layer 4 containing no impurities, and a second insulating layer 13 made of, for example, silicon nitride are sequentially deposited on the entire surface. The deposition is preferably performed in the same chamber or in a plurality of chambers with a vacuum transfer path so that each deposition is not exposed to the atmosphere.
For this purpose, a deposition method by glow discharge decomposition of a silane-based gas is simple. Next, as shown in FIG. 3 (b), the second
Of the first insulating layer 13 is formed with a pair of openings 14 partially overlapping with the first metal layer 2 so that a part 13 'of the second insulating layer 13 is smaller than the first metal layer 2 serving as a gate. Leave it in
After selectively exposing the amorphous silicon layer 4 containing no impurities, the amorphous silicon layer 5 containing impurities is deposited on the entire surface. Thereafter, as shown in FIG. 3 (c), the amorphous silicon layer 5, the second insulating layer 13, and the amorphous silicon layer 4 are selectively removed in order to include the opening, Island-shaped amorphous silicon layers 5 ', 4'having a size larger than that of the metal layer 2 are formed. Although not shown, an opening 6 (shown in FIG. 1) for connecting to the first metal layer 2 is formed in the first insulating layer 3, and then a metal layer is deposited on the entire surface to remove impurities. Source / drain wirings 7 and 8 on the first insulating layer 3 including the amorphous silicon layer 5'containing impurities deposited on the amorphous silicon layer 4'not containing A gate wiring 9 is formed on the first insulating layer 3 including the opening 6.
Finally, using the source / drain wirings 7 and 8 as a mask, the second
Amorphous silicon layer 5'containing impurities on the insulating layer 13 '
And the MIS according to the present invention as shown in FIG. 3 (d).
The transistor is completed.

As is clear from a comparison between FIG. 2 (d) and FIG. 3 (d), in the step of selectively removing the amorphous silicon layer 5'containing impurities using the source / drain wirings 7 and 8 as masks. According to the present invention, the presence of the second insulating layer 13 'does not etch the amorphous silicon layer 4 which does not contain impurities and serves as a channel portion. Therefore, variations in transistor characteristics due to film slippage in the channel portion do not occur. At the same time, the second insulating layer 13 'shields the amorphous silicon layer 4', which does not contain impurities, which constitutes the channel portion, from the atmosphere. Therefore, even if moisture in the air is adsorbed, the channel portion does not reach the p-type through the second insulating layer 13 ', and the operation is stable even for a long time operation. Of course, passivation in the general sense, that is, the same effect can be expected by depositing an appropriate insulating layer on the entire surface in the step after FIG. 2 (d), but the source / drain wirings 7 and 8 are The presence of the passivation insulating layer is apt to be contaminated by the metal, and depending on the material, the passivation insulating layer and the source / drain wiring may be combined to cause the source / drain wiring.
There is a drawback that the resistance value of the drain wiring layer becomes high. On the other hand, in the present invention, the second insulating layer 13 having the passivation function is formed following the deposition of the amorphous silicon layer 4 containing no impurities, so that the amorphous silicon layer and the second insulating layer are formed. The interface with and the second insulating layer itself have high purity at a semiconductor level, and the introduction of the second insulating layer that is also a passivation film has an excellent effect that various characteristics of the MIS transistor do not change.

As is clear from the above description, the gist of the present invention is applicable to all silicon semiconductors other than single crystal silicon, and in addition to the amorphous silicon mentioned in the examples, microcrystalline silicon and polycrystalline silicon are also applicable. There is no problem. Also the first
Needless to say, silicon oxide or silicon carbide may be appropriately used for the second insulating layer in addition to silicon nitride.

[Brief description of drawings]

FIG. 1 is a plan view of a conventional MIS type transistor, and FIGS. 2 (a) to 2 (d) are AA 'of the transistor of FIG.
3 (a) to 3 (d) are cross-sectional views of the manufacturing process of the MIS transistor according to the embodiment of the present invention. 1 ... Insulating substrate, 2 ... First metal layer, 3 ... First insulating layer, 4, 4 '... Amorphous silicon layer containing no impurities, 5, 5' ... containing impurities Silicon layer, 7, 8 ...
Source / drain wiring, 9 ... Gate wiring, 10, 11
... Amorphous silicon layer, 13, 13 '... Second insulating layer.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Sadakichi Hotta 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Hiroki Saito, 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd. 72) Inventor Shigenobu Shirai 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) Reference JP-A-58-112365 (JP, A)

Claims (1)

[Claims] 1. A step of selectively depositing and forming a first metal layer to be a gate on an insulating substrate, and a first insulating layer to be a gate insulating layer and impurities are included on the entire surface of the insulating substrate. A first non-single-crystal silicon layer and a second insulating layer are sequentially deposited, and the second insulating layer is selectively removed to form the gate on the first metal layer to be the gate. A step of leaving the second insulating layer having a size smaller than that of the first metal layer to be a gate so as to face the gate metal layer, and depositing a second non-single-crystal silicon layer containing impurities on the entire surface. And a step of selectively removing the non-single-crystal silicon layer to form a non-single-crystal silicon layer composed of the second and first non-single-crystal silicon layers on the first insulating layer formed on the entire surface. A step of forming an island shape having a size larger than that of the gate metal layer, and a second gold layer on the entire surface. Forming a source / drain wiring by selectively removing the second metal layer on the second insulating layer after depositing a layer, and using the source / drain wiring as a mask And a step of removing the non-single-crystal silicon layer containing impurities on the layer.