JPH0652818B2 - Method for manufacturing semiconductor laser device - Google Patents
Method for manufacturing semiconductor laser deviceInfo
- Publication number
- JPH0652818B2 JPH0652818B2 JP59049033A JP4903384A JPH0652818B2 JP H0652818 B2 JPH0652818 B2 JP H0652818B2 JP 59049033 A JP59049033 A JP 59049033A JP 4903384 A JP4903384 A JP 4903384A JP H0652818 B2 JPH0652818 B2 JP H0652818B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- active layer
- insulating film
- semiconductor laser
- laser device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/30—Structure or shape of the active region; Materials used for the active region
- H01S5/32—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/0201—Separation of the wafer into individual elements, e.g. by dicing, cleaving, etching or directly during growth
- H01S5/0202—Cleaving
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
- H01S5/227—Buried mesa structure ; Striped active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
- H01S5/227—Buried mesa structure ; Striped active layer
- H01S5/2275—Buried mesa structure ; Striped active layer mesa created by etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
- H01S5/227—Buried mesa structure ; Striped active layer
- H01S5/2275—Buried mesa structure ; Striped active layer mesa created by etching
- H01S5/2277—Buried mesa structure ; Striped active layer mesa created by etching double channel planar buried heterostructure [DCPBH] laser
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/83—Electrodes
- H10H20/831—Electrodes characterised by their shape
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Optics & Photonics (AREA)
- Semiconductor Lasers (AREA)
Description
【発明の詳細な説明】 〔技術分野〕 本発明は半導体レーザ素子、特に、埋め込みヘテロ構造
（ＢＨ；buried-hetero structure）の半導体レーザ素
子に関する。Description: TECHNICAL FIELD The present invention relates to a semiconductor laser device, particularly to a semiconductor laser device having a buried hetero structure (BH).
光通信用光源あるいはデジタルオーディオディスク，ビ
デオディスク等の情報処理装置用光源の一つとして、た
とえば、日経エレクトロニクス、１９８１年、９月１４
日号，１３８〜１５１頁にも記載されているように、各
種構造の半導体レーザ素子（レーザチップ）が開発され
ている。As one of light sources for optical communication or light sources for information processing devices such as digital audio discs and video discs, for example, Nikkei Electronics, September 1981, September 14
As described in Japanese issue, pages 138 to 151, semiconductor laser devices (laser chips) having various structures have been developed.
ところで、本出願人は、たとえば、日立評論，Vol.65,N
o.10（１９８３年），３９頁〜４８頁にも記載されてい
るように、光通信・情報処理用半導体レーザ素子とし
て、ＢＨ型半導体レーザ素子を開発している。By the way, the applicant of the present invention is, for example, Hitachi review, Vol.65, N
O.10 (1983), pp. 39-48, a BH type semiconductor laser device is being developed as a semiconductor laser device for optical communication / information processing.
この半導体レーザ素子は光通信用の半導体レーザ素子の
場合には、InGaAsP系の化合物半導体で構成され、情報
処理用の半導体レーザ素子の場合には、GaAlAs系の化合
物半導体で構成されている。そして、その構造はいずれ
も略同一となっている。This semiconductor laser device is composed of an InGaAsP-based compound semiconductor in the case of a semiconductor laser device for optical communication, and is composed of a GaAlAs-based compound semiconductor in the case of a semiconductor laser device for information processing. And, the structures are almost the same.
ここで、InGaAsP系の半導体レーザ素子について、簡単
に説明する。レーザチップは第１図に示すような構造と
なっていて、製造にあってはｎ形のＩｎ（インジウム）
−Ｐ（燐）の長方形（チップ形成前までは長方形ウエハ
でチップ化によって図のようになる。）の基板１が用い
られる。すなわち、基板１の主面（上面）となる（１０
０）結晶面には液相エピタキシャル法によって、ｎ形Ｉ
ｎＰからなるバッファ層２，Ｉｎ−Ｇａ（ガリウム）−
Ａｓ（ヒ素）−Ｐからなる活性層３，ｐ形InPからなる
クラッド層４，ｐ形InGaAsPからなるキャップ層５が順
次形成される。その後、この多層成長層はブロメタノー
ル等のエッチング液によって部分エッチングされ、５〜
６μｍの幅にストライプ状に形成される。このストライ
プ部は結晶の〈１１０〉方向（劈開方向）に沿って延在
するように設けられる結果、活性層３，クラッド層４，
キャップ層５に亘る部分は断面形状が逆三角形となり、
いわゆる、逆メサ構造となる。この逆メサ構造の側面は
（１１１）結晶面となり、Ｉｎが現れる面となる。ま
た、活性層３の幅は結晶表面から活性層３までの深さ
と、エッチング時にキャップ層５上に設けた絶縁膜から
なるマスクの幅のみによって決まり、エッチング条件に
は左右されないため、再現性良く形成できる。なお、逆
メサ部分の下方は順メサ構造となり、緩やかに広がって
いる。一方、エッチングされて窪んだ部分にはｐ形のＩ
ｎＰからなるブロッキング層６，ｎ形のＩｎＰからなる
埋め込め層７，ｎ形InGaAsPからなるキャップ層８が形
成される。また、メサ部分の表面にはクラッド層４の途
中深さにまで達する亜鉛拡散領域９が形成される。ま
た、基板１の主面上には電極コンタクト部分を除いて絶
縁膜１０が形成される。そして、この絶縁膜１０および
メサ部上には金系電極からなるアノード電極１１が設け
られる。また、基板１の裏面には金系電極からなるカソ
ード電極１２が設けられる。Here, the InGaAsP-based semiconductor laser device will be briefly described. The laser chip has a structure as shown in FIG. 1, and n-type In (indium) is used in manufacturing.
A substrate 1 of -P (phosphorus) rectangle (a rectangular wafer is formed into chips as shown in the figure before the chips are formed) is used. That is, it becomes the main surface (upper surface) of the substrate 1 (10
0) n-type I
nP buffer layer 2, In-Ga (gallium)-
An active layer made of As (arsenic) -P, a clad layer made of p-type InP, and a cap layer 5 made of p-type InGaAsP are sequentially formed. After that, the multilayer growth layer is partially etched by an etching solution such as bromethanol,
It is formed in a stripe shape with a width of 6 μm. This stripe portion is provided so as to extend along the <110> direction (cleavage direction) of the crystal. As a result, the active layer 3, the cladding layer 4,
The cross-sectional shape of the portion extending over the cap layer 5 is an inverted triangle,
It is a so-called inverted mesa structure. The side surface of this inverted mesa structure is a (111) crystal plane, and is a surface on which In appears. Further, the width of the active layer 3 is determined only by the depth from the crystal surface to the active layer 3 and the width of the mask made of the insulating film provided on the cap layer 5 at the time of etching, and is not influenced by the etching conditions, so that the reproducibility is good. Can be formed. The lower part of the reverse mesa has a forward mesa structure, which is gradually widened. On the other hand, a p-type I
A blocking layer made of nP 6, a buried layer 7 made of n-type InP, and a cap layer 8 made of n-type InGaAsP are formed. Further, a zinc diffusion region 9 reaching the midway depth of the cladding layer 4 is formed on the surface of the mesa portion. Further, the insulating film 10 is formed on the main surface of the substrate 1 except for the electrode contact portion. An anode electrode 11 made of a gold-based electrode is provided on the insulating film 10 and the mesa portion. A cathode electrode 12 made of a gold-based electrode is provided on the back surface of the substrate 1.
このような基板１はその一端部にダイヤモンドツール等
で外力が加えられ、結晶の劈開面に沿って定間隔に劈開
用傷が入れられる。その後、ウエハは外部より曲げ応力
が加えられて劈開が行なわれ、短冊状の分断片が形成さ
れる。次いで、この分断片はダイヤモンドツール等によ
って劈開線に直交する方向に定間隔に引っ掻き傷（スク
ライブ）が入れられるとともに、クラッキングによって
スクライブに沿って分断され、多数のレーザチップとな
る。An external force is applied to one end of such a substrate 1 with a diamond tool or the like, and cleavage scratches are made at regular intervals along the cleavage plane of the crystal. After that, the wafer is subjected to a bending stress from the outside and cleaved to form strip-shaped divided pieces. Then, the divided pieces are scratched (scribed) at regular intervals in a direction orthogonal to the cleavage line by a diamond tool or the like, and are divided along the scribe by cracking to be a large number of laser chips.
レーザチップは、たとえば、幅が４００μｍ，長さが３
００μｍ，高さが１００μｍとなり、アノード電極１１
およびカソード電極１２に所定電圧が印加されると、３
００μｍの長さの活性層端面（ミラー面）からレーザ光
を発振する。なお、このレーザチップはアノード電極１
１を介し、あるいはカソード電極１２を介して支持板に
固定されて使用される。The laser chip has, for example, a width of 400 μm and a length of 3
The anode electrode 11 has a height of 00 μm and a height of 100 μm.
When a predetermined voltage is applied to the cathode electrode 12 and 3
Laser light is emitted from the end surface (mirror surface) of the active layer having a length of 00 μm. This laser chip has an anode electrode 1
It is used by being fixed to the support plate via 1 or via the cathode electrode 12.
ところで、このようなレーザチップは、ｐｎ接合への異
物の付着により信頼度が低下するということが本発明者
によってあきらかにされた。By the way, the present inventor has clarified that the reliability of such a laser chip deteriorates due to the adhesion of foreign matter to the pn junction.
すなわち、前記レーザチップはその製造において、ウエ
ハを格子状に分断することによって形成されるが、この
分断時に微細な割れ欠けが発生し、この微細物（異物）
が前記ｐｎ接合に掛けて付着すると、第１図に示すよう
に、この異物１３は導電性であるため、ショートを生じ
てしまう。また、このレーザチップの電極材は展延性に
富んだ金系材料からなっていることから、前述のような
ウエハ分断時にきれいに切れず延びてしまい、電極材が
レーザチップの周縁から部分的に垂れ下がる現象が生じ
てショートしてしまう。ところで、このレーザチップは
ｐｎ接合を形成する活性層部分およびバッファ層２とブ
ロッキング層６との界面部分はいずれも、レーザチップ
の主面から３〜５μｍ程度の深さに位置し極めて浅く、
かつレーザチップの周面に露出している。この結果、第
１図に示すように、前記のような垂れ下がった電極材１
４はｐ形導電領域とｎ形導電領域とを接触させる原因と
なり易く、ショートが発生したり、耐圧が低くなったり
する。That is, in the manufacture of the laser chip, the wafer is formed by dividing the wafer into a lattice shape, but during this division, fine cracks and chips occur, and this fine matter (foreign matter)
When the foreign substance 13 adheres to the pn junction, as shown in FIG. 1, the foreign substance 13 is conductive, so that a short circuit occurs. In addition, since the electrode material of this laser chip is made of a gold-based material with high ductility, it will not be cut cleanly when the wafer is cut as described above, and the electrode material will hang partially from the peripheral edge of the laser chip. A phenomenon occurs that causes a short circuit. By the way, in this laser chip, both the active layer portion forming the pn junction and the interface portion between the buffer layer 2 and the blocking layer 6 are located at a depth of about 3 to 5 μm from the main surface of the laser chip and are extremely shallow.
And it is exposed on the peripheral surface of the laser chip. As a result, as shown in FIG. 1, the sagging electrode material 1 as described above is used.
4 easily causes the p-type conductive region and the n-type conductive region to come into contact with each other, which may cause a short circuit or a low breakdown voltage.
このような異物付着および垂れ下がった電極材の付着現
象は、製品検査時に発生している場合はすぐさま不良品
として排除されるが、異物および垂れ下がった電極材が
ｐｎ接合付近にあっても、製品検査時にはたまたま接触
していないような場合には何等異常を来していないこと
から良品として取り扱われる。しかし、この場合には、
異物および垂れ下がった電極材がいつｐｎ接合部分に付
着して、特性に異常を来すかわからず、極めて信頼性に
乏しいこととなる。If such foreign matter adherence or sagging electrode material adhesion phenomenon occurs during product inspection, it will be immediately rejected as a defective product.However, even if foreign matter and sagging electrode material are near the pn junction, product inspection Occasionally, if there is no contact, it is treated as a good product because there is no abnormality. But in this case,
The foreign matter and the sagging electrode material adhere to the pn junction portion to cause abnormal characteristics, and the reliability is extremely poor.
本発明の目的は高耐圧，高信頼度の半導体レーザ素子を
提供することにある。An object of the present invention is to provide a semiconductor laser device having high breakdown voltage and high reliability.
本発明の他の目的は製造歩留りが高くできる構造の半導
体レーザ素子を提供することにある。Another object of the present invention is to provide a semiconductor laser device having a structure capable of increasing the manufacturing yield.
本発明の他の目的は生産コストの低い半導体レーザ素子
を提供することにある。Another object of the present invention is to provide a semiconductor laser device having a low production cost.
本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel characteristics of the present invention are
It will be apparent from the description of the present specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows.
すなわち、本発明のＢＨ型半導体レーザ素子は、活性層
から遠い位置側のブロッキング層、埋め込み層、キャッ
プ層等の埋め込み層部分およびこれらの層に対応する基
板表層部分を、素子の特性を低下させないことを限度と
して除去して埋め込み層の幅を狭くし、かつそれらの表
面部分を絶縁膜で被うことにより、素子周面に露出する
ｐｎ接合の長さを短くして異物付着の確率を少なくして
ショート発生の機会を少なくするとともに、さらに、前
記埋め込み層および基板を被う前記絶縁膜上に設けられ
た電極の周縁は素子特性を低下させないことを限度とし
て絶縁膜の周縁よりも内側に位置させることにより、素
子周縁における電極の垂れ下がりの発生を防止してショ
ート発生の防止を図り、信頼度および歩留りの向上、コ
ストの低減を達成するものである。That is, in the BH type semiconductor laser device of the present invention, the device characteristics are not deteriorated in the buried layer parts such as the blocking layer, the buried layer, the cap layer, etc. on the side far from the active layer and the substrate surface layer part corresponding to these layers. The width of the burying layer is narrowed by removing the above, and the surface portion thereof is covered with an insulating film to shorten the length of the pn junction exposed on the peripheral surface of the element and reduce the probability of foreign matter adhesion. As a result, the chances of occurrence of a short circuit are reduced, and further, the peripheral edge of the electrode provided on the insulating film covering the buried layer and the substrate is located inside the peripheral edge of the insulating film as long as the element characteristics are not deteriorated. By positioning it, it is possible to prevent the electrode from sagging around the edge of the device to prevent short circuit, improve reliability and yield, and reduce cost. Is shall.
第２図〜第７図は本発明の一実施例によるＢＨ型半導体
レーザ素子の各製造工程におけるワークを示す図であっ
て、第２図はワークであるウエハの断面図、第３図はメ
サエッチングが施されたウエハの断面図、第４図は埋め
込み成長処理が施されたウエハの断面図、第５図は埋め
込み成長層の一部除去処理が施されたウエハの断面図、
第６図は絶縁膜・電極形成処理が施されたウエハの断面
図、第７図は完成状態のＢＨ型半導体レーザ素子を示す
斜視図である。2 to 7 are views showing a work in each manufacturing process of a BH type semiconductor laser device according to an embodiment of the present invention. FIG. 2 is a sectional view of a wafer which is the work, and FIG. 3 is a mesa. FIG. 4 is a cross-sectional view of the wafer subjected to the embedded growth process, FIG. 5 is a cross-sectional view of the wafer subjected to the partial removal process of the embedded growth layer, and FIG.
FIG. 6 is a cross-sectional view of a wafer that has been subjected to an insulating film / electrode forming process, and FIG. 7 is a perspective view showing a completed BH type semiconductor laser device.
この実施例におけるＢＨ型半導体レーザ素子（以下、単
にレーザチップとも称する。）は、第２図〜第６図に示
すように化合物半導体薄板（ウエハ）に順次各種処理が
施された後、第７図に示されるような半導体レーザ素子
となる。In the BH type semiconductor laser device (hereinafter, also simply referred to as a laser chip) in this embodiment, as shown in FIGS. 2 to 6, a compound semiconductor thin plate (wafer) is sequentially subjected to various treatments, and thereafter, a seventh semiconductor laser device. A semiconductor laser device as shown in the figure is obtained.
すなわち、レーザチップの製造に際して、最初に第２図
に示すように、化合物半導体薄板（ウエハ）１５が用意
される。このウエハ１５はｎ形ＩｎＰの基板１と、この
基板１の（１００）結晶面上に液相エピタキシャル法に
よって順次形成されたｎ形InPのバッファ層２，InGaAsP
の活性層３，ｐ形ＩｎＰのクラッド層４，ｐ形InGaAsP
のキャップ層５からなる多層成長層１６と、からなり、
バッファ層２，活性層３，クラッド層４とによってダブ
ルヘテロ接合構造を構成している。前記基板１は２００
μｍ前後の厚さとなり、活性層３は0.15μｍの厚さ、他
の各層はおよそ１〜２μｍ前後の厚さとなっている。That is, when manufacturing a laser chip, first, as shown in FIG. 2, a compound semiconductor thin plate (wafer) 15 is prepared. This wafer 15 is composed of an n-type InP substrate 1, an n-type InP buffer layer 2 and an InGaAsP layer sequentially formed on the (100) crystal plane of the substrate 1 by a liquid phase epitaxial method.
Active layer 3, p-type InP cladding layer 4, p-type InGaAsP
A multi-layered growth layer 16 composed of the cap layer 5 of
The buffer layer 2, the active layer 3 and the cladding layer 4 form a double heterojunction structure. The substrate 1 is 200
The thickness of the active layer 3 is about 0.15 μm, and each of the other layers is about 1 to 2 μm.
つぎに、第３図に示すように、ウエハ１５の主面（上
面）に化学気相堆積（ＣＶＤ）法で絶縁膜（SiO2）が形
成されるとともに、ホトリソグラフィ技術によりこの絶
縁膜は部分的に除去され、〈１１０〉劈開方向と平行に
幅５〜６μｍの多数のストライブ状のマスク１７が形成
される。その後、このウエハ１５のマスク１７から露出
する半導体層はブロメタノール等のエッチング液でエッ
チングされる。エッチングはバッファ層２の途中あるい
は基板１の表層部に達するように行われる。この実施例
ではエッチングはバッファ層２の途中まで達している。
前記マスク１７に被われた活性層３から上方部分は異方
性エッチングの結果、その断面が逆三角形となる逆メサ
部となり結晶の〈１１０〉方向に沿ってストライプ状に
残留し、かつ、活性層３から下方は放物線を描くような
順メサ部となっている。なお、各マスク間隔はおよそ４
００μｍとなっている。Next, as shown in FIG. 3, an insulating film (SiO 2 ) is formed on the main surface (upper surface) of the wafer 15 by a chemical vapor deposition (CVD) method, and this insulating film is partially formed by photolithography. Are removed, and a large number of stripe-shaped masks 17 having a width of 5 to 6 μm are formed in parallel with the <110> cleavage direction. After that, the semiconductor layer exposed from the mask 17 of the wafer 15 is etched with an etching solution such as bromethanol. The etching is performed so as to reach the middle of the buffer layer 2 or the surface layer portion of the substrate 1. In this embodiment, the etching reaches the middle of the buffer layer 2.
As a result of anisotropic etching, a portion above the active layer 3 covered with the mask 17 becomes an inverted mesa portion whose cross section becomes an inverted triangle and remains in a stripe shape along the <110> direction of the crystal, and the active portion is formed. Below layer 3 is a forward mesa part that draws a parabola. Each mask interval is about 4
It is 00 μm.
つぎに、ウエハ１５の主面に部分的に延在するマスク１
７は除去される。その後、第４図に示すように、エッチ
ングによって窪んだ部分にはｐ形ＩｎＰのブロッキング
層６，ｎ形ＩｎＰの埋め込み層７，ｎ形InGaAsPのキャ
ップ層８が順次エピタキシャル法によって埋め込まれ
る、なお、以下において、これら三層全体を単に埋め込
み層とも称する場合がある。Next, the mask 1 partially extending on the main surface of the wafer 15
7 is removed. Thereafter, as shown in FIG. 4, a p-type InP blocking layer 6, an n-type InP burying layer 7, and an n-type InGaAsP cap layer 8 are sequentially buried in the recessed portion by etching by an epitaxial method. Hereinafter, these three layers as a whole may be simply referred to as a buried layer.
つぎに、第５図に示すように、ホトリソグラフィ技術に
よって活性層周辺を除いた埋め込み層部分、すなわち、
活性層３と活性層３の中間部分を除去して、メサ部を中
心として幅がたとえばおよそ１００μｍ程度のメサ部１
８を形成する。なお、除去部の埋め込み層部分を完全に
除去するために、除去は基板１の表層部分にまでおよん
でいる。Next, as shown in FIG. 5, a buried layer portion excluding the periphery of the active layer by the photolithography technique, that is,
The active layer 3 and the intermediate portion of the active layer 3 are removed, and the width of the mesa portion 1 is about 100 μm with the mesa portion as the center.
8 is formed. In addition, in order to completely remove the embedded layer portion of the removed portion, the removal extends to the surface layer portion of the substrate 1.
つぎに、ウエハ１５の主面にはSiO2等からなる絶縁膜１
０が部分形成される。したがって、側面に露出するｐｎ
接合端はこの絶縁膜１０によって被われることになる。
前記絶縁膜１０は第６図で示すように、ウエハ１５の劈
開面と直交する方向の分断領域（幅ａで示すスクライブ
エリア）および逆メサ部の表層部分には設けられていな
い。つぎに、この絶縁膜１０がマスクとなって亜鉛（Ｚ
ｎ）がウエハ１５の主面に打ち込まれ、クラッド層４の
途中深さに達する亜鉛拡散領域９が形成される。この亜
鉛拡散領域９はコンタクト電極のオーミック層になる。
また、このウエハ１５の主面にはアノード電極１１が、
裏面にはカソード電極１２がそれぞれ設けられている。
アノード電極１１および、カソード電極１２はいずれも
蒸着アロイ法によって形成されている。カソード電極１
２はウエハ１５の裏面全域に形成されるが、アノード電
極１１は第７図に示されるように、メサ部１８の全体お
よび基板１に直接載る絶縁膜１０の周縁部分（メサ部１
８に近接している部分は除き、かつ絶縁膜の周縁から数
十μｍの幅領域）を除く部分に渡って設けられている。
すなわち、アノード電極１１もまたウエハ１５の主面に
定間隔にくびれ部を有するストライプパターンとして設
けられている。そして、このくびれ部を繋ぐライン方向
が劈開する面となる。なお、ウエハ１５の裏面にカソー
ド電極１２が形成される前に、ウエハ１５の裏面はエッ
チングされ、ウエハ１５の全体の厚さは１００μｍ程度
とされる。Next, the insulating film 1 made of SiO 2 or the like is formed on the main surface of the wafer 15.
0 is partially formed. Therefore, the pn exposed on the side surface
The junction end is covered with this insulating film 10.
As shown in FIG. 6, the insulating film 10 is not provided on the dividing region (the scribe area indicated by the width a) in the direction orthogonal to the cleavage plane of the wafer 15 and the surface layer portion of the reverse mesa portion. Next, the insulating film 10 serves as a mask for zinc (Z
n) is implanted into the main surface of the wafer 15 to form a zinc diffusion region 9 reaching the middle depth of the cladding layer 4. This zinc diffusion region 9 becomes an ohmic layer of the contact electrode.
In addition, the anode electrode 11 is formed on the main surface of the wafer 15.
Cathode electrodes 12 are provided on the back surface, respectively.
Both the anode electrode 11 and the cathode electrode 12 are formed by a vapor deposition alloy method. Cathode electrode 1
2 is formed on the entire back surface of the wafer 15, the anode electrode 11 is, as shown in FIG. 7, the entire mesa portion 18 and the peripheral portion of the insulating film 10 (mesa portion 1) directly mounted on the substrate 1.
8 is provided over a portion excluding a portion close to 8 and a region excluding a peripheral region of the insulating film having a width of several tens of μm).
That is, the anode electrode 11 is also provided on the main surface of the wafer 15 as a stripe pattern having constrictions at regular intervals. Then, the line direction connecting the constrictions becomes a cleavage plane. Before the cathode electrode 12 is formed on the back surface of the wafer 15, the back surface of the wafer 15 is etched so that the total thickness of the wafer 15 is about 100 μm.
つぎに、このようなウエハ１５はその一端部にダイヤモ
ンドツール等で外力が加えられ、結晶の劈開面に沿って
定間隔に劈開用傷が入れられる。その後、ウエハ１５は
外部より曲げ応力が加えられて劈開が行なわれ、短冊状
の分断片が形成される。次いで、この分断片はダイヤモ
ンドツール等によって劈開線に直交する方向に定間隔に
引っ掻き傷（スクライブ）がスクライブエリアに入れら
れるとともに、クラッキングによってスクライブに沿っ
て分断され、多数のレーザチップが形成される。レーザ
チップ１９の外観形状は第７図に示されるような形状と
なり、その寸法はたとえば、幅が４００μｍ，長さが３
００μｍ，高さが１００μｍとなり、アノード電極１１
およびカソード電極１２に所定電圧が印加されると、３
００μｍの長さの活性層端面（ミラー面）からレーザ光
２０を発振する。なお、このレーザチップ１９はアノー
ド電極１１を介し、あるいはカソード電極１２を介して
支持板に固定されて使用される。たとえば、レーザチッ
プ１９が高熱伝導度ＳｉＣセラミック（熱伝導度；2.5
Ｗ／deg・cm）の支持板にソルダーを介して固定される場
合にはカソード電極１２面を固定面とすることができ、
第７図で示すように、ワイヤ２１は基板１に直接載るア
ノード電極１１部分に接続できる。この場合、ワイヤボ
ンディング時の衝撃は素子特性に殆ど影響がない基板１
部分に加わり、レーザ発振するアクティブ領域（活性層
３，ブロッキング層６等が存在する領域）には加わらな
い。このため、ワイヤボンディング時にワイヤボンディ
ングによってレーザチップ特性が劣化するようなことは
防止できる。Next, an external force is applied to one end of such a wafer 15 by a diamond tool or the like, and cleavage scratches are made at regular intervals along the cleavage plane of the crystal. After that, the wafer 15 is cleaved by applying bending stress from the outside, and strip-shaped divided pieces are formed. Next, this fragment is scratched (scribed) into the scribe area at regular intervals in a direction orthogonal to the cleavage line by a diamond tool or the like, and is divided along the scribe by cracking to form a large number of laser chips. . The external shape of the laser chip 19 is as shown in FIG. 7, and its dimensions are, for example, 400 μm in width and 3 in length.
The anode electrode 11 has a height of 00 μm and a height of 100 μm.
When a predetermined voltage is applied to the cathode electrode 12 and 3
Laser light 20 is oscillated from the end surface (mirror surface) of the active layer having a length of 00 μm. The laser chip 19 is used by being fixed to the support plate via the anode electrode 11 or the cathode electrode 12. For example, the laser chip 19 has a high thermal conductivity SiC ceramic (thermal conductivity; 2.5.
When fixed to a support plate of W / deg.cm) via a solder, the surface of the cathode electrode 12 can be used as a fixed surface,
As shown in FIG. 7, the wire 21 can be connected to the portion of the anode electrode 11 directly mounted on the substrate 1. In this case, the impact during wire bonding has almost no effect on the device characteristics.
It does not add to the active region (the region where the active layer 3 and the blocking layer 6 etc. are present) where the laser oscillation occurs. Therefore, it is possible to prevent the laser chip characteristics from being deteriorated by wire bonding during wire bonding.
１．本発明の半導体レーザ素子は素子の周面に露出する
ｐｎ接合の長さが従来の１／７と極めて短くなったこと
から、ｐｎ接合への異物１３および垂れ下がり電極材１
４の付着確率は遥かに小さくなり、素子の耐圧低下発生
頻度・ショート発生頻度低減が達成でき歩留り向上、信
頼度向上が達成できるという効果がえられる。1. In the semiconductor laser device of the present invention, the length of the pn junction exposed on the peripheral surface of the device is extremely short, which is 1/7 of that of the conventional one. Therefore, the foreign matter 13 to the pn junction and the hanging electrode material 1
The adhesion probability of No. 4 is much smaller, and it is possible to achieve the effect of lowering the frequency of occurrence of withstand voltage decrease and the frequency of occurrence of short circuit of the device, improving yield, and improving reliability.
２．本発明の半導体レーザ素子は上記１のようにｐｎ接
合長が短いことに加えてアノード電極の大半の周縁は絶
縁膜の周縁から内側に数１０μｍ程度引っ込んでいる。
このため、異物付着はもちろんのこと垂れ下がり電極材
の発生があっても、耐圧劣化不良，ショート不良は起き
にくく，歩留り向上，信頼度向上が達成できるという効
果がえられる。2. In the semiconductor laser device of the present invention, in addition to the short pn junction length as described above, most of the peripheral edge of the anode electrode is recessed inward from the peripheral edge of the insulating film by several tens of μm.
For this reason, even if foreign matter is adhered and even if a sagging electrode material is generated, a breakdown voltage deterioration defect and a short circuit defect are unlikely to occur, and the yield and reliability can be improved.
３．本発明の半導体レーザ素子はワイヤ接続部分はレー
ザ発振が行われない基板上方となっていることから、ワ
イヤボンディングが行われても素子特性は劣化せず、高
品位となり、歩留り向上が達成できるという効果がえら
れる。3. In the semiconductor laser device of the present invention, since the wire connection portion is located above the substrate where laser oscillation is not performed, the device characteristics are not deteriorated even if wire bonding is performed, the quality is high, and the yield can be improved. The effect can be obtained.
４．前記１〜３から、本発明の半導体レーザ素子はその
製造において、歩留り向上，信頼度向上が達成できるた
め、製造コストの軽減化が図れる。4. From the above 1 to 3, since the semiconductor laser device of the present invention can be improved in yield and reliability in manufacturing, the manufacturing cost can be reduced.
以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は上記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもない。Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments and various modifications can be made without departing from the scope of the invention. Nor.
以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野である光通信用半導体レー
ザ素子製造技術に適用した場合について説明したが、そ
れに限定されるものではなく、たとえば、情報処理用半
導体レーザ素子製造技術などに適用できる。In the above description, the case where the invention made by the present inventor is mainly applied to the semiconductor laser device manufacturing technology for optical communication which is the field of application which is the background has been described, but the invention is not limited thereto, and for example, information It can be applied to processing semiconductor laser device manufacturing technology.
本発明は少なくとも埋め込みヘテロ構造の半導体レーザ
素子には適用できる。The present invention can be applied to at least a semiconductor laser device having a buried hetero structure.
第１図は従来のＢＨ型半導体レーザ素子を示す斜視図、 第２図は本発明の一実施例によるＢＨ型半導体レーザ素
子の一製造工程におけるウエハの断面図、 第３図は同じくメサエッチングが施されたウエハの断面
図、 第４図は同じく埋め込み成長処理が施されたウエハの断
面図、 第５図は同じく埋め込み成長層の一部除去処理が施され
たウエハの断面図、 第６図は同じく絶縁膜・電極形成処理が施されたウエハ
の断面図、 第７図は同じく完成状態のＢＨ型半導体レーザ素子を示
す斜視図である。 １…基板、２…バッファ層、３…活性層、４…クラッド
層、５…キャップ層、６…ブロッキング層、７…埋め込
み層、８…キャップ層、９…亜鉛拡散領域、１０…絶縁
膜、１１…アノード電極、１２…カソード電極、１３…
異物、１４…垂れ下がり電極材、１５…化合物半導体薄
板（ウエハ）、１６…多層成長層、１７…マスク、１８
…メサ部、１９…レーザチップ、２０…レーザ光、２１
…ワイヤ。FIG. 1 is a perspective view showing a conventional BH type semiconductor laser device, FIG. 2 is a sectional view of a wafer in one manufacturing process of the BH type semiconductor laser device according to one embodiment of the present invention, and FIG. FIG. 4 is a sectional view of a wafer that has been similarly subjected to embedded growth processing, FIG. 5 is a sectional view of a wafer that has been similarly subjected to partial removal processing of an embedded growth layer, and FIG. Is a sectional view of a wafer similarly subjected to an insulating film / electrode forming process, and FIG. 7 is a perspective view showing a BH type semiconductor laser device similarly in a completed state. 1 ... Substrate, 2 ... Buffer layer, 3 ... Active layer, 4 ... Clad layer, 5 ... Cap layer, 6 ... Blocking layer, 7 ... Buried layer, 8 ... Cap layer, 9 ... Zinc diffusion region, 10 ... Insulating film, 11 ... Anode electrode, 12 ... Cathode electrode, 13 ...
Foreign matter, 14 ... Hanging electrode material, 15 ... Compound semiconductor thin plate (wafer), 16 ... Multilayer growth layer, 17 ... Mask, 18
... Mesa part, 19 ... Laser chip, 20 ... Laser beam, 21
… Wire.
Claims (1)
れた両積層界面がヘテロ接合となる活性層を形成する工
程と、この活性層の両側にそれぞれ形成されかつ活性層
との間にヘテロ接合を形成する埋め込み層を形成する工
程とを有する半導体レーザ素子の製造方法であって、 前記活性層周辺の領域を残して埋め込み層を除去する工
程と、スクライブエリアを除いた基板の主面及び残った
埋め込み層を覆う絶縁膜を形成する工程と、この絶縁膜
上に、活性層上部で絶縁膜を貫通して活性層の所定導電
領域に電気的に接続し、該活性層の上部全域及び前記基
板上に直接形成された絶縁膜周縁より内側に位置する領
域に電極を形成する工程とを有することと、 該活性層上からずれて基板上に直接形成位置された絶縁
膜上に形成されている電極部分に対してワイヤボンディ
ングを行なうこととを特徴とする半導体レーザ素子の製
造方法。1. A step of forming an active layer in which both laminated interfaces formed on one main surface of a substrate made of a semiconductor form a heterojunction, and between the active layer formed on both sides of the active layer. A method of manufacturing a semiconductor laser device, comprising the step of forming a buried layer forming a heterojunction, the step of removing the buried layer leaving a region around the active layer, and the main surface of the substrate excluding the scribe area. And a step of forming an insulating film covering the remaining buried layer, and electrically connecting to a predetermined conductive region of the active layer on the insulating film by penetrating the insulating film on the active layer, and the entire upper part of the active layer. And a step of forming an electrode in a region located inside a peripheral edge of the insulating film directly formed on the substrate, and forming on an insulating film directly formed on the substrate while being displaced from the active layer. Electrode part The method of manufacturing a semiconductor laser device and in that wire bonding is performed with respect to.
Priority Applications (10)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59049033A JPH0652818B2 (en) | 1984-03-16 | 1984-03-16 | Method for manufacturing semiconductor laser device |
| GB08502982A GB2156585B (en) | 1984-03-16 | 1985-02-06 | Light-emitting device electrode |
| GB08502981A GB2156584B (en) | 1984-03-16 | 1985-02-06 | Semiconductor laser chip |
| KR1019850001289A KR930004127B1 (en) | 1984-03-16 | 1985-02-28 | Light emitting device |
| US06/712,028 US4731790A (en) | 1984-03-16 | 1985-03-15 | Semiconductor laser chip having a layer structure to reduce the probability of an ungrown region |
| US06/712,029 US4692927A (en) | 1984-03-16 | 1985-03-15 | Light emitting device with improved electrode structure to minimize short circuiting |
| DE3509441A DE3509441C2 (en) | 1984-03-16 | 1985-03-15 | Semiconductor laser chip |
| US07/078,097 US4785455A (en) | 1984-03-16 | 1987-07-27 | Light emitting device with improved electrode structure to minimize short circuiting |
| US07/098,198 US4849982A (en) | 1984-03-16 | 1987-09-17 | Semiconductor laser chip having a layer structure to reduce the probability of an ungrown region |
| US07/615,827 USRE34378E (en) | 1984-03-16 | 1990-11-15 | Light emitting device with improved electrode structure to minimize short circuiting |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59049033A JPH0652818B2 (en) | 1984-03-16 | 1984-03-16 | Method for manufacturing semiconductor laser device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60194590A JPS60194590A (en) | 1985-10-03 |
| JPH0652818B2 true JPH0652818B2 (en) | 1994-07-06 |
Family
ID=12819775
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59049033A Expired - Lifetime JPH0652818B2 (en) | 1984-03-16 | 1984-03-16 | Method for manufacturing semiconductor laser device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0652818B2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60169184A (en) * | 1984-02-13 | 1985-09-02 | Mitsubishi Electric Corp | Semiconductor laser |
-
1984
- 1984-03-16 JP JP59049033A patent/JPH0652818B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60194590A (en) | 1985-10-03 |
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