JPH0654784B2 - Semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device for a complementary field effect transistor that controls the flow rates of high mobility electrons and holes distributed in a two-dimensional state by an electric field. Regarding

(Prior Art) A GaAs complementary field-effect transistor (hereinafter referred to as a field-effect transistor FE) that utilizes conduction of electrons and holes.
Referred to as T) in the literature (IEEE Electron Device Letters ED
L-5 , [1] (1984) p. 21). This conventional
The structure of the GaAs complementary FET is shown in a sectional view in FIG. In FIG. 6, 51 is a semi-insulating GaAs substrate, and T ₁ and T ₂ are an n-channel FET and a p-channel FET built in this substrate 51. 52 is a Si ₃ N ₄ insulating film, 53 is an n ⁺ -GaAs region implanted with Si ions as donor ions, 54 is a p ⁺ -GaAs region implanted with Mg ions as acceptor ions, and 55 is Si ions implanted as donor ions N-GaAs layer serving as an n-channel layer, and 56 is p-GaAs serving as a p-channel layer into which Mg ions are implanted as acceptor ions.
Layer, 57 is an Au / Ge ohmic electrode layer that serves as the source and drain electrodes of the n-channel FET T ₁ , 58 is a p-channel FET
The Pt / Au ohmic electrode layer serving as the source and drain electrodes of T ₂ , and 59 is the Pt / Au ohmic electrode layer serving as the gate electrode of the n-channel FET T _1.
An Au ohmic electrode layer, 60 is an Au.Ge ohmic electrode that serves as a gate electrode of a p-channel FET.

Each FET T _{1 and} T ₂ is electrically connected to the outside of the structure shown in the figure so as to form a complementary FET, and is controlled by the bias voltage applied to the gate electrodes 59 and 60, so that one FET T ₁ or When T ₂ turns on, the other F
It operates so that ETT ₂ or T ₁ is turned off.

(Problems to be Solved by the Invention) By the way, the n-channel FET T ₁ and the p-channel FET T ₂ having such a structure are prepared by injecting a donor ion and an acceptor ion into one common semi-insulating substrate 51 to generate electrons and holes. The conductive layer is formed to operate in the enhancement mode. However, since the n-channel layer 55 and the p-channel layer 56 are formed by ion implantation, the impurity scattering becomes large, so that the mobility of electrons and holes becomes small, and therefore both the FETs T ₁ and T ₂ are complemented. When operated as a combination,
There is a drawback that the delay time per gate becomes long and high speed operation cannot be performed.

It is an object of the present invention to use two types of FEs utilizing a high mobility two-dimensional electron and hole flow, which are suitable for combination as a complementary FET capable of low power consumption and high speed operation.
It is to provide a semiconductor device having T.

(Means for Solving the Problems) The main point of the present invention is to include a modulation doping layer of the first conductivity type and a second conductivity type in a multi-layer structure laminated on the same substrate to accumulate high mobility. The flow of the two-dimensional electrons and holes in (3) can be controlled individually by the gate bias voltage.

Therefore, according to the semiconductor device of the present invention, the first conductivity type channel field effect transistor includes the first conductivity type channel field effect transistor and the second conductivity type channel field effect transistor formed on the upper side of the same substrate. Is a small electron affinity, the sum of the electron affinity and the energy gap is large and the first semiconductor layer doped with the first conductivity type impurity, and provided on the upper side of the first semiconductor layer, the electron affinity is large, A second semiconductor layer having a small sum of electron affinity and energy gap and no impurities, and a first source, drain and gate electrodes provided on the second semiconductor layer, wherein the second conductivity type channel electric field The effect transistor is provided on the first semiconductor layer, the second semiconductor layer, and the second semiconductor layer, and has a small electron affinity. A third semiconductor layer having a large sum of a child affinity and an energy gap and having a second conductivity type impurity added thereto, and a second source, drain and gate electrodes provided on the upper side of the third semiconductor layer, The two semiconductor layers form a quantum well of potential,
The quantum well has a structure in which first and second conductivity type carriers are separated and accumulated, and the first and second conductivity type carriers form channels of the first and second conductivity type channel field effect transistors, respectively. ing.

(Operation) According to such a configuration, the first semiconductor layer of the first conductivity type channel field effect transistor and the third semiconductor layer of the second conductivity type channel field effect transistor are modulation doping layers, respectively, and Since the second semiconductor layer of the first conductivity type and the second conductivity type channel field effect transistor is a layer with few impurities and forms a quantum well,
Since high mobility first and second conductivity type carriers can be stored separately in this quantum well, a large transconductance gm is obtained.

Further, since the second semiconductor layer is thus provided so as to be a common quantum well of carriers of both conductivity types, the structure of the semiconductor device is simplified as a whole and the manufacturing process is simplified.

Further, since the first conductivity type channel field effect transistor and the second conductivity type channel field effect transistor are provided on the upper side of the same substrate, when both transistors are combined as a complementary field effect transistor, ultra low power consumption and high speed are achieved. It is possible to obtain a complementary field effect transistor for operation, and therefore, this semiconductor device can be used for a very large scale integrated circuit.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

Description of Structure FIGS. 1 (A) and 1 (B) are schematic cross-sectional views showing second conductivity type and first conductivity type channel field effect transistors T ₂ and T ₁ , respectively, which constitute a semiconductor device of the present invention. These transistors T ₁ and T ₂ are a semi-insulating GaAs substrate as a substrate 1 and an undoped Al _0.3 Ga _0.7 As layer having a thickness of about 1000 Å as an undoped (hereinafter referred to as undoped) layer 2 laminated thereon. It is provided on a common underlayer 3 composed of layers.

In this embodiment, the first conductivity type is n-type and the second conductivity type is p-type.
Use as a mold. Therefore, FIG. 1 (A) shows the p-channel FET T _2, and FIG. 1 (B) shows the n-channel FET T ₁ .

In FIGS. 1 (A) and (B), 4 has a small electron affinity,
The sum of this electron affinity and energy gap is large,
In addition, in the first semiconductor layer doped with the first conductivity type impurity, therefore, in this case, Si is added in an amount of about 3 × 10 ¹⁸ cm ⁻³ and n ⁺ -Al _0.3 having a thickness of about 200 Å. Ga _0.7 As layer. 5 is a first spacer layer laminated on this layer 4,
For example, an undoped Al _0.3 Ga _0.7 As layer having a thickness of about 60Å. 6 is laminated on the first spacer layer 5, for example,
The electron affinity is large, the sum of the electron affinity and the energy gap is small, and the thickness of the undoped GaAs layer which is the undoped second semiconductor layer is set to about 700Å. A second spacer layer 7 is laminated on the layer 6, and is, for example, an undoped Al _0.3 Ga _0.7 As layer having a thickness of about 60Å.

Reference numeral 8 denotes a third semiconductor layer laminated on the layer 7, for example, having a small electron affinity, a large sum of the electron affinity and the energy gap, and having a second conductivity type impurity added thereto. In this case, a p ⁺ -Al _0.3 Ga _0.7 As layer with a thickness of about 400 Å is prepared by adding Be in an amount of 3 × 10 ¹⁸ cm ^-3 .

Reference numeral 9 denotes a second-conductivity-type carrier accumulated in the quantum well formed by the second semiconductor layer, which is a two-dimensional hole gas in this case. This two-dimensional hole gas is accumulated at the junction interface with the undoped Al _0.3 Ga _0.7 As layer 7 in the undoped GaAs layer 6.

Further, 10 is a contact layer provided on the p ⁺ -Al _0.3 Ga _0.7 As layer 8. This contact layer 10 is, for example, a p ⁺ -GaAs layer having a thickness of about 500 Å to which Be is added in an amount of about 3 × 10 ¹⁸ cm ^-3. The parasitic resistance can be reduced and the contact resistance of the ohmic electrode can be reduced. Further, 11 and 12 are a second source electrode and a second drain electrode, for example, AuBe electrode layers forming ohmic contact with the lower p-type contact layer 10. Reference numeral 13 is a second gate electrode, for example, for forming a junction with the p ⁺ -Al _0.3 Ga _0.7 As layer which is the lower third semiconductor layer 8.
It consists of an Al electrode layer. Reference numeral 14 denotes a second high impurity concentration region to which a second conductivity type impurity is added. For example, AuBe reaches the second semiconductor layers 6 below the second source electrode 11 and the second drain electrode 12, respectively. This is the diffused p ⁺ − region.

Each of the constituent components 4 to 14 has a second conductivity type channel FE.
It forms TT ₂ (Fig. 1 (A)).

Further, as shown in FIG. 1 (B), 15 is a first source electrode and 16 is a first drain electrode, both of which are, for example, an AuGe electrode layer which is ohmic with the second semiconductor layer 6 on the lower side. And 17 is a first gate electrode similar to the second gate electrode. Reference numeral 18 denotes a first high-impurity concentration region to which an impurity of the first conductivity type is added. In this case, AuGe is used as the second source electrode 15
And the n ⁺ − region diffused to reach the first semiconductor layer 4 below the second drain electrode 16. Further, in this case, since the second spacer layer 7 and the third semiconductor layer 8 are provided only under the second gate electrode, the undoped Al _0.3 Ga in the undoped GaAs layer of the second semiconductor layer 6 is not formed. Two-dimensional electron gas, which is the first conductivity type carrier 19, is accumulated at the junction interface with the _0.7 As layer 5.

The components 4 to 6 and 15 to 19 form the first conductivity type channel FET T ₁ . In this case, leaving the layers 7 and 8 under the second gate electrode reduces the etching amount of the gate portion, which is closely related to the threshold voltage control, and simplifies the processing of the semiconductor device having this structure. This is because.

Description of Energy Band Structure FIGS. 2 (A) and 2 (B) show the p-channel FET T having the above structure.
FIG. 3 is a diagram showing the energy band structures of a ₂ and n-channel FET T ₁ , respectively. In the figure, 20 indicates the Fermi level, and the other regions are indicated by the respective layers shown in FIGS. 1 (A) and (B) and other corresponding numbers.

In the energy band structure shown in FIG. 2 (A), n ⁺ and p ⁺
-Al _0.3 Ga _0.7 As layers 4 and 8 are modulation doping layers,
Moreover, the undoped GaAs layer 6 serves as a potential quantum well. Therefore, the holes in the p ⁺ -Al _0.3 Ga _0.7 As layer 8 are diffused in the undoped GaAs layer 6 and accumulated as the two-dimensional hole gas 9. Therefore, when an electric field is applied by the second source electrode 11 and the second drain electrode 12 in a direction parallel to the interface of the undoped GaAs layer 6, these two-dimensional hole gases are conducted with high mobility.

In this case, even if the two-dimensional electron gas is accumulated at the bonding interface of the second semiconductor layer 6 with the first spacer layer 5, the lower side of the second source and drain electrodes 11 and 12 is the p ⁺ − region.
At 14, these electron gases do not contribute to conduction.

In the band structure of the n-channel FET T ₁ shown in FIG. 2 (B), the n ⁺ -Al _0.3 Ga _0.7 As layer 4 is a modulation doping layer,
Electrons in n ⁺ -Al _0.3 Ga _0.7 As layer 4 are undoped GaAs layer 6
It diffuses inside and is accumulated as a two-dimensional electron gas 19.
Therefore, when an electric field is applied by the first source electrode 15 and the first drain electrode 16 in a direction parallel to the interface of the undoped GaAs layer 6, these two-dimensional electron gases are conducted with high mobility.

Description of operation When a negative bias voltage is applied to the second gate electrode 13 of the p-channel FET T ₂ , as shown in FIG. 3 (A), the undoped GaAs layer 6, the undoped Al _0.3 Ga _0.7 As layer 7 and p ⁺ −
The energy level of the Al _0.3 Ga _0.7 As layer 8 shifts to the upper side, and the two-dimensional hole gas 9 is induced in the GaAs layer 6 at the junction interface side with the undoped Al _0.3 Ga _0.7 As layer 7. Therefore,
The two-dimensional hole gas 9 is distributed and accumulated at the junction interface on the layer 7 side in the quantum well formed by the GaAs layer 6 to form a p-channel. The two-dimensional hole gas 9 does not flow out to the second gate electrode 13 because the potential barrier of the layer 8 is high even when the gate bias voltage is applied.

Similarly, when a positive bias voltage is applied to the first gate electrode 17 of the n-channel FET T ₁ , as shown in FIG. 3 (B), the undoped GaAs layer 6, the undoped Al _0.3 Ga _0.7 As layer 7 and the p ⁺ -al _0.3 Ga _0.7 energy levels of as layer 8 is in the GaAs layer 6 is shifted to the lower side, undoped Al _0.3 Ga _0.7
Two-dimensional electron gas 19 is induced at the junction interface side with As layer 5,
Therefore, the two-dimensional electron gas 19 is distributed and accumulated at the junction interface on the layer 5 side in the quantum well formed by the GaAs layer 6 to form an n-channel. The two-dimensional electron gas 19 does not flow out to the second gate electrode 17 because the potential barrier of the layer 8 is high even when the gate bias voltage is applied.

FIGS. 4A and 4B are diagrams showing the structure and energy band structure of the first conductivity type channel FET T ₁ for explaining another embodiment of the present invention. In this embodiment, the first gate electrode 17 is directly provided on the undoped GaAs layer which is the second semiconductor layer 6. Also in this case, as in the case of the above-described embodiment, the two-dimensional electron gas 19 is distributed and accumulated at the junction interface on the layer 5 side in the quantum well formed by the GaAs layer 6 to form an n-channel. The two-dimensional electron gas 19 does not flow out to the second gate electrode 17 because the potential barrier of the layer 8 is high even when the gate bias voltage is applied.

5 (A) and 5 (B) are diagrams showing an energy band structure for explaining still another embodiment of the present invention.

In this embodiment, the first semiconductor layer 4 is doped with Be impurities.
A p ⁺ -Al _0.3 Ga _0.7 As layer is used, the first conductivity type carrier 19 is used as a two-dimensional hole gas, and the third semiconductor layer 8 is doped with Si impurities to form an n ⁺ -Al _0.3 Ga _0.7 As layer. Layer 10 to n ⁺ −GaAs
Layer, the second source and drain electrodes 11 and 12 are formed of AuGe ohmic electrodes, and the second high impurity concentration region 14 is formed of Au.
N ⁺ − region by diffusion of Ge, and further, the first source and drain electrodes 15 and 16 are formed of AuBe electrode layer, and
The energy band structures of the n-channel FET T ₁ and the p-channel FET T ₂ of the semiconductor device having a structure in which the first high impurity concentration region 18 is a p ⁺ − region due to AuBe diffusion are shown, respectively. Even in the case of this structure, the operation is similar to that of the above-described embodiment.

Although the first and second spacer layers 5 and 7 having a thickness of about 60 Å are stacked in the structure of each of the above-described embodiments, these spacer layers 5 and 7 are accumulated in the second semiconductor layer 6. When a high mobility two-dimensional electron or hole is conducted in parallel to these layers 5 and 7, Si donor ions and Be acceptor ions formed in the first semiconductor layer 4 and the third semiconductor layer 8 respectively. By the Coulomb scattering, it functions to prevent the mobility of holes or electrons from decreasing. However, these spacer layers 5 and 7 are not always necessary layers.

The semiconductor device of the present invention includes the above-mentioned GaAs and Al _0.3 Ga _0.7 As.
It can be realized by changing the combination of layers. For example, In _0.53
Ga _0.47 As / InP or Ga _0.47 In _0.53 As / Al _0.48 In _0.52 As can also be used. In this case, GaAs is In _0.53 Ga _0.47 As
, Replace Al _0.3 Ga _0.7 As with InP, or replace GaAs with Ga.
_{It is sufficient} to substitute _0.47 In _0.53 As and Al _0.3 Ga _0.7 As with Al _0.48 In _0.52 As.

(Effect of the Invention) As is apparent from the above description, according to the semiconductor device of the present invention, the first semiconductor layer of the first conductivity type channel field effect transistor and the third semiconductor layer of the second conductivity type channel field effect transistor. Are modulation doping layers, and the second semiconductor layers of the first and second conductivity type channel field effect transistors are layers with few impurities and form a quantum well. Since the first and second conductivity type carriers having mobility can be separately stored, a large transconductance gm is obtained.

Further, since the second semiconductor layer is thus provided so as to be a common quantum well of carriers of both conductivity types, the structure of the semiconductor device is simplified as a whole and the manufacturing process is simplified.

Further, since the first conductivity type channel field effect transistor and the second conductivity type channel field effect transistor are provided on the upper side of the same substrate, when both transistors are combined as a complementary field effect transistor, ultra low power consumption and high speed are achieved. It is possible to obtain a complementary field effect transistor for operation, and therefore, this semiconductor device can be used for a very large scale integrated circuit.

[Brief description of drawings]

1 (A) and 1 (B) are schematic sectional views for explaining an embodiment of a semiconductor device of the present invention, FIGS. 2 (A) and (B), and FIG. 3 (A). 1 and (B) are diagrams showing an energy band structure used for explaining the semiconductor device having the structure of FIG. 1, and FIGS. 4 (A) and (B) are for explaining another embodiment of the semiconductor device of the present invention. FIG. 3 is a schematic cross-sectional view and a diagram showing an energy band structure. 5 (A) and 5 (B) are schematic diagrams showing an energy band structure for explaining another embodiment of the present invention, and FIG. 6 is a sectional view for explaining a conventional semiconductor device. T ₁ …… first conductivity type channel field effect transistor T ₂ …… second conductivity type channel field effect transistor 1 …… substrate 2 …… impurity-free layer 3 …… base layer 4 …… first semiconductor layer 5 ...... First spacer layer, 6 ...... Second semiconductor layer 7 ...... Second spacer layer, 8 ...... Third semiconductor layer 9 ...... Second conductivity type carrier 10 ...... Contact layer 11 ...... Second source electrode , 12 ...... Second drain electrode 13 ...... Second gate electrode 14 ...... Second high impurity concentration region 15 ...... First source electrode, 16 ...... First drain electrode 17 ...... First gate electrode, 18 ...... First high impurity concentration region 19 …… First conductivity type carrier 20 …… Fermi level.

Claims (5)

[Claims] 1. A first conductivity type channel field effect transistor and a second conductivity type channel field effect transistor formed on the same substrate, wherein the first conductivity type channel field effect transistor has a small electron affinity. A first semiconductor layer having a large sum of the electron affinity and the energy gap and added with a first conductivity type impurity, and provided on the upper side of the first semiconductor layer and having a large electron affinity, the electron affinity and the energy gap And a second semiconductor layer having a small sum of impurities and no impurity, and a first source, drain and gate electrodes provided on the second semiconductor layer, wherein the second conductivity type channel field effect transistor is One semiconductor layer, the second semiconductor layer, and the second semiconductor layer are provided on the second semiconductor layer and have a low electron affinity. A third semiconductor layer having a large sum of the second group and a second conductivity type impurity, and a second source, drain and gate electrodes provided on the upper side of the third semiconductor layer, wherein the second semiconductor layer is Forming a quantum well of potential,
The quantum well separates and stores first and second conductivity type carriers, and the first and second conductivity type carriers form channels of the first and second conductivity type channel field effect transistors, respectively. Semiconductor device. 2. The semiconductor device according to claim 1, wherein the first conductivity type is an n conductivity type and the second conductivity type is a p conductivity type. 3. The semiconductor device according to claim 1, wherein the first conductivity type is p conductivity type and the second conductivity type is n conductivity type. 4. The semiconductor device according to claim 1, wherein the first semiconductor layer and the third semiconductor layer are formed of the same material. 5. A second semiconductor layer is provided on the first semiconductor layer via a first spacer layer, and a third semiconductor layer is provided on the second semiconductor layer via a second spacer layer. The semiconductor device according to claim 1.