JPH0654834B2 - Method for manufacturing multilayer wiring board - Google Patents
Method for manufacturing multilayer wiring boardInfo
- Publication number
- JPH0654834B2 JPH0654834B2 JP1128337A JP12833789A JPH0654834B2 JP H0654834 B2 JPH0654834 B2 JP H0654834B2 JP 1128337 A JP1128337 A JP 1128337A JP 12833789 A JP12833789 A JP 12833789A JP H0654834 B2 JPH0654834 B2 JP H0654834B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- circuit
- cuo
- multilayer wiring
- copper
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 238000000034 method Methods 0.000 title claims description 14
- 239000000463 material Substances 0.000 claims description 28
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 claims description 27
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 22
- 239000010949 copper Substances 0.000 claims description 21
- 239000005751 Copper oxide Substances 0.000 claims description 14
- 229910052802 copper Inorganic materials 0.000 claims description 14
- 229910000431 copper oxide Inorganic materials 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 239000000956 alloy Substances 0.000 claims description 10
- 229910045601 alloy Inorganic materials 0.000 claims description 10
- 239000008151 electrolyte solution Substances 0.000 claims description 9
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 51
- 125000001475 halogen functional group Chemical group 0.000 description 16
- 239000011889 copper foil Substances 0.000 description 9
- 239000011229 interlayer Substances 0.000 description 8
- 239000004744 fabric Substances 0.000 description 7
- 230000003647 oxidation Effects 0.000 description 7
- 238000007254 oxidation reaction Methods 0.000 description 7
- 239000011701 zinc Substances 0.000 description 7
- KRKNYBCHXYNGOX-UHFFFAOYSA-N citric acid Chemical compound OC(=O)CC(O)(C(O)=O)CC(O)=O KRKNYBCHXYNGOX-UHFFFAOYSA-N 0.000 description 6
- 239000000853 adhesive Substances 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- 239000003822 epoxy resin Substances 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- 239000007864 aqueous solution Substances 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 239000003792 electrolyte Substances 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- PPBRXRYQALVLMV-UHFFFAOYSA-N Styrene Chemical compound C=CC1=CC=CC=C1 PPBRXRYQALVLMV-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- BDAGIHXWWSANSR-UHFFFAOYSA-N methanoic acid Natural products OC=O BDAGIHXWWSANSR-UHFFFAOYSA-N 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- LNOPIUAQISRISI-UHFFFAOYSA-N n'-hydroxy-2-propan-2-ylsulfonylethanimidamide Chemical compound CC(C)S(=O)(=O)CC(N)=NO LNOPIUAQISRISI-UHFFFAOYSA-N 0.000 description 2
- ACVYVLVWPXVTIT-UHFFFAOYSA-N phosphinic acid Chemical compound O[PH2]=O ACVYVLVWPXVTIT-UHFFFAOYSA-N 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000007788 roughening Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 229910052725 zinc Inorganic materials 0.000 description 2
- OSWFIVFLDKOXQC-UHFFFAOYSA-N 4-(3-methoxyphenyl)aniline Chemical compound COC1=CC=CC(C=2C=CC(N)=CC=2)=C1 OSWFIVFLDKOXQC-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- -1 aminoborane compound Chemical class 0.000 description 1
- 239000004760 aramid Substances 0.000 description 1
- 229920003235 aromatic polyamide Polymers 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 235000019253 formic acid Nutrition 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000004745 nonwoven fabric Substances 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000011734 sodium Substances 0.000 description 1
- UKLNMMHNWFDKNT-UHFFFAOYSA-M sodium chlorite Chemical compound [Na+].[O-]Cl=O UKLNMMHNWFDKNT-UHFFFAOYSA-M 0.000 description 1
- 229960002218 sodium chlorite Drugs 0.000 description 1
- SUKJFIGYRHOWBL-UHFFFAOYSA-N sodium hypochlorite Chemical compound [Na+].Cl[O-] SUKJFIGYRHOWBL-UHFFFAOYSA-N 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 229920006305 unsaturated polyester Polymers 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Wiring (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） この発明は、多層配線基板の製造方法に関するものであ
る。さらに詳しくは、この発明は、内層材とプリプレグ
層との接着力を向上させ、ファイン回路を有する配線板
の信頼性を向上させることのできる、新しい多層配線基
板の製造方法に関するものである。The present invention relates to a method for manufacturing a multilayer wiring board. More specifically, the present invention relates to a method for manufacturing a new multilayer wiring board, which can improve the adhesive force between an inner layer material and a prepreg layer and improve the reliability of a wiring board having a fine circuit.
（従来の技術） 電気・電子機器、電子計算機、通信機器等に用いられて
いるプリント配線板については、近年の高密度実装の要
望の高まりとともに多層配線板への需要が増大し、これ
にともなって多層配線板の信頼性向上のための種々の工
夫がなされてきている。(Prior Art) Regarding printed wiring boards used in electric / electronic devices, electronic computers, communication devices, etc., the demand for multilayer wiring boards has increased along with the increasing demand for high-density mounting in recent years. Various efforts have been made to improve the reliability of multilayer wiring boards.
従来、このような多層構造を有するプリント配線板につ
いては、たとえば第３図に示したように、片面又は両面
銅張積層板の銅箔面に回路（ア）を形成したものを内層
材（イ）とし、この内層材（イ）の表面をサンダー、ベ
ルトサンダー等によって物理的に粗化し、あるいはこの
粗化後にアルカリ性亜塩素酸ナトリウム水溶液等で処理
して銅箔回路（ア）の表面に黒色酸化銅皮膜を形成する
黒化処理してから、プリプレグ層（ウ）を介して片面銅
張積層板や銅箔（エ）を外層材として配設一体化成形す
ることにより製造してきている。Conventionally, as for a printed wiring board having such a multilayer structure, for example, as shown in FIG. 3, an inner layer material (a) having a circuit (a) formed on a copper foil surface of a single-sided or double-sided copper clad laminate is used. ), The surface of the inner layer material (a) is physically roughened by a sander, a belt sander, or the like, or after this roughening, the surface of the copper foil circuit (a) is blackened by treatment with an alkaline sodium chlorite aqueous solution or the like. After a blackening treatment for forming a copper oxide film, a single-sided copper-clad laminate or a copper foil (d) is disposed and integrally molded as an outer layer material via a prepreg layer (c).
（発明が解決しようとする課題） このような従来の製造方法は、これまでのパターン密度
の回路においては信頼性を一応は確保できるものの、近
年の回路密度が著しく増大したファインパターン回路に
おいては、内層材（イ）とプリプレグ層（ウ）との間の
層間接着力を確保することが難しくなってきている。こ
れは、プリント配線板における内層材（イ）表面の従来
の回路面積に比べて、ファインパターン回路の場合には
その回路（ア）の占める面積が著しく大きくなっている
ためで、内層材（イ）の樹脂層とプリプレグ層（ウ）と
の接触面積は減少しており、たとえば銅箔回路（ア）を
従来のように表面処理したとしてもこの接触面での層間
接着性の低下は避けられない。(Problems to be Solved by the Invention) Such a conventional manufacturing method can temporarily secure reliability in a circuit having a pattern density up to now, but in a fine pattern circuit in which the circuit density has increased remarkably in recent years, It has become difficult to secure an interlayer adhesive force between the inner layer material (a) and the prepreg layer (c). This is because in the case of a fine pattern circuit, the area occupied by the circuit (a) is significantly larger than the conventional circuit area on the surface of the inner layer material (a) in the printed wiring board. ) The contact area between the resin layer and the prepreg layer (c) is reduced, and even if the copper foil circuit (a) is surface-treated as in the conventional case, a decrease in interlayer adhesion at this contact surface can be avoided. Absent.
このため、従来の製造方法によっては層間接着力が低下
し、ハローの発生と配線板の信頼性の低下が避けられな
かった。For this reason, the interlayer adhesive force is lowered by the conventional manufacturing method, and the occurrence of halo and the reduction in reliability of the wiring board cannot be avoided.
このような課題を解決するものとして、内層材（イ）の
表面を黒化処理した後に還元する方法が提案されている
が、この方法は、特殊なアミノボラン化合物を使用する
ことが必要であり、その効果も必ずしも満足できるもの
ではなかった。As a solution to such a problem, a method of reducing the surface of the inner layer material (a) after blackening is proposed, but this method requires the use of a special aminoborane compound, The effect was not always satisfactory.
この発明は、以上の通りの事情に鑑みてなされたもので
あり、従来の多層配線板の製造方法の欠点を改善し、フ
ァインパターン回路、すなわち内層材表面の回路面積が
大きくなっても層間接着性が良好であって、耐ハロー性
に優れ、信頼性も向上した多層配線基板を製造すること
のできる新しい製造方法を提供することを目的としてい
る。The present invention has been made in view of the circumstances as described above, improves the drawbacks of the conventional method for manufacturing a multilayer wiring board, and enables fine pattern circuits, that is, interlayer adhesion even when the circuit area of the inner layer material surface is large. It is an object of the present invention to provide a new manufacturing method capable of manufacturing a multilayer wiring board having good properties, excellent halo resistance, and improved reliability.
（課題を解決するための手段） この発明は、上記の課題を解決するものとして、内層回
路板の銅回路表面を酸化処理して形成した銅酸化物層
を、ＣｕＯよりも酸化還元電位の低い金属又はその合金
からなる還元処理用ラック、もしくはその金属又は合金
によって表面メッキした還元処理用ラックと、ＣｕＯ溶
解性の電解質溶液中において接触させて粗面化し、次い
でプリプレグを介在させて外層材を積層一体化成形する
ことを特徴とする多層配線基板の製造方法を提供する。(Means for Solving the Problems) In order to solve the above problems, the present invention provides a copper oxide layer formed by oxidizing a copper circuit surface of an inner layer circuit board with a redox potential lower than that of CuO. A reduction treatment rack made of a metal or an alloy thereof, or a reduction treatment rack surface-plated with the metal or an alloy thereof is brought into contact with a CuO-soluble electrolyte solution for roughening, and then an outer layer material is interposed with a prepreg interposed. Provided is a method for manufacturing a multilayer wiring board, which is characterized in that the layers are integrally molded.
この発明においてＣｕＯよりも酸化還元電位の低い金属
としては、ＣｕＯの0.6Ｖよりも低い、たとえばＺｎ
（亜鉛），Ａｌ（アルミニウム），Ｓｎ（錫）などの金
属、もしくはハンダ等のそれらの合金類を用いることが
でき、この発明では、これらの金属又は合金から作製し
た、もしくは金属又は合金によって表面メッキした還元
処理用ラックを使用する。そして、処理浴としてのＣｕ
Ｏ溶解性の電解質溶液中において、その還元処理用ラッ
クと、内層材の銅回路表面に酸化処理により形成したＣ
ｕＯ，Ｃｕ２Ｏの銅酸化物層とを少なくとも一部分で接
触させる。このようなＣｕＯ溶解性の電解質溶液中での
還元処理用ラックと銅酸化物層との接触により、銅酸化
物層はより酸化レベルの低い状態となり、内層材表面の
銅回路表面は粗面化される。プリプレグとの接着力が一
段と向上する。In the present invention, the metal having a lower redox potential than CuO is lower than 0.6V of CuO, for example, Zn.
A metal such as (zinc), Al (aluminum), Sn (tin), or an alloy thereof such as solder can be used. In the present invention, a surface made of or made of these metals or alloys can be used. Use plated reduction racks. And Cu as a treatment bath
In the O-soluble electrolyte solution, C formed by oxidation treatment on the reduction treatment rack and the copper circuit surface of the inner layer material.
The copper oxide layer of uO, Cu 2 O is contacted at least partially. The contact between the reduction treatment rack and the copper oxide layer in the CuO-soluble electrolyte solution causes the copper oxide layer to have a lower oxidation level, and the copper circuit surface on the surface of the inner layer material to be roughened. To be done. The adhesive strength with the prepreg is further improved.
処理浴は、上記の通りのＣｕＯ溶解性の電解質溶液と
し、単独でＣｕＯを溶解することのできるものとする。
このような電解質としては、たとえばスルファミン酸、
次亜リン酸、ギ酸、クエン酸などを使用することができ
る。また、電解質溶液は、水系、あるいは溶媒系との混
合系等のいずれであってもよい。The treatment bath is a CuO-soluble electrolyte solution as described above, and is capable of dissolving CuO by itself.
Examples of such an electrolyte include sulfamic acid,
Hypophosphorous acid, formic acid, citric acid and the like can be used. The electrolyte solution may be either an aqueous system or a mixed system with a solvent system.
添付した図面の第１図に沿って、この発明の多層配線基
板の製造方法について説明する。A method for manufacturing a multilayer wiring board according to the present invention will be described with reference to FIG. 1 of the accompanying drawings.
（ａ）プリプレグ及び銅箔等から成形された片面又は両
面に銅回路（１）を有する内層材（２）の銅回路（１）
表面を酸化処理し、ＣｕＯ，Ｃｕ２Ｏの銅酸化物層
（３）を形成する。(A) Copper circuit (1) of inner layer material (2) having copper circuit (1) on one or both sides molded from prepreg and copper foil
The surface is oxidized to form a copper oxide layer (3) of CuO, Cu 2 O.
この時の内層材（２）を形成するプリプレグには特にそ
の種類に限定はなく、ガラスクロス、紙等の基材にフェ
ノール、エポキシ、ポリイミド、不飽和ポリエステル等
の樹脂を含浸させたものを適宜使用することができる。The type of prepreg for forming the inner layer material (2) at this time is not particularly limited, and a material such as a glass cloth or paper substrate impregnated with a resin such as phenol, epoxy, polyimide or unsaturated polyester is appropriately used. Can be used.
これらのプリプレグは、たとえば１〜３枚の適宜な枚数
を用いることができる。For these prepregs, for example, an appropriate number of 1 to 3 can be used.
銅回路（１）の酸化は、これまでに知られているたとえ
ば黒化処理等の方法によって行うことができる。この時
の処理に応じて、ＣｕＯ又はＣｕ２Ｏもしくはその共存
の状態の銅酸化物層（３）が形成される。Oxidation of the copper circuit (1) can be performed by a conventionally known method such as blackening treatment. Depending on the treatment at this time, CuO or Cu 2 O or the copper oxide layer (3) in the coexisting state thereof is formed.
次いで、この銅酸化物層（３）を、ＣｕＯよりも酸化還
元電位の低い、たとえばＺｎ，Ａｌ，Ｓｎなどの金属、
もしくはそれらの合金類から作製した、あるいはその金
属又は合金によって表面メッキした還元処理用ラック
と、ＣｕＯ溶解性電解質溶液中で接触させ、銅酸化物層
（３）の酸化レベルをより低い状態とする。Next, the copper oxide layer (3) is provided with a metal having a redox potential lower than that of CuO, such as Zn, Al, or Sn.
Alternatively, a reduction rack made of an alloy thereof or surface-plated with the metal or alloy thereof is brought into contact with a CuO-soluble electrolyte solution to lower the oxidation level of the copper oxide layer (3). .
より具体的には、たとえば第２図に示したように、たと
えばＺｎ製等の還元処理用の平板ラック（１０）に、止
め具（１１）を介して銅酸化物層（３）が表面に形成さ
れた内層材（２）を装着する。この際に、平板ラック
（１０）と銅酸化物層（３）の一部とを必ず接触させ
る。スペース（１）を設ける場合には、0.1〜５mm程度
とするのが好ましい。More specifically, as shown in FIG. 2, for example, a flat plate rack (10) for reduction treatment made of, for example, Zn is provided with a copper oxide layer (3) on the surface via a stopper (11). The formed inner layer material (2) is attached. At this time, the flat plate rack (10) and a part of the copper oxide layer (3) are always brought into contact with each other. When the space (1) is provided, it is preferably about 0.1 to 5 mm.
このようなラックとの電解質溶液中での接触処理によ
り、銅酸化物層（３）の酸化レベルはより低いものとな
り、その表面は粗面化される。なお、処理時間、温度等
は、採用する処理系に応じて適宜とすればよい。By such contact treatment with the rack in the electrolyte solution, the oxidation level of the copper oxide layer (3) becomes lower and the surface thereof is roughened. The processing time, temperature, etc. may be appropriately set depending on the processing system used.
（ｂ）次いで、得られた表面に、所要枚数のプリプレグ
（４）と外層材（５）とを配設して積層一体化する。(B) Next, the required number of prepregs (4) and the outer layer material (5) are arranged on the obtained surface to be laminated and integrated.
プリプレグ（４）は、たとえば１〜３枚程度配設するの
が好ましいが、特にこれに限定されることはない。プリ
プレグ（４）としては、内層材（２）の場合と同様にガ
ラスクロス、アラミドクロス、ポリエステルクロスなど
のクロスやマット状物、あるいは不織布や紙などの基材
にエポキシ樹脂、フェノール樹脂、ポリイミド樹脂など
の樹脂を含浸させたものを用いることができる。中でも
ガラスクロスエポキシ樹脂プリプレグは好適なものとし
て例示される。また、外層材（５）としては、銅箔や、
あるいはプリプレグと銅箔とから片面銅張積層体とした
ものなどを用いることができる。The prepreg (4) is preferably arranged, for example, about 1 to 3, but not limited to this. As the prepreg (4), similar to the case of the inner layer material (2), cloth or mat-like material such as glass cloth, aramid cloth, polyester cloth, or epoxy resin, phenol resin, polyimide resin as a base material such as nonwoven fabric or paper. Those impregnated with a resin such as can be used. Among them, the glass cloth epoxy resin prepreg is exemplified as a suitable one. Further, as the outer layer material (5), copper foil,
Alternatively, a one-sided copper clad laminate made of prepreg and copper foil can be used.
積層一体化成形は、多段プレス、スチロール、ダブルベ
ルト、無圧連続加熱等の従来公知の方法や条件に沿って
適宜に実施することができる。この成形によって一体化
した積層板の最外層銅箔に回路形成することにより多層
回路板が製造される。The laminated integral molding can be appropriately carried out according to conventionally known methods and conditions such as multi-stage pressing, styrene, double belt, and pressureless continuous heating. A multilayer circuit board is manufactured by forming a circuit on the outermost copper foil of the laminated board integrated by this molding.
もちろん、以上の製造上の条件等の細部については、公
知のものを含めて様々な態様が可能であることは言うま
でもない。Needless to say, the details of the above manufacturing conditions and the like can be variously modified, including known ones.
（作用） この発明においては、内層材の銅回路表面の酸化処理
と、ＣｕＯよりも酸化還元電位の低い金属又はその合金
から作製した、もしくはその金属又は合金によって表面
んメッキした還元処理用のとの電解質溶液中での接触に
よる酸化レベルの低次化処理とにより銅回路表面を粗化
するため、内層材とプリプレグ層との層間接着力が大き
く向上し、優れた耐ハロー性が実現する。(Function) In the present invention, for the oxidation treatment of the copper circuit surface of the inner layer material and the reduction treatment made of a metal or its alloy having a lower redox potential than CuO, or surface-plated with the metal or alloy. Since the copper circuit surface is roughened by lowering the oxidation level by contacting in an electrolyte solution, the interlayer adhesion between the inner layer material and the prepreg layer is greatly improved and excellent halo resistance is realized.
以下、実施例を示し、さらに詳しくこの発明の多層板の
製造方法について説明する。Examples will be shown below to describe the method for producing a multilayer board of the present invention in more detail.
（実施例） 実施例１ 厚さ１mmの両面銅張ガラスエポキシ樹脂積層板の両面に
回路形成し、これを内層材とした。(Example) Example 1 A circuit was formed on both sides of a double-sided copper-clad glass epoxy resin laminate having a thickness of 1 mm, and this was used as an inner layer material.
水洗後に、ＮａＣｌＯ４，ＮａＯＨ及びＮａ２ＰＯ４・
２Ｈ２Ｏの水溶液で処理して、回路表面にＣｕＯ層を形
成した。After washing with water, NaClO 4 , NaOH and Na 2 PO 4
It was treated with an aqueous solution of 2H 2 O to form a CuO layer on the circuit surface.
その後、内層材を第２図に例示した還元処理用ラック
（Ｚｎメッキ）に装着し、スルファミン酸水溶液（２０
ｇ／）中に３分間浸漬して、ＣｕＯ層をＣｕ，Ｃｕ２
Ｏに還元した。その後、引き上げて水洗した。Then, the inner layer material was mounted on the reduction treatment rack (Zn plating) illustrated in FIG. 2, and the sulfamic acid aqueous solution (20
g /) for 3 minutes to form a CuO layer containing Cu, Cu 2
Reduced to O. Then, it was pulled up and washed with water.
乾燥後、厚さ0.1mmのガラスクロスエポキシ樹脂プリプ
レグを内層材の上下両面に各々２枚ずつ配設し、さらに
最外層に厚さ0.035mmの銅箔を配設した。After drying, two 0.1 mm thick glass cloth epoxy resin prepregs were provided on each of the upper and lower surfaces of the inner layer material, and a 0.035 mm thick copper foil was provided as the outermost layer.
この積層体を４０kg/cm2の圧力、１６５℃の温度で６０
分間積層成形し、４層回路プリント配線基板を得た。This laminated body is subjected to 60 kg at a pressure of 40 kg / cm 2 and a temperature of 165 ° C.
The laminate was molded for a minute to obtain a 4-layer circuit printed wiring board.
この配線板について層間接着性と耐ハロー性を評価した
ところ、表１に示した結果を得た。後述の比較例との対
比から、層間接着力が向上し、耐ハロー性は著しく改善
されていることが確認された。When the interlayer adhesion and the halo resistance of this wiring board were evaluated, the results shown in Table 1 were obtained. From the comparison with Comparative Examples described later, it was confirmed that the interlayer adhesive force was improved and the halo resistance was remarkably improved.
なお、耐ハロー性については、１：１ＨＣｌ溶液３０分
浸漬により評価した。The halo resistance was evaluated by immersion in a 1: 1 HCl solution for 30 minutes.
実施例２ 回路表面にＣｕ２Ｏ層を形成した他は、実施例１と同様
にして配線板を製造し、耐ハロー性を評価した。その結
果を表１に示した。Example 2 A wiring board was manufactured in the same manner as in Example 1 except that a Cu 2 O layer was formed on the circuit surface, and the halo resistance was evaluated. The results are shown in Table 1.
優れた耐ハロー性が得られた。Excellent halo resistance was obtained.
実施例３〜４ ＺｎメッキのラックからＺｎ製のラックに代え、実施例
１及び実施例２と同様にして配線板を製造し、耐ハロー
性について評価した。Examples 3 to 4 Wiring boards were manufactured in the same manner as in Example 1 and Example 2 by replacing the Zn plated rack with a Zn rack, and evaluated for halo resistance.
いずれの場合も耐ハロー性は良好であった。In each case, the halo resistance was good.
実施例５ 電解質に次亜リン酸を用い、実施例１と同様にして配線
板を製造した。Example 5 A wiring board was produced in the same manner as in Example 1 except that hypophosphorous acid was used as the electrolyte.
得られた配線板について耐ハロー性を評価したところ、
同様に良好であった。When the halo resistance of the obtained wiring board was evaluated,
Similarly good.
実施例６ ＣｕＯをＣｕ２Ｏとして実施例５に従って配線板を製造
し、耐ハロー性を評価した。その結果は良好なものであ
った。Example 6 A wiring board was manufactured according to Example 5 using CuO as Cu 2 O, and the halo resistance was evaluated. The results were good.
実施例７〜８ Ａｌ製のラックを用い、実施例１と同様にして多層配線
基板を製造し、物性を評価した。Examples 7 to 8 A multilayer wiring board was manufactured in the same manner as in Example 1 using an Al rack, and the physical properties were evaluated.
また、電解質をクエン酸に代えて同様に製造し、評価し
た。Further, the electrolyte was replaced with citric acid, and the same production was performed and evaluated.
いずれの場合も耐ハロー性は良好であった。In each case, the halo resistance was good.
比較例１ ＣｕＯ層を形成し、そのままの状態で多層配線基板を製
造した。耐ハロー性を評価したところ、実施例に比べて
はるかに劣っていた。Comparative Example 1 A CuO layer was formed, and a multilayer wiring board was manufactured as it was. When the halo resistance was evaluated, it was far inferior to the examples.
比較例２ Ｃｕ２Ｏ層を形成し、そのままの状態で多層板を製造し
た。耐ハロー性は劣っていた。Comparative Example 2 A Cu 2 O layer was formed, and a multilayer board was manufactured as it was. The halo resistance was inferior.
（発明の効果） この発明の多層配線基板の製造方法により、以上詳しく
説明した通り、層間接着性及及び耐ハロー性を大きく向
上させた多層配線基板が実現される。 (Effect of the Invention) As described in detail above, the method for manufacturing a multilayer wiring board according to the present invention realizes a multilayer wiring board with greatly improved interlayer adhesion and halo resistance.
ファインパターン回路を有する多層配線基板の信頼性を
向上させることができる。It is possible to improve the reliability of a multilayer wiring board having a fine pattern circuit.
【図面の簡単な説明】 第１図は、この発明の多層配線基板の製造方法の製造工
程を例示した工程断面図である。第２図は、還元処理用
ラックの一例を示した斜視図である。 第３図は、従来の製造方法を示した工程断面図である。 １……銅回路 ２……内層材 ３……銅酸化物層 ４……プリプレグ ５……外層材 １０……平板ラック １１……止め具BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a process sectional view illustrating a manufacturing process of a method for manufacturing a multilayer wiring board according to the present invention. FIG. 2 is a perspective view showing an example of a reduction treatment rack. FIG. 3 is a process sectional view showing a conventional manufacturing method. 1 ... Copper circuit 2 ... Inner layer material 3 ... Copper oxide layer 4 ... Prepreg 5 ... Outer layer material 10 ... Flat rack 11 ... Stopper
フロントページの続き (72)発明者 赤松 資幸 大阪府門真市大字門真1048番地 松下電工 株式会社内 (56)参考文献 特開 昭52−71348（ＪＰ，Ａ) 特開 昭60−143693（ＪＰ，Ａ)Front page continuation (72) Inventor Yoshiyuki Akamatsu 1048 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Works, Ltd. (56) References JP-A-52-71348 (JP, A) JP-A-60-143693 (JP, A)
Claims (1)
成した銅酸化物層を、ＣｕＯよりも酸化還元電位の低い
金属又はその合金からなる還元処理用ラック、もしくは
その金属又は合金によって表面メッキした還元処理用ラ
ックと、ＣｕＯ溶解性の電解質溶液中において接触させ
て粗面化し、次いでプリプレグを介在させて外層材を積
層一体化成形することを特徴とする多層配線基板の製造
方法。1. A copper oxide layer formed by oxidizing the surface of a copper circuit of an inner layer circuit board is treated with a reduction treatment rack made of a metal or an alloy thereof having a lower redox potential than CuO, or a metal or alloy thereof. A method for manufacturing a multilayer wiring board, comprising: bringing a surface-plated rack for reduction treatment into contact with a CuO-soluble electrolyte solution to roughen the surface, and then integrally laminating an outer layer material with a prepreg interposed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1128337A JPH0654834B2 (en) | 1989-05-22 | 1989-05-22 | Method for manufacturing multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1128337A JPH0654834B2 (en) | 1989-05-22 | 1989-05-22 | Method for manufacturing multilayer wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02306697A JPH02306697A (en) | 1990-12-20 |
| JPH0654834B2 true JPH0654834B2 (en) | 1994-07-20 |
Family
ID=14982302
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1128337A Expired - Lifetime JPH0654834B2 (en) | 1989-05-22 | 1989-05-22 | Method for manufacturing multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0654834B2 (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS586800B2 (en) * | 1975-12-12 | 1983-02-07 | ニホンコウギヨウ カブシキガイシヤ | Insatsu Kairo Youdou Hakuo Hiyou Menshiyo Risuru Hohou |
| JPS60143693A (en) * | 1983-12-29 | 1985-07-29 | 株式会社日立製作所 | Method of forming multilayer circuit board |
-
1989
- 1989-05-22 JP JP1128337A patent/JPH0654834B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02306697A (en) | 1990-12-20 |
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