JPH065599B2 - Semiconductor memory device - Google Patents

Description

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device including a random access memory.

[Conventional technology]

A conventional random access memory device (hereinafter referred to as RAM) has a wide range of applications because data can be read and written at any time at any address.

However, in the conventional RAM, the data stored in the memory cell cannot be directly shifted inside the RAM. Therefore, to shift the data stored in the memory cell to the address before or after the address where the data is stored, first set the address where the data is stored and The object was achieved by performing a series of operations for reading the stored data to the outside once, then subtracting or adding 1 to the address and writing the data again for the required number of times.

[Problems to be solved by the invention]

In the above-described conventional semiconductor memory device, newly input data must be written in the RAM and all the data stored in the RAM must be shifted one stage, as in the case where the signal processor constitutes the digital filter. When it is necessary, not only the shift operation requires several steps of signal processor instructions, but also the shift operation takes time proportionally as the number of stages increases. There is a problem in that it may not be possible to complete all the processing, which necessitates limiting the characteristics that can be realized as a digital filter.

An object of the present invention is to provide a semiconductor memory device that can directly shift data between memory cells at adjacent addresses without reading the data stored in the memory cells to the outside of the RAM.

[Means for solving problems]

A semiconductor memory device of the present invention includes a first transistor having a gate connected to a word line and a source connected to one data line, and a second transistor having a gate connected to the word line and a drain connected to the other data line. A transistor, a first inverter having an input terminal connected to the drain of the first transistor and an output terminal connected to the source of the second transistor, and a source connected to the input terminal of the first inverter A third transistor whose gate is connected to the control line of
A fourth transistor having a drain connected to the output terminal of the first inverter and a gate connected to the first control line; and a drain of the third transistor having an input terminal connected to the source of the fourth transistor A second inverter having an output terminal connected to the second inverter, and a fifth inverter having a drain connected to the output terminal of the second inverter and a gate connected to the second control line.
And a source connected to the input terminal of the second inverter and a gate connected to the second control line.
The i-th (i is a natural number) memory cell and the (i + 1) -th memory cell having the same configuration as the i-th memory cell.
The source of the fifth transistor of the th memory cell is connected to the input terminal of the first inverter of the (i + 1) th memory cell, and the drain of the sixth transistor of the i th memory cell is connected to the drain of the sixth transistor. It is configured to include connection to the output terminal of the first inverter of the (i + 1) th memory cell.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a semiconductor memory device according to an embodiment of the present invention.

As shown in FIG. 1, the semiconductor memory device of the present embodiment is an N-channel enhancement MOS type memory device in which the gate is connected to the i-th (i is a natural number) word line Wi and the source is connected to the data line 9. 1 transistor 1 and word line W
A second transistor 2 having a gate connected to i and a drain connected to the data line 10, and a CMOS type in which an input end is connected to the drain of the first transistor 1 and an output end is connected to the source of the second transistor 2. A first inverter 7,
The third transistor 3 whose source is connected to the input terminal of the first inverter 7 and whose gate is connected to the _first control line C ₁ i
And a fourth transistor 4 whose drain is connected to the output terminal of the inverter 7 and whose gate is connected to the _first control line C ₁ i.
And an input end connected to the source of the fourth transistor 4 and an output end connected to the drain of the third transistor 3.
Of the second inverter 8, the drain is connected to the output terminal of the second inverter 8 and the gate is connected to the _second control line C ₂ i, and the source is connected to the input terminal of the second inverter 8. The i-th memory cell Mi having the sixth transistor 6 whose gate is connected to the _second control line C ₂ i and the (i + 1) th memory cell having the same configuration as the i-th memory cell Including M (i + 1), the source of the fifth transistor 5 of the i-th memory cell Mi is connected to the input terminal of the first inverter 7 of the (i + 1) -th memory cell M (i + 1). Then, the drain of the sixth transistor 6 of the i-th memory cell Mi is connected to the output terminal of the first inverter 7 of the (i + 1) -th memory cell M (i + 1).

Next, the operation of the embodiment shown in FIG. 1 will be described.

FIG. 2 is a waveform diagram of signals for operating the embodiment of FIG.

When operating the semiconductor memory device of this embodiment as a RAM, the terminal 14 is set to a low level potential. By this setting, the first control lines C ₁ i, C ₁ (i + 1) connected to the output of the NAND circuit 11 are set to the high level potential,
Second control line C connected to the output of the AND circuit 12
₂ i, C ₂ (i + 1) is set to a low level potential. As a result, the third transistor 3 and the fourth transistor 4 become conductive, and the fifth transistor 5 and the sixth transistor 6 become non-conductive, so that the memory cells Mi and M (i + 1) are independent of each other. It becomes a memory cell, and word line Wi or W (i +
When 1) is selected, the memory cell Mi or M (i + 1) can write or read data through the data lines 10 and 11.

Further, in the operation of shifting the data stored in the memory cells to the memory cells of the adjacent addresses, all the word lines are deselected and the memory cells are cut off from the data lines, and the terminal 14 is set to the high level potential. Set,
At the same time, the signal φ ₁ shown in FIG. ₂ is applied to the terminal 16 and the signal φ ₂ is applied to the terminal 15. In section I, the first control line C
₁ i, C ₁ (i + 1) and the second control line C ₂ i, C ₂ (i + 1)
Are both set to a low level potential, and the third to sixth transistors 3 to 6 become non-conductive, so that the first inverter 7 and the second inverter 7
The inverters 8 are electrically separated from each other, but the data stored up to that point is held as the potential of the gate of each inverter. In the section II, the first control line C ₁ i, C ₁ (i + 1) is at the low level potential, and the second control line C 1
₂ i, C ₂ (i + 1) is set to a high level and the third and fourth
And the fifth and sixth transistors 5 and 6 are turned on, and the second inverter 8 included in the memory cell Mi and the first inverter included in the memory cell M (i + 1). And 7 form a memory cell temporarily, and the data held in the inverter 8 included in the memory cell Mi is shifted to the first inverter 7 included in the memory cell M (i + 1). . In the section III, as in the section I, the first inverter 7 and the second inverter 8 are electrically separated from each other, but the first inverter 7 included in the memory cell M (i + 1) has a memory. The data shifted from the inverter 8 included in the cell Mi is held. Section IV
Then, the first control line C ₁ i, C ₁ (i + 1) is set to a high level potential, and the second control line C ₂ i, C ₂ (i + 1) is set to a low level position. Therefore, the third and fourth transistors 3 and 4 are rendered conductive, and the fifth and sixth transistors 5 and 6 are rendered non-conductive, so that the memory cell is restored by the combination of the first inverter 7 and the second inverter 8. Memory cell M
The data stored in i is shifted to the memory cell M (i + 1).

In this way, the data stored in any memory cell can be shifted by one word.

〔The invention's effect〕

As described above, the present invention has a memory cell configuration including inverters that are alternately connected via the transistors connected to the control line, and the normal RA depending on the potential applied to the control line.
By providing the function of shifting the data stored in the memory cell to the memory cell of the adjacent address in addition to the configuration of M, the data stored in the RAM can be shifted at a time. Therefore, when configuring a digital filter with a signal processor,
Even if the number of stages to be shifted increases, the time required therefor is constant, and the function as a digital filter is not restricted.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG.
It is a wave form diagram of the signal for operating the Example of a figure. 1 to 6 ... N-channel enhancement MOS type transistor, 7, 8 ... CMOS type inverter, 9, 10 ... Data line, 11 ... NAND circuit, 12 ... AND circuit, 13
Inverter, Wi, W (i + 1) ... Word line, Mi, M (i +
1) ... Memory cell, C ₁ i, C ₁ (i + 1), C ₂ i, C ₂ (i +
1) ... control line.

Claims (1)

[Claims] 1. A first transistor having a gate connected to a word line and a source connected to one data line, and a second transistor having a gate connected to the word line and a drain connected to the other data line, A first inverter having an input terminal connected to the drain of the first transistor and an output terminal connected to the source of the second transistor; and a first control line having a source connected to the input terminal of the first inverter Input to a source of the fourth transistor, and a third transistor having a gate connected to the fourth transistor, a fourth transistor having a drain connected to the output terminal of the first inverter and a gate connected to the first control line A second inverter having an end connected to the drain of the third transistor and an output connected to the drain of the third transistor; and a drain connected to the output of the second inverter and connected to a second control line. The fifth transistor connected to the second inverter and the sixth transistor whose source is connected to the input terminal of the second inverter and whose gate is connected to the second control line, the i-th (i is a natural number) The memory cell and the (i +) th memory cell having the same configuration as the i-th memory cell
1) th memory cell, the source of the fifth transistor of the i-th memory cell is the (i + 1) th memory cell.
Connected to the input terminal of the first inverter of the th memory cell, and connecting the drain of the sixth transistor of the i-th memory cell to the output terminal of the first inverter of the (i + 1) th memory cell. A semiconductor memory device having the above structure.