JPH065694B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH065694B2 JPH065694B2 JP24000287A JP24000287A JPH065694B2 JP H065694 B2 JPH065694 B2 JP H065694B2 JP 24000287 A JP24000287 A JP 24000287A JP 24000287 A JP24000287 A JP 24000287A JP H065694 B2 JPH065694 B2 JP H065694B2
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- fuse
- film
- semiconductor device
- internal electronic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
- H10W20/493—Fuses, i.e. interconnections changeable from conductive to non-conductive
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/932—Plan-view shape, i.e. in top view
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Read Only Memory (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に多結晶シリコン・ヒュ
ーズ・メモリを含む半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a polycrystalline silicon fuse memory.
従来、多結晶シリコン・ヒューズ・メモリは回路特性の
製造バラツキの吸収または微調整用として利用される。Conventionally, a polycrystalline silicon fuse memory is used for absorbing or finely adjusting manufacturing variations in circuit characteristics.
第２図（ａ）および（ｂ）はそれぞれ多結晶シリコン・
ヒューズ・メモリを抵抗値のトリミング用に搭載した従
来半導体装置の部分平面図およびその多結晶シリコン・
ヒューズ・メモリの拡大断面図である。ここで、ｒは内
部回路抵抗素子、また、１０ａ〜１０ｃは多結晶シリコ
ン・ヒューズをそれぞれ示し、多結晶シリコン・ヒュー
ズ・メモリの何れか一つをパッド・スルーホール８から
の通電によって切断することにより、拡散端子Ｒ１〜Ｒ
２を任意の抵抗値に設定し得る。この多結晶シリコン・
ヒューズ・メモリは、第２図（ｂ）の拡大図が示すよう
に、通常、シリコン基板１のフィールド酸化膜２上に内
部回路抵抗素子ｒ（図示しない）と並べて形成される。
すなわち、Ｐ型シリコン基板１上にフィールド酸化膜２
をまず形成し、ついでその上にヒューズ・メモリ部とな
る多結晶シリコン・ヒューズ膜３を形成する。つぎに層
間絶縁膜４を成長させ、多結晶シリコン膜３の両端部に
コンタクト孔５をそれぞれ開孔した後、アルミ配線６を
形成し、更にカバー膜７を成長させ、パッド・スルーホ
ール８を開孔するという順序を踏む。以上の説明から明
らかなように、従来の多結晶シリコン・ヒューズ・メモ
リでは、多結晶シリコン・ヒューズ膜３の両端はコンタ
クト孔５を介して直接内部回路抵抗素子ｒとアルミ配線
６で接続され、必要に応じパッド・スルーホール８から
の電流で切断される。2 (a) and 2 (b) are polycrystalline silicon
A partial plan view of a conventional semiconductor device in which a fuse memory is mounted for trimming the resistance value and its polycrystalline silicon
It is an expanded sectional view of a fuse memory. Here, r is an internal circuit resistance element, and 10a to 10c are polycrystal silicon fuses, respectively, and any one of the polycrystal silicon fuse memories is cut by energization from the pad through hole 8. Therefore, the diffusion terminals R 1 to R
2 can be set to any resistance value. This polycrystalline silicon
As shown in the enlarged view of FIG. 2B, the fuse memory is usually formed on the field oxide film 2 of the silicon substrate 1 side by side with the internal circuit resistance element r (not shown).
That is, the field oxide film 2 is formed on the P-type silicon substrate 1.
Is first formed, and then a polycrystalline silicon fuse film 3 to be a fuse memory portion is formed thereon. Next, an interlayer insulating film 4 is grown, contact holes 5 are formed at both ends of the polycrystalline silicon film 3, aluminum wirings 6 are formed, a cover film 7 is further grown, and pad through holes 8 are formed. Follow the order of opening a hole. As is clear from the above description, in the conventional polycrystalline silicon fuse memory, both ends of the polycrystalline silicon fuse film 3 are directly connected to the internal circuit resistance element r through the contact holes 5 by the aluminum wiring 6, If necessary, it is cut by a current from the pad through hole 8.
しかしながら、従来構造の多結晶シリコン・ヒューズ・
メモリは、多結晶シリコン・ヒューズ膜３を切断した
際、第２図（ｂ）に矢印Ｙで示したようにヒューズ膜３
直上のカバー膜７内にクラックが生じたとき、このクラ
ックから浸入して来る水分によってアルミ配線６が腐食
され、この腐食が更にアルミ配線６に沿って進行し第２
図（ａ）に示すＸ部まで達すると、２つの抵抗端子Ｒ１
−Ｒ２間がオープンとなつてしまう欠点がある。このア
ルミ配線の腐食断線による内部回路のオープン現象はト
リミング抵抗回路に限らず全ての内部電子回路について
起こる。However, the conventional structure of polycrystalline silicon fuse
When the polycrystalline silicon fuse film 3 is cut, the memory has the fuse film 3 as shown by the arrow Y in FIG.
When a crack is generated in the cover film 7 immediately above, the aluminum wiring 6 is corroded by the water entering from the crack, and this corrosion further progresses along the aluminum wiring 6 and
When reaching the portion X shown in FIG. 3A, the two resistance terminals R 1
There is a drawback between -R 2 resulting in summer and open. The open phenomenon of the internal circuit due to the corrosion disconnection of the aluminum wiring occurs not only in the trimming resistor circuit but also in all internal electronic circuits.
本発明の目的は、上記の情況に鑑み、カバー膜に生じた
クラックからの水分浸入によって並列接続される内部電
子回路にオープン現象を生じることなき多結晶シリコン
・ヒューズ・メモリを備えた半導体装置を提供すること
である。In view of the above situation, an object of the present invention is to provide a semiconductor device provided with a polycrystalline silicon fuse memory that does not cause an open phenomenon in internal electronic circuits connected in parallel by moisture intrusion from cracks generated in a cover film. Is to provide.
本発明によれば、半導体装置は、半導体基板と、前記半
導体基板上に形成される内部電子回路と、前記内部電子
回路の両端に挿入される多結晶シリコン・ヒューズ・メ
モリとを含んで成り、前記多結晶シリコン・ヒューズ・
メモリは、前記半導体基板上に互いに離間し且つ周囲を
フィールド酸化膜で取囲まれ島状に対向配置される２つ
の高濃度拡散層と、前記２つの高濃度拡散層の離間領域
のフィールド酸化膜上にヒューズ部を含んで形成される
多結晶シリコン・ヒューズ膜と、前記２つの高濃度拡散
層のうちの一つをそれぞれ介し前記多結晶シリコン・ヒ
ューズ膜の端部を前記内部電子回路に至るアルイ配線の
端部とをそれぞれ互いに接続する２つの引出アルミ接続
とを備えて形成されることを含む。According to the present invention, a semiconductor device includes a semiconductor substrate, an internal electronic circuit formed on the semiconductor substrate, and a polycrystalline silicon fuse memory inserted at both ends of the internal electronic circuit, The polycrystalline silicon fuse
The memory includes two high-concentration diffusion layers that are spaced apart from each other on the semiconductor substrate and are surrounded by a field oxide film and are arranged to face each other in an island shape, and a field oxide film in a separation region between the two high-concentration diffusion layers. An end of the polycrystalline silicon fuse film reaches the internal electronic circuit through a polycrystalline silicon fuse film formed to include a fuse portion and one of the two high-concentration diffusion layers, respectively. And two lead aluminum connections that connect the ends of the Alui wiring to each other.
以下図面を参照して本発明を詳細に説明する。 Hereinafter, the present invention will be described in detail with reference to the drawings.
第１図（ａ）および（ｂ）はそれぞれ本発明の半導体装
置が搭載する多結晶シリコン・ヒューズ・メモリの一実
施例を示す模式的平面図およびそのＡ−Ａ′断面図であ
る。本実施例によれば、半導体装置は、Ｐ型シリコン基
板１と、この基板１上に形成されたフィールド酸化膜２
と、基板１上に互いに離間し且つ周囲をフィールド酸化
膜２で取囲まれ島状に対向配置された２つのｎ＋拡散膜
９と、２つのｎ＋拡散層９の離間領域のフィールド酸化
膜２上に形成されたヒューズ部３ａ含む多結晶シリコン
・ヒューズ膜３と、ｎ＋拡散層９を介し多結晶シリコン
・ヒューズ膜３の両端部から引出されるアルミ接続線６
ａと内部電子回路に至るアルミ配線６とをそれぞれ接続
するコンタクト孔５および１１とを含む。1 (a) and 1 (b) are a schematic plan view and an AA 'sectional view showing an embodiment of a polycrystalline silicon fuse memory mounted on a semiconductor device of the present invention, respectively. According to this embodiment, the semiconductor device has a P-type silicon substrate 1 and a field oxide film 2 formed on the substrate 1.
And two n + diffusion films 9 which are spaced apart from each other on the substrate 1 and are surrounded by the field oxide film 2 and are opposed to each other in an island shape, and the field oxide films in the separated regions of the two n + diffusion layers 9. 2 and the polycrystalline silicon fuse film 3 including the fuse portion 3a formed above the aluminum connection line 6 drawn from both ends of the polycrystalline silicon fuse film 3 through the n + diffusion layer 9.
It includes contact holes 5 and 11 for connecting a and aluminum wiring 6 reaching the internal electronic circuit, respectively.
本実施例によれば、ｎ＋拡散層９は配線層として機能
し、アルミ接続線６ａとアルミ配線６との間に介在し
て、多結晶シリコン・ヒューズ膜３が切断された際生じ
るアルミ接続線６ａの腐食断線がアルミ配線６にまで波
及するのを有効に阻止することができる。本実施例の多
結晶シリコン・ヒューズ・メモリの製造はつぎに説明す
る如くきわめて容易である。すなわち、Ｐ型シリコン基
板１上に互いに対向する２つのｎ＋拡散層９及びフィー
ルド酸化膜２をまず形成し、２つのｎ＋拡散層９で挟ま
れたフィールド酸化膜２上にヒューズ部３ａを含む多結
晶シリコン・ヒューズ膜３をパターニング形成する。次
に、層間絶縁膜４を成長させ、多結晶シリコン・ヒュー
ズ膜３およびｎ＋拡散層９のそれぞれの両端部にコンタ
クト孔５および１１をそれぞれ開孔する。ついでアルミ
接続線６ａおよびアルミ配線６を形成した後にカバー膜
７を成長させ、最後にアルミ配線６上にパッド・スルー
ホール８（図示しない）を開孔すれば完了する。According to the present embodiment, the n + diffusion layer 9 functions as a wiring layer and is interposed between the aluminum connection line 6a and the aluminum wiring 6 to form an aluminum connection which is generated when the polycrystalline silicon / fuse film 3 is cut. It is possible to effectively prevent the corrosion breakage of the wire 6a from reaching the aluminum wiring 6. The manufacture of the polycrystalline silicon fuse memory of this embodiment is extremely easy as described below. That is, the two n + diffusion layers 9 and the field oxide film 2 facing each other are first formed on the P-type silicon substrate 1, and the fuse portion 3a is formed on the field oxide film 2 sandwiched by the two n + diffusion layers 9. The polycrystalline silicon fuse film 3 containing the same is patterned and formed. Next, the interlayer insulating film 4 is grown, and contact holes 5 and 11 are opened at both ends of the polycrystalline silicon fuse film 3 and the n + diffusion layer 9, respectively. Then, after forming the aluminum connection line 6a and the aluminum wiring 6, the cover film 7 is grown, and finally, a pad through hole 8 (not shown) is formed on the aluminum wiring 6 to complete the process.
以上詳細に説明したように本発明によれば、多結晶シリ
コン・ヒューズ膜と内部電子回路に至るアルミ配線との
間に拡散層を介在させる多結晶シリコン・ヒューズ・メ
モリの内部においてアルミ配線を２つの部分に機械的に
分断したことによって、多結晶シリコン・ヒューズ・メ
モリを切断した際、カバー膜上に生じたクラックからの
浸入水分によって、ヒューズ・メモリ・内だけに止まら
ず主回路のアルミ配線までも腐食し消失させ主回路の全
機能を停止させるが如き従来の問題点を完全に解決し得
るので、半導体装置の信頼性向上に顕著なる効果を奏し
得る。As described above in detail, according to the present invention, the aluminum wiring is provided in the polycrystalline silicon fuse memory in which the diffusion layer is interposed between the polycrystalline silicon fuse film and the aluminum wiring reaching the internal electronic circuit. When the polycrystalline silicon fuse memory is cut by mechanically dividing it into two parts, the moisture entering from the cracks generated on the cover film does not stop inside the fuse memory Since the conventional problems such as even corrosion and disappearance to stop all the functions of the main circuit can be completely solved, the reliability of the semiconductor device can be remarkably improved.
第１図（ａ）および（ｂ）はそれぞれ本発明の半導体装
置が搭載する多結晶シリコン・ヒューズ・メモリの一実
施例を示す模式的平面図及びそのＡ−Ａ′断面図、第２
図（ａ）および（ｂ）はそれぞれ多結晶シリコン・ヒュ
ーズ・メモリを抵抗値のトリミング用に搭載した従来半
導体装置の部分平面図およびその多結晶シリコン・ヒュ
ーズ・メモリの拡大断面図である。 １…Ｐ型シリコン基板、２…フィールド酸化膜、３…多
結晶シリコン・ヒューズ膜、３ａ…ヒューズ部、４…層
間絶縁膜、５，１１…コンタクト孔、６…アルミ配線、
６ａ…引出アルミ接続線、７…カバー膜、８…パッド・
スルーホール、９…ｎ＋拡散層。1 (a) and 1 (b) are a schematic plan view showing an embodiment of a polycrystalline silicon fuse memory mounted in a semiconductor device of the present invention and a sectional view taken along the line AA ', respectively.
FIGS. 2A and 2B are a partial plan view of a conventional semiconductor device having a polycrystalline silicon fuse memory mounted for trimming a resistance value and an enlarged sectional view of the polycrystalline silicon fuse memory, respectively. DESCRIPTION OF SYMBOLS 1 ... P-type silicon substrate, 2 ... Field oxide film, 3 ... Polycrystalline silicon fuse film, 3a ... Fuse part, 4 ... Interlayer insulating film, 5, 11 ... Contact hole, 6 ... Aluminum wiring,
6a ... Lead-out aluminum connecting wire, 7 ... Cover film, 8 ... Pad
Through holes, 9 ... N + diffusion layer.
Claims (1)
れる内部電子回路と、前記内部電子回路の両端に挿入さ
れる多結晶シリコン・ヒューズ・メモリとを含んで成
り、前記多結晶シリコン・ヒューズ・メモリは、前記半
導体基板上に互いに離間し且つ周囲をフィールド酸化膜
で取囲まれ島状に対向配置される２つの高濃度拡散層
と、前記２つの高濃度拡散層の離間領域のフィールド酸
化膜上にヒューズ部を含んで形成される多結晶シリコン
・ヒューズ膜と、前記２つの高濃度拡散層のうちの一つ
をそれぞれ介し前記多結晶シリコン・ヒューズ膜の端部
と前記内部電子回路に至るアルミ配線の端部とをそれぞ
れ互いに接続する２つの引出アルミ接続線とを備えて形
成されることを特徴とする半導体装置。1. A semiconductor substrate, an internal electronic circuit formed on the semiconductor substrate, and a polycrystalline silicon fuse memory inserted at both ends of the internal electronic circuit. The fuse memory includes two high-concentration diffusion layers that are spaced apart from each other on the semiconductor substrate and are surrounded by a field oxide film and are arranged to face each other in an island shape, and a field of a separation region between the two high-concentration diffusion layers. A polycrystalline silicon fuse film formed to include a fuse portion on an oxide film, and an end portion of the polycrystalline silicon fuse film and the internal electronic circuit via one of the two high-concentration diffusion layers, respectively. The semiconductor device is formed by including two lead aluminum connecting wires that connect the ends of the aluminum wires to the above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24000287A JPH065694B2 (en) | 1987-09-24 | 1987-09-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24000287A JPH065694B2 (en) | 1987-09-24 | 1987-09-24 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6481341A JPS6481341A (en) | 1989-03-27 |
| JPH065694B2 true JPH065694B2 (en) | 1994-01-19 |
Family
ID=17053002
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24000287A Expired - Lifetime JPH065694B2 (en) | 1987-09-24 | 1987-09-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH065694B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP4450147A1 (en) | 2023-04-18 | 2024-10-23 | JONQUIL CONSULTING Inc. | Carbon dioxide-containing gas processing system and carbon dioxide-containing gas processing method |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5006604B2 (en) | 2006-09-08 | 2012-08-22 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
-
1987
- 1987-09-24 JP JP24000287A patent/JPH065694B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP4450147A1 (en) | 2023-04-18 | 2024-10-23 | JONQUIL CONSULTING Inc. | Carbon dioxide-containing gas processing system and carbon dioxide-containing gas processing method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6481341A (en) | 1989-03-27 |
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