JPH0656953B2 - Digital circuit - Google Patents

Description

The present invention relates to a digital circuit, and more specifically, to counter operation, serial input shift register operation, and parallel input / output shift register operation with a small number of circuit elements. The present invention relates to a configuration of a realized digital circuit.

(B) Conventional Technology When a digital circuit is operated as a counter or as a serial input / output or parallel input / output shift register as needed, the configuration of the circuit is complicated.

FIG. 5 is a block diagram of a digital circuit having such a function. In the figure, (1) is a toggle-type flip-flop circuit, which is connected in cascade to form an n-bit counter. J is a J input, which is controlled by the clock (CLK2) input to the preset enable input (PE) to initialize the count of each bit. The counting is performed in synchronization with the clock (CLK1) input to the T input. FIG. 6 (a) is a diagram showing the circuit configuration of the toggle flip-flop circuit (1).

(2) is a D-type flip-flop circuit, which is connected in cascade to form an n-bit shift register. P / S
The input is a control input for selecting the parallel mode or the serial mode. In the parallel mode, data input from the PD input is permitted, and in the serial mode, SD is input.
Allow data input from input. The register operates by the clock (CLK3).

PI _{o to} PIn are parallel data input to the counter side, PO _{o to} POn are parallel data output from the counter side, and ISEL is PI _o to PI input from the outside.
_n is a control signal for selecting _n or shift register output data, and OPE is a control signal for selecting serial data input to the register or serial data output from the register. FIG. 6 (b) is a diagram showing the circuit configuration of the D-type flip-flop circuit (2).

(C) Problems to be Solved by the Invention By the way, according to the circuit of the conventional example, since the counter circuit and the shift register circuit are simply gathered together, a large number of elements are required even when integrated into a circuit. However, there is a problem that the formation area becomes large.

The present invention was created in view of the above conventional problems, and an object of the present invention is to provide a digital circuit having both a counter function and a shift register function and a small number of constituent elements.

(D) Means for Solving the Problems The digital circuit of the present invention has a plurality of master-slave flip-flop circuits, and the output of the flip-flop circuit of the previous stage is connected to the clock input (CKT) of the next stage. Has been done. That is, they are connected in cascade.

Each flip-flop circuit has a first clock input (CKT) for toggle operation, a second clock input (CKD) for shift operation, a toggle operation control input (TGL), serial data input (SD), and serial data selection. It has a control input (ESD), a parallel data input (PD) and a parallel data selection control input (EPD). Further, when the toggle operation control input becomes active, each flip-flop circuit toggles to enter the counter mode,
When the serial data selection control input becomes active,
When each flip-flop circuit performs a shift operation and serial data input is selected to enter the shift register mode, when each parallel data selection control input is active, each flip-flop circuit performs a shift operation and parallel data is selected. It has a logic circuit for controlling the parallel load mode.

(E) Action When the toggle operation control input becomes active, the logic circuit of each stage feeds back each output of each flip-flop circuit to the data input of each flip-flop circuit. After that, when the first clock input (CKT) is input, each flip-flop circuit toggles to count the number of clocks.

When the serial data selection control input is activated, the logic circuit allows data to be input from the data input of the first stage flip-flop circuit. After that, when the second clock input (CKD) is input, the data of each flip-flop circuit is sequentially shifted in synchronization with the clock.

When the parallel data selection control input is activated, the logic circuit allows data to be input in parallel to each flip-flop circuit for initialization. After this,
By switching the mode, it is possible to operate as the counter mode or the shift register mode.

(F) Example Next, an example of the present invention will be described with reference to the drawings. FIG. 1 is a configuration block diagram of a digital circuit having a counter function and a shift register function according to an embodiment of the present invention. (3) is a master-slave type flip-flop circuit that forms the basic configuration. FIG. 2 shows a detailed equivalent circuit diagram of the flip-flop circuit (3). CKT is the first clock input for toggle operation. This CKT input receives the first clock signal (CLK1) at the first stage and is connected to the force at the previous stage after the second stage. TGL is a toggle operation control input for controlling the flip-flop circuit (3) to perform a toggle operation, and receives a counter mode control signal (CTMOD).

CKD represents the second clock input for shift register operation. The second clock signal (CLK2) is input in parallel to the CKD input of each flip-flop circuit.

ESD is a serial data selection control input, and receives the shift register mode control signal (SRMOD). SD
Is the serial data input and the first stage flip-flop
Serial data input / output (SDATA) is connected to SD of (3), and Q output of the flip-flop (3) of the previous stage is connected to SD of the flip-flops (3) of the second and subsequent stages. In the shift register mode, serial data is supplied to the serial data input SD of the first-stage flip-flop (3) in synchronization with the second clock signal (CLK2). EPD is a parallel data selection control input and receives a parallel load mode control signal (PLMOD).
PD is a parallel data input, and in the parallel load mode, the parallel data signals (PI _{o to} PIn) are input in parallel to each flip-flop circuit (3) in synchronization with the second clock signal (CLK2), Is initialized.

OPE is a serial output enable signal for controlling the input / output control buffer (4), and when this signal is active, data is sequentially serially input / output controlled from the Q output of the final stage flip-flop circuit (3). The data is output to the serial data input / output (SDATA) via the buffer (4) and is also supplied to the serial data input (SD) of the first stage flip-flop circuit (3). Also, PO _o ~ PO
_n is a parallel data output signal for outputting data in parallel from the Q output of each flip-flop (3).

As shown in FIG. 2, the flip-flop circuit (3) which is the basic configuration of the embodiment circuit of the present invention is a master-slave type flip-flop circuit including a master section (5) and a slave section (6). Yes, each control signal (TGL, ES
D, EPD), each data signal (SD, PD) and each clock signal (CKT, CKD) are appropriately activated according to the operation mode, and logic circuits (7), (8) are provided.

In the circuit shown in FIG. 1, the control of the operation mode is
The counter mode control signal (CTMOD), the shift register mode control signal (SRMOD) and the parallel load mode control signal (PLMOD) are used. The operation mode control of each flip-flop (3) is performed by each control signal (CT
MOD, SRMOD, PLMOD) are applied by the respective control inputs (TGL, ESD, EPD).
Toggle motion control input (TGL) is active, ie
When it becomes "1", the output of each flip-flop circuit (3) is fed back to each data input, and the clock is the first
The clock input (CKT1) is selected and the TFF configuration is realized (this state is hereinafter referred to as TFF mode). on the other hand,
When the toggle operation control input (TGL) becomes "0", the output feedback loop is cut off in the logic circuit (7), and the second clock input (CK
D) is selected, and the DFF configuration is obtained (hereinafter, this state is referred to as the DFF mode). Where the flip-flop circuit
In the mode switching of (3), the output state of the flip-flop circuit (3) may change depending on the state of the clock signal before the mode switching and the state of the clock signal after the mode switching. Therefore, the mode switching of the flip-flop circuit (3) needs to follow a certain rule.

FIG. 3 is a diagram for explaining in what case the output state changes, and the cases are classified according to the state of the mode switching and the state of the clock signal (CP) before and after the switching,
The result of examining whether the output state is retained is shown.

When switching from the DFF mode to the TFF mode, if CKD = CP = “1” before the switching, the master section (5) retains the data, and its output passes through the transmission gate and goes to the slave section (6). The output has been reached. In this case, if CKT = CP = “1” after switching, the states of the master unit (5) and the slave unit (6) do not change after switching, and the data is retained. After switching, C
When KT = CP = “0”, the slave unit (6) is in a holding state, and the data output from the master unit (5) after switching is held in the slave unit (6), so that there is no change in data. Absent. On the other hand, if CKD = CP = “0” before switching, the slave unit (6) is in a data holding state and is outputting the data. In this case, CKT =
When CP = "1", the master section (5) is in a data holding state and this data is output from the slave section (6), so it is held in the slave section (6) before switching. The existing data will change. On the other hand, C after switching
When KT = CP = “0”, the holding state of the slave unit (6) does not change, so that the data is held.

Next, set the flip-flop circuit (3) from the TFF mode to D
When switching to FF mode, CKT = CP = before switching
In the case of "1", the master section (5) is in a data holding state, and its output is output from the slave section (6). In this case, if CKD = CP = “1” after switching, the states of the master unit (5) and the slave unit (6) do not change and the data does not change. Further, if CKT = CP = “0” after switching, the slave unit (6) is in a data holding state and holds the data output from the master unit (5) before switching, so the data does not change. . On the other hand, CKT = CP before switching
When = "0", the slave unit (6) is in a data holding state and this data is being output. in this case,
If CKD = CP = “1” after switching, the master unit
Since (5) becomes a holding state and its output is output through the slave section (6), the data held in the slave section (6) changes. After switching, CKD =
When CP = "0", the slave unit (6) is held, so that the data does not change as before switching.

As shown in FIG. 3, there is a possibility that the data may change before and after the change from the DFF mode to the TFF.
When switching to the mode, from CKD = "0" to CKT =
There are a case where it becomes "1" and a case where CKT = "0" changes to CKD = "1" when switching from the TFF mode to the DFF mode. Therefore, when switching the operation mode, attention must be paid to the signal levels of the first clock input CKT and the second clock input CKD.

By the way, since the CKT is connected to the output of the flip-flop circuit (3) at the preceding stage as shown in FIG. 1, the contents of the data of the flip-flop circuit (3) at each stage, that is, when operating in the counter mode. CK depending on the count value of and the data set by the parallel load mode
The level state of T changes and cannot be specified before and after the switching of the operation mode. On the other hand, CKD is a clock signal for controlling the shift of data or for controlling the loading of parallel data, so that the level can be determined by the side supplying the clock to CKD. Therefore,
Focusing on CKD in FIG. 3, if CKD is set to “1” before and after switching from the DFF mode to the TFF mode, there is no change in data, and before and after switching from the TFF mode to the DFF mode, CKD is set to “0”.
If it is set to, it can be seen that the data does not change.

Therefore, in FIG. 1, when the counter mode control signal (CTMOD) is switched from "0" to "1",
That is, when switching to the counter mode, the level of the second clock signal (CLK2) is held at "1", and when switching the counter mode control signal (CTMOD) from "1" to "0". , The second clock signal (C
The level of LK2) may be held at "0".

Next, regarding the operation of the embodiment circuit of the present invention shown in FIG.
This will be described with reference to the timing chart in the figure.

First, in the counter mode, the CTMOD signal = “1”. As a result, the Q output of each flip-flop circuit is connected to the data input of the master section (5). Therefore, each flip-flop circuit (3) toggles by the CLK1 signal and counts the pulses of the CLK1 signal.

Next, when the PLMOD signal becomes "1", the counter mode is switched to the parallel load mode. Before and after the mode switching, CLK2 = “0” is set. Then C
When the LK2 signal becomes “1”, the PI _{o to} PIn signals are input and parallel data is loaded.

Next, when the CTMOD signal becomes "1", the parallel load mode is switched to the counter mode. Note that CKT2 is set to "1" before and after the mode switching. After that, the number of pulses of the CKT1 signal can be added to the parallel data.

Next, when the SRMOD signal becomes "1", the counter mode is switched to the shift register mode. Note that CKT2 is set to "0" before and after the mode switching. After that, the data in the flip-flop circuit is sequentially shifted in synchronization with the CKT2 signal pulse.

Next, when the PLMOD signal becomes "1", the parallel load mode is set again. Next, when the CLK2 signal becomes “1”, the PI _{o to} PIn signals are input and the parallel data is loaded.

Next, when the SRMOD signal becomes "1", the mode is switched to the shift register mode. After that, the parallel load data is sequentially shifted in synchronization with the CKT2 signal pulse.

Next, when the CTMOD signal becomes "1", the shift register mode is switched to the counter mode. Note that CKT2 is set to "1" before and after the mode switching. Then, the CLK1 signal pulse is counted.

As described above, according to the embodiment circuit of the present invention, it is possible to realize a digital circuit having both a counter function and a shift register function with a small number of constituent elements.

(G) Effect of the Invention As described above, according to the present invention, it is possible to realize a digital circuit having a counter function and a shift register function with an extremely small number of elements as compared with a conventional circuit. As a result, the integrated circuit can be highly integrated.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a digital circuit according to an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of a flip-flop circuit forming the basic configuration of FIG. 1, and FIG. 3 is an embodiment circuit of the present invention. FIG. 4 is a diagram for explaining the switching of the operation modes of FIG.
5 is a timing chart for explaining the operation of the digital circuit shown in FIG. 5, FIG. 5 is a configuration block diagram of a conventional example, and FIG. 6 is an equivalent circuit diagram of a flip-flop circuit forming the basic configuration of FIG. (1), (2) …… Flip-flop circuit with conventional configuration, (3)…
... Flip-flop circuit according to the configuration of the present invention, (4) ...
Input / output control buffer, (5) ... Master section, (6) ... Slave section, (7), (8) ... Logic circuit, CKT ... First clock input for toggle operation, CLK1 ... First clock signal, TGL ... Toggle operation control input, CTMOD ...
... Counter mode control signal, CKD ... Second clock input for shift register operation, CLK2 ... Second clock signal, SD ... Serial data input, SDATA ...
... Serial data input / output signal, ESD ... Serial data selection control input, SRMOD ... Shift register mode control signal, PD ... Parallel data input, PI _{o to} PI
n: parallel data signal, EPD: parallel data selection control input, PLMOD: parallel load mode control signal, OPE: serial output enable signal, PO
_o ~ POn: Parallel data output signal.

Claims (1)

[Claims] 1. A master unit and a slave unit, and a toggle operation control input (TG) for instructing a T-FF mode.
L), the output of the slave unit is supplied to the data input of the master unit and the first clock input (CKT) for the toggle operation is supplied as the clock of the master unit and the slave unit, and the D-FF mode is set. A second clock input (CKD) for shift operation according to a toggle operation control input (TGL) for instructing the D-FF.
A parallel data selection control input (EPD) that supplies a serial data input (SD) to the data input of the master unit based on a serial data selection control input (ESD) that indicates a shift register mode in the mode, and indicates a parallel data load mode. Parallel data input (P
A plurality of flip-flop circuits each having a logic circuit for supplying D) to the data input of the master section, and a control signal corresponding to each of the toggle operation control input, the serial data selection control input, and the serial data selection control input. , The serial data input is connected to the Q output of the preceding stage, the first clock input is connected to the output of the preceding stage, and the shift clock is commonly applied to the second clock input. By
Each of the flip-flop circuits is operated in a counter mode, a shift register mode, and a parallel data load mode, and the signal level of the second clock input is set to the first or second when the signal level of the toggle operation control input is switched. A digital circuit characterized by being fixed at a level.