JPH0657009B2 - Repeater checker for multiplex transmission - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a repeater checker for multiplex transmission.

[Background technology]

In a general multiplex transmission control system, as shown in FIG. 1, one receiver RC and, for example, eight repeaters (each having 1 to 8 as an address) T
C _{1 to} TC ₈ are connected by a transmission line L, and the relays TC _{1 to} T 8 are connected.
A load (not shown) is connected to each C ₈ .

Then, to control the terminal device receiver RC via the repeater TC ₁ to Tc _8, it is designed to monitor the control status of the terminal unit. Specifically, repeater terminal unit receiver RC can be controlled is connected, sending to the transmission line L to control data, for example, TC ₁ address data 1 and the terminal device. Each of the repeaters TC _{1 to} TC ₈ is adapted to take in the address data and the control data sent out to the transmission line L, compare the taken-in address data with its own address, and when they match (self When the address is specified), the terminal is controlled based on the control data taken in. In this case, since the address data is 1, the repeater TC ₁ switches the control state of the terminal device based on the control data, and the other repeater TCs
_{1 to} TC ₈ do not switch the control state.

Further, at this time, the repeater T having its own address specified
C ₁ sends the monitoring data to the transmission line L at the same timing as the timing of fetching the control data, and the receiver RC
Captures this monitoring data at the same timing as the control data is sent, and monitors the control state of the terminal. This monitoring data is for the control data sent immediately before.

Normally, this multiplex transmission control system operates in two cycles of the previous control cycle and the subsequent monitoring cycle, and in the control cycle, sends control data to the repeaters TC _{1 to} TC 8 of addresses 1 to ₈ respectively and monitors them. Address 1-8 in cycle
The monitoring data of the repeaters TC _{1 to} TC ₈ are fetched, the monitoring data is not fetched in the control cycle, and the control data is not sent in the monitoring cycle.

A repeater used in such a multiplex transmission control system is configured as shown in FIG. This repeater is of the 3 control 3 monitoring type and is connected to the receiver RC by six transmission lines L _{1 to} L ₆ . The 6 lines are divided into a power supply voltage + 12V, a power supply line L ₁ , a GND (ground line) L ₂ , and a transmission signal (address data + control data) D.
Transmission signal line L ₃ for sending P, reply signal (monitoring data)
A reply signal line L ₄ for sending RD, a sub-sync signal line L ₅ for sending the sub-sync signal CP ₁ , and a main sync signal line L ₆ for sending the main sync signal CP ₂ . Sub sync signal CP ₁ , main sync signal CP
₂ , the transmission signal DP and the reply signal RD are transmitted at the timing shown in FIG. The main synchronization signal CP ₂ has a cycle 1
It is constantly transmitted from the receiver RC at KHz and high level (power supply voltage) time of 0.3 msec. The sub synchronization signal CP ₁ is
Phase in the same pulse as the main synchronization signal CP ₂ is transmitted advances 180 degrees, is transmitted in correspondence with the pulses from the first main synchronization signal CP ₂ to the 12th, the 13th 16th 4 pulses of corresponding duration of the pulse becomes empty pulse, so that each repeater TC ₁ to Tc ₈ detects the start information of the signal received by the free pulses of the 4 pulses. The transmission signal DP consists of address data from the first bit to the eighth bit and control data from the ninth bit to the twelfth bit, and these data are the first to the twelfth bits of the main synchronization signal CP ₂ . Sequentially sent at the same timing as the pulse. The reply signal RD is
It is sent at the same timing as the ninth to twelfth pulses of the main synchronization signal CP ₂ .

In this repeater, power is supplied to each circuit portion by a power supply circuit E ₁ . Then, the main synchronizing signal CP ₂ (FIG. 4 (B)) and the sub synchronizing signal CP ₁ sent from the receiver RC.
Based on (FIG. 4 (A)), the timing generation circuit TA
₁ generates various timing pulses.

This timing generation circuit TA ₁ generates a read signal A ₃ (FIG. 4 (D)) consisting of 12 pulses at the same timing as the first to twelfth pulses of the main synchronization signal CP ₂ . This read signal A ₃ is applied to the clock input terminal CK of the shift register SR ₁ . As a result, the shift register SR ₁ reads the transmission signal DP (address data + control data: FIG. 4C) sent from the receiver RC while sequentially shifting.

While the shift register SR ₁ is reading the transmission signal DP by the read signal A ₃ (FIG. 5 (A)),
Specifically, read signal as A ₃ outputs eight pulses, the transmission signal 8-bit address data of the DP is read into the shift register SR _1, the shift register SR ₁ of the output terminal Q ₁ to Q ₈ From the address data output in parallel, that is, the main synchronization signal CP
_The timing generation circuit TA ₁ generates the address coincidence timing determination signal A ₄ (FIG. 5 (B)) at the same timing as the pulse of the sub-synchronization signal CP ₁ between the 8th and 9th pulses of ₂ . , Address match detection circuit AD.

Address coincidence detection circuit AD is the address coincidence timing judgment signal A _4, output to Q ₁ shift register SR ₁
~ Q _{8 The} address data output from Q ₈ is compared with the self address set by the group of eight address setting switches SW ₁ , and when both addresses match, the output terminal Q
To generate an address coincidence signal and apply it to the output circuit DR.

Further, the address match signal after the occurrence also, the shift register SR ₁ is transmitting signals continue to read the DP, the main synchronization signal CP ₂ ninth through twelfth timing generating circuit TA ₁ at the same timing as the pulse output timing Pulses A ₆ , A ₇ , A ₈ (Fig. 5 (F), (G), (H))
Are generated respectively and are added to the output circuit DR.

The output circuit DR outputs data from the output terminals Q _{1 to} Q ₃ of the shift register SR ₁ when the output timing pulses A ₆ , A ₇ and A ₈ are applied in the state where the address match signal is input. The control data input to the terminals D _{1 to} D ₃ are output from the output terminals Q _{1 to} Q ₃ , and the delay circuits DL _{1 to} D ₃ are output.
Through L ₃ controls the relay RY ₁ ~RY _3.

In addition, the timing generation circuit TA ₁ uses the sub synchronization signal CP between the 12th and 13th pulses of the main synchronization signal CP ₂ .
A reset signal A ₅ (FIG. 5 (E)) is generated at the same timing as the ₁ pulse and is applied to the address coincidence detection circuit AD. As a result, the address match detection circuit AD stops outputting the address match signal.

Further, the timing generation circuit TA ₁ has the read signal A which rises at the same timing as the pulse of the sub synchronizing signal CP ₁ between the 8th and 9th pulses of the main synchronizing signal CP ₂ .
₂ (FIG. 5 (D)) is generated and added to the shift register SR ₂ . The shift register SR ₂ reads the 3-bit monitoring data applied to the input terminals P _{1 to} P ₄ . This monitoring data is input via the photocouplers PC _{1 to} PC ₃ .

After that, the timing generation circuit TA ₁ outputs the main synchronization signal CP ₂
The sending timing signal A ₁ (FIG. 5 (C)) is generated at the same timing as the ninth to twelfth pulses, and the monitoring data is sequentially shifted and sent from the output terminal Q as a reply signal RD.

The reply signal RD is transmitted only when an address is designated and is not shown in the circuit diagram. However, for example, the monitor data may be generated only when the address match signal is output. Alternatively, the transmission timing signal A ₁ can be generated only when the address coincidence signal is generated.

The address coincidence detection circuit AD is specifically realized by a circuit as shown in FIG. In the sixth figure, exclusive OR circuits EX ₁ ~EX ₈ AND circuit AN ₁ the address data (D ₁ ~D ₈₎ and the own address (D ₁ '~
D ₈ ′) are individually compared with each other, and when all match, the output of the AND circuit AN ₁ becomes high level, and the output of the AND circuit AN ₁ is output by the D flip-flop FF ₁ to the address match determination timing signal A ₄ Hold in response to
The reset signal A ₅ resets the D flip-flop FF ₁ .

The output circuit DR is specifically realized by a circuit as shown in FIG. In FIG. 7, AND circuits AN _{2 to} AN ₄ are shown.
Is opened when an address coincidence signal is output to pass control data (D _{1 to} D ₃ ), and AND circuits AN _{5 to} AN ₇ are opened when output timing pulses A ₆ , A ₇ and A ₈ are output. Control data (D _{1 to} D ₃ ) are passed.

Such a multiplex transmission control system is constructed on-site, but during the construction, wiring of trunk lines such as signal lines and power lines and wiring to sensors, dampers, etc. connected to repeaters are performed correctly. There is a possibility that there will be two cases, that is, a trouble with the repeater may occur and a trouble due to a defect in the repeater itself may occur.

For such troubles, there has been a demand for a checker capable of individually checking the repeaters in order to quickly determine the cause and deal with the troubles.

[Object of the Invention]

An object of the present invention is to provide a repeater checker for multiplex transmission, which can check the repeaters individually.

A repeater checker for multiplex transmission according to the present invention includes a power supply voltage,
The main synchronization signal composed of periodic pulses and a phase advance of 180 degrees from the main synchronization signal generate a pulse for a period corresponding to the number of bits of the address data and control data, and stop the pulse generation for a fixed number of subsequent periods. A sub-synchronization signal and a transmission signal composed of the address data and control data are sent from the receiver, and when the address data and the self-address match, the terminal device is controlled according to the control data, and the terminal device A repeater checker for multiplex transmission for checking a repeater that repeats a cycle operation of sending a reply signal consisting of monitoring data of the control state of the control data to the receiver at the same timing as the control data. An address data setting switch for setting address data, a control data setting switch for setting the control data, A signal start switch, a power supply circuit for generating a power supply voltage for the repeater, the main synchronization signal and the sub-sync signal, and based on the signal and the sub-sync signal generated by operating the transmission start switch in a control cycle. Each bit of the address data and control data is generated by generating a read timing signal which rises at the same timing as the pulse of the sub-synchronization signal half cycle before the pulse of the main synchronization signal corresponding to the first bit of the address data and control data. Generating a shift signal at the timing of each pulse of the sub-synchronization signal before the half cycle of the pulse of the main synchronization signal corresponding to
A read signal is generated at the same timing as each pulse of the main synchronizing signal corresponding to the control data, and the read timing signal is generated after the pulse of the main synchronizing signal corresponding to the last bit of the address data and the control data is generated. A falling timing generation circuit, which reads the address data and control data in response to the read timing signal, sequentially shifts the address data and control data in response to the shift signal, and outputs the transmission signal in series as the transmission signal. A first shift register; a second shift register which reads the monitoring data of the reply signal sent from the repeater while sequentially shifting in response to the read signal and outputs the read data in parallel; An indicator for displaying the output, and the read timing signal Of the data transmission completion detection pulse signal by detecting the trailing edge of the data transmission completion signal, and the data transmission completion detection pulse signal output from the differentiation circuit to the timing generation circuit It is characterized in that it is provided with an OR circuit for regenerating the read timing signal from the timing generation circuit in the next monitoring cycle by supplying in the combined state.

Embodiments of the present invention will be described below in detail with reference to the drawings.

A multiplex transmission repeater checker according to an embodiment of the present invention will be described with reference to FIGS. As shown in FIG. 8, this repeater checker for multiplex transmission is connected to the repeaters TC _{1 to} TC ₈ via _six transmission lines L _{1 to} L ₆ instead of the receiver RC at the time of test. It is something. The six internal divisions are as described above.

The multiplex transmission relay checker, the repeater TC ₁ to Tc ₈ with battery power supply BT, which is charged by the AC power supply AC of AC100V supplies power supply voltage to each circuit unit +
Supply a voltage of 12V.

Then, the timing generation circuit TA ₂ constantly generates the main synchronization signal CP ₂ (FIG. 9 (C)) and the sub synchronization signal CP ₁ (FIG. 9 (B)), and turns the transmission start switch SW ₂ on. When pressed, switch input circuit SI causes transmission start pulse B
₆ (FIG. 9 (A)) to generate the timing generation circuit TA ₂
Add to. The timing generation circuit TA ₂ uses the transmission start pulse B ₆ and the sub-synchronization signal CP ₁ as a basis for the main synchronization signal CP.
_The read timing signal B ₇ (FIG. 9 (G)) which rises at the same timing as the pulse of the sub synchronizing signal CP _{1 which} is a half cycle before the _first pulse of ₂ and the first of the main synchronizing signal CP ₂ The shift signal B _{3 is} generated at the timing of the trailing edge of each pulse from the pulse of the sub-sync signal CP ₁ half cycle before the pulse to the pulse of the sub-sync signal CP ₁ half cycle before the 12th pulse.
(FIG. 9 (D)) and the gate control signal B ₄ (FIG. 9 (E)) are generated. The shift register SR ₃ reads the address data set by the address data setting switch group SW ₃ at the timing of the read timing signal B ₇ , and the shift register SR ₄ sets the control data set by the control data setting switch group SW ₄ at the same timing. reading, the shift register SR _3, SR ₄ are sequentially shifts the address data and control data read by the shift signal B _3, the pulse width of the gate control signal B ₄ gate control signal B ₄ through the aND circuit aN ₈ which is controlled by The transmission signal DP (FIG. 9 (F)) is output.

Further, the timing generation circuit TA ₂ generates the read signal B ₅ (FIG. 10 (A)) at the same timing as each of the ninth to twelfth pulses of the main synchronization signal CP ₂ and shift register SR 2 ₅ sequentially reads the reply signal RD (FIG. 10 (B)) based on the read signal B ₅ and outputs the monitoring data to the output terminals Q _{0 to} Q ₃ , which drives the display elements LED _{1 to} LED _4. Then, the monitoring data is displayed on the display elements LED _{1 to} LED ₄ . The reply signal RD in FIG. 10 (B) indicates that the control of 2 is completed when the pulse indicated by the broken line is not output.

The read timing signal B ₇ [FIG. 12 (A)] output from the timing generation circuit TA ₂ is inverted by the inverter IN ₁ [signal B ₇ ′ in FIG. 12 (B)], and this signal B ₇ 'is differentiated by a differential circuit DF (12
Since the differential signal B ₇ ″ in FIG. 6C) and the differential signal B ₇ ″ are added to the switch input circuit SI via the OR circuit OR ₁ together with the pulse signal by the operation of the transmission start switch SW ₂ , the transmission start switch once When SW ₂ is operated to perform the operation of the control cycle, the operation of the next monitoring cycle can be automatically performed.

The above-mentioned inverter IN ₁ , differentiation circuit DF and OR circuit OR ₁
Generates a pulse signal at the trailing edge of the read timing signal output from the timing generation circuit in the claims, and the pulse signal causes the timing generation circuit to regenerate the read timing signal in the next monitoring cycle. .

Next, the operation procedure of this multiplex transmission repeater checker will be described.

The address setting switch group SW ₃ is set to the repeater address to be checked.

The control data setting switch group SW ₄ is set to the control state to be checked.

Press the transmission start switch SW ₂ (control cycle). For example, assuming that the repeater address is 1 and the control is 2, the transmission signal DP is as shown in FIG. 11 (A), and the reply signal RD returned from the repeater TC _{1 having the} address 1 is shown in FIG. 11 (C). ), The reply signal RD at this time corresponds to the previous control state and does not become monitoring data.

Next cycle (monitoring cycle). In this cycle, since the pulse signal is applied to the switch input circuit SI from the differentiating circuit DF at the timing of the trailing edge of the read timing signal B ₇ of the previous cycle in the same manner as when the transmission start switch SW ₂ is operated, it automatically starts. To do. The transmission signal DP at this time is as shown in FIG. 11 (B), and the reply signal RD returned from the relay TC _{1 having the} address 1 is shown in FIG. 11 (D).
The monitor data of the reply signal RD at this time shows the result corresponding to the control data of the transmission signal DP transmitted in, and if the control data in and the monitor data in The operation of control 2 of the repeater TC ₁ can be checked.

This check is performed by the repeaters TC _{1 to} TC ₈ of each address.
Are sequentially performed, and each control is also sequentially performed.

As a result of such a configuration, it is possible to check the circuits of the repeaters TC _{1 to} TC ₈ , check the crossovers of the repeaters, and check the wiring of the terminal. Further, since it is operated by the battery power source BT and is small and lightweight, it is easy to carry, and the cause of the repeater trouble can be quickly clarified.

Further, since the pulse signal obtained by inverting and differentiating the read timing signal B ₇ is applied to the switch input circuit SI via the OR circuit OR ₁ , the transmission start switch S
By pressing W ₂ once, it is possible to perform two cycles of operation including the control cycle and the monitoring cycle, and the operation for checking the repeaters TC _{1 to} TC ₈ becomes easy.

Although the number of repeaters is eight in the above-described embodiment, since the address can be set by a combination of 8-bit data, a maximum of 256 addresses can be set, and control data and monitoring data can also be set at the maximum. Eight types can be set.

〔The invention's effect〕

According to the multiplex transmission repeater checker of the present invention, the trouble of each repeater can be clarified by a quick and easy operation. Further, an OR circuit is provided so that a pulse signal is generated at the trailing edge of the read timing signal output from the timing generation circuit, and the pulse generation signal causes the timing generation circuit to regenerate the read timing signal in the next cycle. By pressing the transmission start switch once, the control cycle and monitoring cycle can be
The operation of the cycle can be performed, and the operation for checking the repeater becomes easy.

[Brief description of drawings]

FIG. 1 is a schematic diagram of a conventional multiplex transmission control system, FIG. 2 is a circuit diagram of a repeater thereof, FIGS. 3, 4, and 5 are timing charts of respective parts, FIG. 6, and FIG. Is a specific circuit diagram of a main part of a repeater, FIG. 8 is a circuit diagram of a repeater checker for multiplex transmission according to an embodiment of the present invention, and FIGS. 9, 10, 11, and 12 show respective parts thereof. It is a timing diagram. BT ... battery power, SW ₂ ... transmission start switch, TA ₂
... Timing generator, SR ₃ , SR ₄ , SR ₅ ... Shift register, SW ₃ ... Address data setting switch, SW ₄
... Control data setting switch, LED _{1 to} LED ₄ ... Display element

Claims (1)

[Claims] 1. A power supply voltage, a main synchronization signal composed of periodic pulses, and a phase advance of 180 degrees from the main synchronization signal, generating pulses during a period corresponding to the number of bits of address data and control data, and a constant number thereafter. The sub-synchronization signal for stopping the pulse generation during the period of, and the transmission signal composed of the address data and the control data are sent from the receiver, and when the address data and the self address match, the sub-synchronization signal is generated according to the control data. A repeater checker for multiplex transmission for checking a repeater that controls a terminal and sends a reply signal consisting of monitoring data of the control state of the terminal to the receiver at the same timing as the control data. Address data setting switch for setting the address data of the repeater to be checked, and the control for setting the control data. A data setting switch, a transmission start switch, a power supply circuit that generates a power supply voltage for the repeater, a signal that is generated by operating the transmission start switch in a control cycle, and the sub synchronization that generates the main synchronization signal and the sub synchronization signal. A read timing signal which rises at the same timing as the pulse of the sub-synchronization signal half cycle before the pulse of the main synchronization signal corresponding to the first bit of the address data and the control data based on the signal, and the address data and A shift signal is generated at the timing of each pulse of the sub-synchronization signal half cycle before the pulse of the main synchronization signal corresponding to each bit of the control data,
A read signal is generated at the same timing as each pulse of the main synchronizing signal corresponding to the control data, and the read timing signal is generated after the pulse of the main synchronizing signal corresponding to the last bit of the address data and the control data is generated. A timing generation circuit for falling, reading the address data and control data in response to the read timing signal, sequentially shifting the address data and control data in response to the shift signal, and outputting in series as the transmission signal. A first shift register; a second shift register which reads the monitoring data of the reply signal sent from the repeater while sequentially shifting in response to the read signal and outputs the read data in parallel; An indicator for displaying the output, and the read timing signal Of the data transmission completion detection pulse signal by detecting the trailing edge of the data transmission completion signal, and the data transmission completion detection pulse signal output from the differentiation circuit to the timing generation circuit A repeater checker for multiplex transmission, comprising an OR circuit for regenerating a read timing signal from the timing generating circuit in the next monitoring cycle by supplying in a combined state.