JPH0411058B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a time division multiplex transmission system.

[Background technology]

Conventionally, this type of time division multiplexing transmission system
As shown in the figure, a central control device 1 and a plurality of terminal devices 2 are connected by a signal line 3, and address data D _A for calling the terminal device 2 from the central control device 1 to the terminal device 2 is transmitted. Transmission data D _S consisting of control data D _C for controlling, other data D _O , and checksum data D _P for checking errors in data transmission.
time-division multiplex transmission. The format of the transmission signal V _S that transmits _the transmission data D _S is as shown in FIG. In the figure, SP is a start pulse indicating the start of transmission of the transmission signal V _S , and WP is a return period setting pulse that sets the return timing of the monitoring data D _B sent back from the terminal device 2 to the central control device 1.

However, the other data _D0 is data in a predetermined format that conforms to the control data.

On the other hand, _the terminal device 2, as shown in _FIG .
and check sum data for errors in transmission data D _S.
An error verification unit 13 that performs verification based on D _p and an address verification unit 1 that compares its own unique address set in the address setting unit 12a with address data and outputs an address match signal V _A when they match.
2, when the address matching signal V _A is obtained and the data is being transmitted normally, the control data D _C is output by the latch clock CL ₁ output from the error verification section 13.
an output latch section 14 that latches the output, and a monitoring input section 1
Monitoring data based on the monitoring signal input from 5a
It is formed by a _monitoring data creation _{unit 15} that creates _D When the control data D _C is latched to the output latch section 14, a return signal V _B for returning the monitoring data D _B is sent from the data transmitting/receiving section 10 to the signal line 3 during the return waiting period. . By the way, in such a conventional example, each terminal device 2 only has the function of outputting control data D _C sent to its own unique address in a transmission signal V _S of a predetermined format, and the signal line 3 did not have a function to arbitrarily monitor the transmission data D _S above.

[Purpose of the invention]

The present invention has been made in view of the above points, and is based on a method of converting data transmitted on a signal line between sending monitor start data to a terminal device and sending monitor end data from a central control device to a predetermined bit. It is an object of the present invention to provide a time division multiplex transmission system that can arbitrarily monitor multiple block data.

[Disclosure of the invention]

Embodiment 1 FIG. 3 shows a block circuit diagram of a main part of a terminal device 2 according to an embodiment of the present invention, in which 16 is a monitor clock generating section consisting of a counter CO ₁ that is reset by an address match signal _VA ; Each bit signal (pulse signal) of the received transmission data D _S is counted and a data monitoring clock CL ₂ is generated every time a predetermined number of bits (8 bits in the embodiment) of block data is received. 17 is a data switch 18
, a latch control section 19 consisting of AND circuits A ₁ , A ₂ and an OR circuit O ₁ , and a decoder DE AND circuit
A ₂ and the NOR circuit forming the R-S latch N ₁ ~
This is a monitor switching unit formed by a switching control unit 20 consisting of _N4 , and is used for the period from the output of the detection signal V _MS of monitor start data from the decoder DE until the output of the detection signal V _ME of monitor end data. The monitor switching signal V _M becomes "1", and the data D _M sent from the central controller 1 between the monitor start data and the monitor end data is input to the output latch section 14 via the data switch section 18. , the latch unit 14 outputs block data D _Ma , D _Mb . . . in 8-bit units at the data monitor clock CL _2.
It is designed to latch on. In the figure, reference numeral 21 denotes a data memory that stores monitor data outputted via the output latch section 14. Note that the other configurations and operations are completely the same as the conventional example shown in FIG.

The operation of the first embodiment will be explained below. Currently, when monitor start data is not being sent from the central controller 1, the monitor switching signal V _M is “0”.
The terminal device 2 performs normal mode control and monitoring operation as in the conventional example shown in FIG. 2, and receives address data that matches its own unique address as shown in FIG.
When D _A is received and an address match is obtained,
Based on the checksum data _Dp , it is verified whether the transmission data D _S is being transmitted without error or not, and if the transmission data D S is being transmitted without error, the control data D _C is latched in the output latch section 14. FIG. 4e shows the latch timing of the control data _DC . Next, FIGS. 4f to 1 show the monitor operation according to the present invention, and now, as shown in FIG. 4f,
When monitor start data is sent from the central controller 1 as control data D _C of the transmission signal V _S in a predetermined format, the monitor start data is output to the latch unit 1.
4, the data is decoded by the decoder DE of the switching control section 20, and the detection signal _VMS of the monitor start data is outputted from the decoder DE as shown in FIG. At this time, when the R-S latch consisting of NOR circuits _N3 and _N4 is set and the monitor switching signal V _M becomes "1", all bit data of the data D _M transmitted following the monitor start data are sequentially transferred. The signal is input to the output latch unit 14 via the data switch 18, and is latched by the data monitor clock _CL2 as shown in FIG. 4g. That is, every time 8 bits of data _DM transmitted following the monitor start data are received, they are sequentially latched in the output latch section 14 as block data D _Ma , D _Mb . . . . The block data D _Ma , D _Mb . . . of the data outputted through the output latch section 14 in this manner are sequentially stored in predetermined locations of the data memory 21 set based on the output of the counter CO ₁ . Next, when monitor end data is sent from the central control device 1 as control data in a predetermined format, the decoder DE of the switching control section 20
The detection signal V _ME of the monitor end data is shown in Figure 4 i.
As shown in FIG. 2, an R-S latch consisting of NOR circuits N ₁ and N ₂ is set by the output, and then the address matching signal V _A of the transmission signal V _S sent in the original format from the central controller 1 is output. When this is obtained, the R-S latch made up of NOR circuits _N3 and _N4 is reset, the monitor switching signal V _M becomes "0", and the terminal device 2 returns to the normal mode of control and monitoring operation. Fourth
Figure k shows the monitor switching signal V _M and Figure 4 l shows the NOR circuit.
_N1 output.

As described above, in the present invention, from the time when the central control device 1 sends the monitor start data to the terminal device 2 to the time when the monitor end data is sent, the data transmitted on the signal line is The control data can be monitored in an appropriate format (latched as block data of a predetermined number of bits) different from the format used in the latch processing of control data.
This makes it possible to realize a versatile monitor function.

Embodiment 2 FIG. 5 shows another embodiment. In place of the monitoring input section 15a of the embodiment in FIG. 3, a monitor address setting section consisting of a dip switch sets the start address of a series of terminal devices 2 to be monitored. By providing 24, the above start address can be used as monitoring data.
It returns to the central control device 1 as D _B , and continuously transmits each control data D _C for a series of terminal devices 2 to be monitored from the central control device 1 to the monitoring terminal device 2 as monitor data D _M. In place of the data memory 21, there are shift registers 22 ₁ to 22n that hold monitor data _DM and a 7-segment display 23a that displays the monitor data _DM .
23c is provided to display each control data D _C transmitted to a series of terminals 2 to be monitored. In the figure, 25 is a data processing section including the address verification section 12, error verification section 13, and monitor clock generation section 16;
A ₄ and A ₅ are AND circuits.

The operation of the second embodiment will be explained below. In the embodiment, monitor data from the output latch section 14
Since D _M is output as 8-bit block data D _Ma , D _Mb . . . , the shift registers 22 ₁ to 2
The number of clocks 2n is eight (n=8), and the data monitor clock CL ₂ output from the data processing section 25 is used as the shift clock for each shift register 22 ₁ to 22 ₈ . Furthermore, 3-bit shift registers are used as the shift registers 22 ₁ to 22 ₈ so that control data D _C to be transmitted to three terminals 2 with consecutive addresses can be held. Now, I want to monitor the deep switch in the monitor address setting section 24.
When setting the start address of the terminal device 2 and setting the transmission permission signal V _T to the "H" level by operating the transmission switch, the data will be accessed by the transmission signal V _S in the original format from the central control unit 1. When the above first address is the monitoring data
It is sent back from the terminal device 2 to the central control device 1 as D _B. When the central control unit 1 receives this first address, the control data D _C (8 bits) to be transmitted to the terminal device 2 at the first address and the following two addresses are sent to the terminal device 2 as monitor data D _M (24 bits). Transmit. However, since the procedure for transmitting the monitor data _DM is exactly the same as in the first embodiment, a description thereof will be omitted. This monitor data _DM is sequentially outputted from the output latch section 14 as 8-bit block data _DMa , _DMb , _DMc , held in shift registers ₂₂₁ to ₂₂₈ , and displayed as block data DMa on display devices 23a to 23c _. , D _Mb , D _Mc, that is, the control data D _C of the three terminal devices 2 to be monitored are displayed.
Note that if the number of bits of the shift registers 22 ₁ to 22 ₈ and the number of indicators are increased, the central control unit 1
It also becomes possible to display the control status of all terminals 2 at a different location. Also, the transmission permission signal V _T
is reset to "L" level by the monitor end data detection signal V _ME and ends the monitor operation.

As described above, in the second embodiment, by setting the start address of a series of terminal devices 2 to be monitored in the monitor address setting section 2, the control data D _C is transmitted to an appropriate number of terminal devices 2. can be displayed on the monitor, making it easy to check the operating status of the system and perform maintenance such as maintenance and inspection.

〔Effect of the invention〕

As described above, the present invention connects a central control device and a plurality of terminal devices by a signal line, and transmits address data for calling the terminal device from the central control device to the terminal device, control data for controlling the load, etc. In a time-division multiplex transmission system in which transmission data is time-division multiplexed, and a terminal device takes in control data following the address data that matches its own unique address and latches it into an output latch section as appropriate, address matching is achieved. A monitor clock generator generates a data monitor clock every time a predetermined number of bits of data is received, and monitor end data is input after monitor start data transmitted in place of control data is input. The terminal device is provided with a monitor switching section that sequentially latches a predetermined number of bits of data as block data to the output latch section using the data monitor clock, and a signal is sent from the central controller between the monitor start data and the monitor end data. The data transmitted on the line is latched as block data of a predetermined number of bits to the output latch section, and the transmission data and serial data transmitted on the signal line are monitored (objectively) as block data of a predetermined number of bits. data evaluation)
This has the effect of realizing a highly versatile monitor function.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a schematic configuration of a time division multiplex transmission system according to the present invention, FIG. 2 is a block circuit diagram of the same essential parts, FIG. 3 is a block circuit diagram of essential parts of an embodiment of the present invention, and FIG. This figure is an explanatory diagram of the same operation as above, and FIG. 5 is a main block circuit diagram of another embodiment. 1 is a central control unit, 2 is a terminal device, 3 is a signal line,
14 is an output latch section, 16 is a monitor clock generating section, and 17 is a monitor switching section.

Claims (1)

[Claims] 1 A central control unit and multiple terminals are connected via signal lines, and transmission data such as address data for calling terminals and control data for controlling loads is transmitted from the central control unit to the terminals using time division multiplexing. However, in a time division multiplex transmission system in which a terminal device takes in control data following address data that matches its own unique address and latches it into an output latch section as appropriate, after an address match is obtained, a predetermined number of bits are a monitor clock generator that generates a data monitor clock every time data is received, and a monitor clock generator that generates a data monitor clock every time data is received; The terminal device is equipped with a monitor switching unit that sequentially latches a predetermined number of bits of data as block data in the output latch unit, and the data transmitted from the central controller to the signal line between the monitor start data and the monitor end data is A time division multiplex transmission system in which block data of a predetermined number of bits is latched to an output latch section.