JPH0657025B2 - Line scanning method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a communication control device for controlling a plurality of line adapters for accommodating a plurality of different types of lines, in which interruptions from the plurality of line adapters are sequentially performed. The present invention relates to a line scanning method for controlling.

(Prior Art) Conventionally, in this type of line scanning method, a line scanning skip function (hereinafter, scan skip function) and a priority scanning function are added.

The scan skip function is a function of suppressing line scanning of unused line slots and efficiently performing line scanning because the number of accommodated lines differs depending on the system.

With the priority scan function, when the number of accommodated lines is smaller than the maximum accommodated line, the scan skip function uses the skipped empty scan slot to scan the high-speed line and to scan the line faster than other lines. By increasing the ratio, it is a function that preferentially receives interrupts from high-speed lines.

FIG. 3 shows an example of a block diagram of a conventional line scanning system of this type in which the above-mentioned two functions are added. FIG. 3 is a block diagram of the line scanning system when the maximum number of lines accommodated in the communication control device is 16 and four line adapters are accommodated per slot (one line board).

In FIG. 3, 1 is a line scanning circuit which is common regardless of the number of lines. The line scanning circuit 1 is mainly composed of a scanning counter 1-1,
ROM1-2, select decoder 1-3 and common control circuit 1-4
It consists of The scanning counter 1-1 is a counter that counts every line scanning clock and creates a time interval of time slots assigned to each line board. Furthermore, the scanning counter 1-1 carries out a carry every 4 counts and performs counting corresponding to the circuit board, and corresponds to 16 scanning clocks (based on the assumption that the maximum accommodated line is 16 lines), that is, the circuit board. It is a binary counter that returns to 0 when it is counted up to 3 (S ₂ ′ in FIG. 3 is “11”). ROM
1-2 is the circuit board 2-1 to 2-4 which accommodates the signal line S ₂ ′ having the weight of 2 ³ and 2 ² among the scan counter output lines and the line adapters for 4 lines. The signal lines a, b, c, d for notifying the state are input, and the line board on which the line scanning is actually performed is determined by the above signals. Specifically, the signal line a,
When all the input signals b, c, and d indicate the mounted state, the circuit boards are sequentially selected according to the scan counter 1-1. When any of the input signals of the signal lines a, b, c, d indicates the unmounted state, the line scanning of the unmounted circuit board is suppressed (scan skip function) and the high speed line It is assigned to the circuit board (which is fixed in advance and is the circuit board 2-1 in FIG. 3 in this example). Select decoder 1
-3 decodes the output line S ₁ ′ of the ROM 1-2, and its output is connected to the select decoder of each circuit board via the signal lines S _{1-1 to} S _1-4 corresponding to each circuit board. . Common control circuit
1-4 are scan counter 1-1, ROM1-2, select decoder 1
When an interrupt signal S ₃ from each circuit board is received in an interrupt permission time slot assigned to each circuit board by -3, a signal line group S is sent to a microprocessor (not shown).
Interrupt via _M , interrupt line from microprocessor,
When a sense request such as an interrupt code is received via the signal line group S _M , the above information is sent to the microprocessor.

2-1 to 2-4 are circuit boards, respectively. Although details of 2-2 to 2-4 are not shown, the line configuration is the same as that of 2-1. In this line board 2-1 through 2-4, 2-a when slot selection signal S _1-1 is valid, decodes the lower two bits of the scan counter 1-1 (weight of 2 ^1, 2 ⁰⁾ , A select decoder that creates an interrupt-enabled time slot for each of the lines (4 lines) accommodated in the line board. The select decoder 2-a validates S _5-1 when the 2-bit value of the scan counter 1-1 is 0 in the circuit board, S _5-2 when it is 1, and S _5-3 when it is 2 in the following order. , 3, S _5-4 is valid. For 2-b _{0 to} 2-b ₃ , the above-mentioned signal lines S _{5-1 to} S _5-4 are effective,
That is, when the slot of the circuit board 2-1 is selected, the scan counter value is assigned to the time slot of a predetermined circuit, and the interrupt signal S ₃ ′ of the circuit is valid,
It is a gate with a tristate that sends an interrupt signal S ₃ to the common control circuit 1-4. 2-c _{0 to} 2c ₃ enable output signal S ₃ ′ when any of a plurality of interrupts from a predetermined line occurs, and enable common control circuit 1-4 to sense the interrupt code of the above line. This is an interrupt circuit that sends an interrupt code to the signal line S ₄ when it is received by a signal line (not shown).

4A and 4B show various time charts of the block diagram of FIG. The reference symbols on the time chart correspond to the reference symbols in the block diagram of FIG.

FIG. 4A is a time chart of the line scanning when all the circuit boards 2-1 to 2-4 are mounted, and the line scanning is sequentially performed according to the count of the scan counter 1-1.

FIG. 4 (B) is a time chart of line scanning when the circuit board 2-2 is not mounted and the signal line b in FIG. 3 is invalid. Since the circuit board 2-2 is not mounted, the line scanning of the circuit board 2-2 is suppressed, the time slot of the circuit board 2-1 is assigned after the time slot of the circuit board 2-1, and then the empty slot is allocated. The time slot of the circuit board 2-1 is allocated again by using it, and then the time slot of the circuit board 2-4 is allocated and line scanning is performed. By utilizing the fact that an empty time slot is created by the scan skip function of an unmounted board in this way, by assigning the empty time slot to a line slot accommodating a high-speed line,
It is possible to allocate a time slot to a high-speed line more than once during one round of the scan counter. Therefore, the ratio of line scanning to high-speed lines can be increased. That is, while the line scan time slot is assigned once to the line other than the high speed line, the line scan time slot can be assigned to the high speed line more than once, and the priority scan for the high speed line is possible.

Here, if an interrupt is detected at the time point (a) in FIG. 4 (A) (the output signal S ₃ ′ in FIG. 3 2-c ₁ is valid before the time point (a), If the interrupt signal S ₃ is detected at the time of a)),
The scan clock is temporarily stopped by the common control circuit 1-4, interrupts the microprocessor, interrupts the line number (line number 1 from the slot 0 as the smallest number), and operates the scan clock again after the microprocessor finishes sensing the interrupt code. Do. The microprocessor performs a predetermined interrupt process according to the interrupt code after the above information sensing. When the common control circuit 1-4 again operates the scan clock, and when an interrupt is detected at the time point (a) in FIG. 4 (A), the scan clock is similarly stopped, and the scan clock signal at the time point (a) is reached. Wait until the interrupt processing is completed, interrupt the microprocessor again, interrupt line number (line number 2 from slot 0 as the smallest number), and after the microprocessor senses the interrupt code, activate the scan clock in the same way. To do. In this way, if all lines are interrupted sequentially from the time point of (A), the time slot of the line number 0 before (A) is valid from the line number 1 to the line number 15 It is after the interrupt processing by the microprocessor up to.

On the other hand, in FIG. 4 (B), the line number ((A)
If all the lines have been interrupted since the time of (1), the scan of the line number 0 is the line number 1 to the line number 3 and the line number 8
After the interrupt processing by the microprocessor up to line number 11. Therefore, the maximum service holding time for the line number 0 is reduced to less than half as compared with FIG. 4A (although the decrease in the number of lines also has an effect).

Further, in FIG. 4 (A), when it is desired to add a priority scanning function to a high-speed line, the scan counter 1-1 is set to a binary counter that returns to 0 when counting up to 20 scan clocks. ) From the scanning clock 4
The priority scan function can be realized by allocating to the time slot of the individual slot 0 (circuit board 2-1).

As described above, the line scanning of the unused line slot is suppressed by the conventional line scanning method, the empty time slot of the unused line is used, and the priority scan of the high speed line is possible.

(Problems to be Solved by the Invention) However, such a conventional line scanning method has the following problems.

i) Since the unit of line scanning is the line board (slot), there are the following two problems.

Priority scan line (line to increase the line scan ratio)
Becomes a circuit board unit, and 4 circuits per circuit board, even if only 1 circuit is a high speed circuit and the other circuits are low speed circuits, all 4 circuits are set as priority scan circuits. Also, there may be a plurality of priority scan lines due to the structure of the circuit board. At this time, it is necessary to perform the priority scan on a plurality of circuit boards, and the original priority scan function may not be sufficiently fulfilled.

At present, there are various interfaces, and the types of line adapters are increasing accordingly. Moreover, the number of lines per circuit board cannot be fixed. As a result,
For example, when line boards having different numbers of lines, such as 4 lines and 2 lines per line board, are mixed and accommodated, useless line scanning is performed in the above-described method. For example, when a circuit board accommodating two circuits is mounted in the example of FIG. 3, a wasteful circuit scanning time slot for two scanning clocks is created. Furthermore, line scanning is impossible for the maximum number of lines that can be accommodated.
For example, in the case of one circuit board accommodating two lines and three circuit boards accommodating four lines, the above conventional method can scan only 14 lines, and the remaining 2 lines cannot scan lines.

ii) Further, since the scan counter is used as the line scanning method, there are the following two problems.

When the counter value for one round of line scanning is fixed and there are many unused line circuit boards, the number of scan skips of unused line circuit boards increases. Therefore, the line scan ratio (detailed definition will be described later) of the priority scan line may be too high, and the service to the constant speed line may be extremely deteriorated.

Similar to the term, the priority scan ratio is affected by the number of unmounted boards. Therefore, the line scan ratio of the priority scan line cannot be fixed. R to fix the line scan ratio
When creating an OM, there is no other way than fixing the ratio by performing useless line scanning for unimplemented lines, and in this case, useless line scanning increases.

iii) Similar to the item ii), since the scan skip function and the priority scan function are not independent, it is difficult to operate the above two functions in a complete form.

iv) Since the scan clock is supplied to the scan counter,
The output signal of the time slot actually assigned (3rd
The delay times of the ROM and the select decoder are added until the steps S _{1-1 to} S _1-4 ) appear, which adversely affects the scan clock cycle, and it takes one line scan to increase the time.
It is a cause.

v) A signal line for allocating a line scanning time slot to each circuit board by the select decoder ( _{S1-1 in} FIG. 3).
S _1-4 ) and the signal lines (a, b, c, d in FIG. 3) for notifying the mounted / unmounted state of the circuit board are required. Therefore, when the number of accommodated lines is large, the number of these signal lines increases. For example, in the case of FIG. 3, when the number of accommodated lines is 16,
Eight signal lines are required. The number of lines accommodated is 64
In the case of a line, 32 signal lines are required.

Therefore, an object of the present invention is to solve the above problems.

(Means for Solving Problems) A feature of the present invention for solving the above problems is to provide a plurality of line adapters for accommodating a plurality of lines and sequentially control interrupt requests from the plurality of line adapters. In the communication control device having a line scanning circuit for performing the priority scanning, the line scanning circuit scans more lines than other lines and sets the lines to be preferentially scanned in ascending order from the smallest line and the line adapter. Storage means and storage means for storing the number of lines obtained by setting the lines in descending order from the oldest number to the lines to be skip-scanned, which is determined according to the mounted / unmounted state of each line obtained from the side Means for sending line numbers to be sequentially scanned in accordance with the scanning clock to all line adapters based on the information from each of the line adapters. Information setting means for storing the line number of the line to be connected and the mounted / unmounted state of the line, and comparing means for comparing the line number sent from the line scanning circuit with the line number output from the information setting means. And a line scanning system which permits interruption from the corresponding line when the line numbers of both match.

(Operation) The line scanning circuit determines the line numbers to be sequentially scanned based on the number of lines to skip scanning and the number of priority lines, which is determined according to the mounted / unmounted state of each line obtained from the line adapter side. Send to all line adapters. That is,
In one round of line scanning, the priority line is scanned a plurality of times (in other words, interrupts are enabled), the other mounted lines are scanned once, and the unmounted number is skipped. Such a line number is given to the comparison means provided in each line adapter and compared with the line number from the information setting means provided in each line adapter. When both line numbers match, the interrupt from the corresponding line is permitted. Therefore, the above problems are solved.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of the present invention. Like the example of FIG. 3, the maximum number of accommodated lines is 16 lines,
It is a block diagram in the case of accommodating four lines per one slot (one line board) of line adapters. In FIG. 1, circuits and signal lines having the same symbols as in FIG. 3 have the same functions as in FIG.
In FIG. 1, reference numeral 1-5 is a scan mode register, which holds the number of lines for which a priority scan is performed and the number of lines for which a scan skip is performed. The number of priority scan lines and the number of scan skip lines store the number of priority scan lines (the number of lines that increase the line scan ratio) and the number of scan skip lines (the number of lines that suppress line scanning) set during system generation. Memory (not shown)
Then, the scan mode register 1-5 is set according to the actual mounted / unmounted state, which is detected by the hardware capable of sensing the mounted / unmounted state of each line number by a microprocessor (not shown). This hardware corresponds to the signal line S _{10 in} the information setting circuit 2-d ₀₁ described later in FIG.
Is added to the interrupt code. 1-
Reference numeral 6 is a ROM, which is supplied through the signal line groups S ₆ and S ₇ respectively, and the number of priority scan lines and scan skip lines, and the scan register 1-7 through the signal line groups S ₁₁ and S ₈ , respectively. Input priority scanning slot value (specify the line scanning ratio described later) and line scanning time slot number (line number for line scanning), and output the next priority scanning slot value and line scanning time slot number. . Reference numeral 1-7 is a scan register that samples the output of the ROM 1-6 for each scan clock and outputs the signal to the signal line groups S ₈ and S ₁₁ , respectively.

Here, the line scan ratio is the ratio of the number of times the line scan time slot is assigned to the priority scan line while the line scan time slot is assigned once to the lines other than the priority scan line. For example, when the line scan ratio is 4, the line scan time slot is assigned to the priority scan line four times while the line scan time slot is assigned to the lines other than the priority scan line once. That is, when the line scan ratio is 4, the priority scan time slot value of the signal line group S ₁₁ changes in the order of 0 → 1 → 2 → 3 every one line scan. In this case, the priority scan line is scanned every time the priority scan time slot value changes (in this case, it is scanned four times), while the other lines are scanned once every one line scan. It

Further, in the case of the present embodiment, the signal line group S ₈ is composed of four signal lines each having a weight of 2 ³ , 2 ² , 2 ¹ , 2 ⁰ because the maximum number of lines to be accommodated is 16.

2-d ₀₁ is an information setting circuit, provided for each line adapter,
It outputs its own line number to the signal line group S ₉ , and outputs the mounted / unmounted state of the line to the signal line S ₁₀ . 2-d ₀₂ is a comparison circuit, which compares the own line number on the signal line group S _{9 with} the line scanning time slot number on the signal line group S ₈ when the signal line S ₁₀ indicates the mounted state. . When the two match, the comparison circuit 2-d ₀₂ sends a signal to the signal line S _5-1 to permit the interrupt sending from its own line. Such information setting circuit 2-d ₀₁
The comparator circuit 2-d ₀₂ is provided for each of the line adapters 2-d ₀ to 2-d ₃ .

Next, regarding the operation of the block diagram shown in FIG. 1, FIG.
This will be described with reference to (A) to (C).

FIG. 2A is a time chart when the number of priority scan lines is 0 and the number of unused lines is 0, that is, when the maximum number of accommodated lines is fully implemented. The reference symbols of the signals on the time chart are the same as those in FIG. In this case, since the number of priority scan lines and the number of unused lines are both 0, the signals on the signal line groups S ₆ and S ₇ are both 0. Therefore, line scanning is sequentially performed for each scanning clock. Further, since the number of priority scan lines is 0, the signal line group S _{8 is} sent to each line adapter while the priority scan time slot value on the signal line group S ₁₁ makes one round (0 → 1 → 2 → 3). One line scan time slot is provided via each.
The line scan time slot number (line number) is compared with the line number stored in the information setting circuit (2-d _{01 in} the case of line adapter 2-d ₀ ) of each line, and the interrupt right is granted only to the matching line adapter. Is given. Here, the line number values in the information setting circuits of the respective line adapters are all set to different values, and in the case of this embodiment, there are 16 lines, so 0
Values of ~ 15 ₍₁₀₎ are stored in the corresponding information setting circuit. Further, a signal indicating the mounting state is stored in each setting information circuit.

Further, in FIG. 1, even if the number of lines per line board is different, or even if the number of line boards is different, if the information setting circuit of each line adapter sets different line numbers, it becomes as shown in FIG. 2 (A). Operations similar to those shown are performed.
For example, when the circuit boards 2-1 to 2-4 are 4 circuits, 2 circuits, 5 circuits and 3 circuits respectively, or the number of circuit boards is different, for example, the circuit boards 2-1 to 2-4 are 4 circuits respectively. ,
Even if there are 2 lines, 4 lines, and 4 lines, and the line board 2-5 not shown in FIG. 1 has 2 lines, if the line numbers of the information setting circuits are set to 0 to 15 ₍₁₀₎ without duplication. The operation is the same as in FIG. 2 (A). That is, the number of circuit boards, the number of circuits, and the position of the circuit boards are not affected at all.

FIG. 2B is a line scanning time chart in the case where the number of priority scan lines is 2 and the number of unused lines is 4, that is, the number of accommodated lines is 12 in the block diagram of FIG.

In the figure, the reference numerals of the signals on the time chart are the same as those shown in FIG. In this case, the signals on the signal line groups S ₆ and S ₇ from the scan mode register 1-5 are 2 ₍₈₎ and 4 ₍₁₆₎ , respectively. Therefore, the signal line group S
Each time the priority scanning slot value in ₁₁ changes, the line for the lines with the line numbers 0 and 1 for performing the priority scanning (in this embodiment, the priority scanning lines are set in order from the smallest number) Scan time slots are provided. On the other hand, with respect to the other used lines (line numbers 3 to 11), one line scan time slot is given every time the priority scan slot value makes one round. Therefore, unused lines (line numbers
No line scan timeslots for 12-15) are sent. In this embodiment, the scan skip lines are set in order from the oldest number. As a result, the line scan ratio between the priority scan line and the other busy lines is 4
, And line scanning for an unused line is suppressed.

In the case of this embodiment, the priority scan line numbers are set in ascending order from the smallest number, and the scan skip lines are set in descending order from the oldest number. However, the other lines can be used as the priority scan line and the scan skip line regardless of the order. For this purpose, the line numbers of the information setting circuits corresponding to the line numbers to be preferentially scanned may be set to 0 and 1, respectively, and the line numbers of the remaining mounted lines may be set to 2 to 11.

Further, in FIG. 2 (B), the line scanning time slots of the line numbers 0 and 1 for which priority scanning is performed are set at substantially equal intervals to minimize the worst line interrupt hold time at any time. This is to keep it.

Similarly, FIG. 2C is an example of a line scanning time chart when the number of priority scanning lines is one and the number of unused lines is seven. In this case, the scan mode register
The signals on the signal line groups S ₆ and S ₇ from 1-5 are 1 ₍₈₎ respectively.
And 7 ₍₁₆₎ . Therefore, each time the priority scanning slot value on the signal line group S ₁₁ changes, the line scanning time slot is given to the line of line number 0 for which the priority scanning is performed. On the other hand, other lines in use (line numbers 1 to
In contrast to 8), each time the priority scanning slot value makes one round, one line scanning time slot is given. Therefore, the line scanning time slots for the unused lines (line numbers 9 to 15) are not transmitted.

As can be seen from the above description, according to the above-described embodiment, line-by-line scanning including the priority scan line can be performed, so that the priority scan function and the scan skip function become completely independent, which results in efficient and desired operation. The line scan ratio can be obtained.

In the above-described embodiment, if the number of scan skip lines set during system generation differs from the mounted / unmounted state sensed by the microprocessor during operation, the number of scan skip lines is set as follows. That is, when the number of scan skip lines during system generation is greater than the number of actually sensed lines in the unmounted state, the actually sensed information is set in the scan mode register 1-5. Conversely, if the number is small, the number of scan skip lines set during system generation is 1-5.
Is set to.

The present invention has been described above in detail based on the embodiments. Although the line scanning ratio is set to 4 in the above embodiment, this line scanning ratio can be freely set by the number of signal line groups S ₁₁ and the configuration of the ROM 1-6. In addition, the priority scan slot value, line scan time slot number and line number unit (for example, a method of allowing two lines and allowing a maximum of one idle scan) can be freely set by the ROM1-6 configuration. Is. Further, by replacing the ROM1-6 with a RAM, the line scanning time slot can be arbitrarily set by the microprocessor.

(Effects of the Invention) As described above, according to the present invention, the following effects can be obtained.

i) Since the line scanning unit is a line unit, even if a high speed line and a low speed line are mixed on one circuit board,
Only the high speed line which should be preferentially scanned can be preferentially scanned. Also, for the same reason,
It is possible to scan only the mounted lines without being affected by the number of lines that can be accommodated in the line board, the number of line boards, and the position of the line board. It is possible to prevent unnecessary line scanning.

ii) Since the counter value for one round of line scan output from the scan counter is variable, the line scan ratio can be fixed to a desired value. As a result, useless line scanning can be prevented.

iii) Since the line scan time slot number to be scanned is determined based on the number of priority scan lines and the number of scan skip lines determined according to whether or not the lines are installed, the priority scan function and scan skip function are complete. Can operate independently.

iv) The delay of the output of the line scan time slot number is only the output delay of the scan register and does not adversely affect the scan clock cycle.

v) The mounted / unmounted lines can be sensed by a microprocessor, and scanning is performed by a common signal line group connected to all the circuit boards without providing a signal line for allocating a circuit scanning time slot for each circuit board. The number of individual signal lines can be reduced because the line scanning slot number is supplied. Specifically, 1
In the case of 6 lines and 64 lines, the number of individual signal lines may be 4 and 6, respectively.

vi) The setting of the line to be preferentially scanned can be done easily by setting the line numbers in ascending order from the smallest number to the information setting means of each line adapter and storing the number of lines to be preferentially scanned in the storage means of the line scanning circuit. This can be done and can be easily changed by changing the line number set in the information setting means. In addition, the setting of the line to be skipped can be done easily by setting the line number in the information setting unit of each line adapter in descending order from the oldest number and storing the number of lines to be skipped in the storage unit of the line scanning circuit. It can be carried out.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 (A).
~ (C) is an operation time chart of this block diagram, Fig. 3 is a block diagram of a conventional line scanning system, and Fig. 4 (A),
(B) is an operation time chart of this block diagram. 1 ... Line scanning circuit, 1-2 ... ROM, 1-3 ... Select decoder, 1-4 ... Common control circuit, 1-5 ... Scan mode register, 1-6 ... ROM, 1-7 ...... Scan register, 2-1,2-2,2-3,2-4 …… Line board, 2-a …… Select decoder, 2-b ₀ to ₃ …… Tri-state gate, 2-c ₀ ~ ₃ ... Interrupt circuit, 2-d ₀₁ ... Information setting circuit, 2-d ₀₂ ... Comparison circuit, 2-d ₀ ... ₃ ... Line adapter.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Norifumi Tasaka 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (56) Reference JP-A-57-206956 (JP, A)

Claims (1)

[Claims] 1. A communication control device comprising a plurality of line adapters for accommodating a plurality of lines and a line scanning circuit for sequentially controlling interrupt requests from the plurality of line adapters, wherein the line scanning circuit comprises: It is determined and skipped according to the number of lines obtained by setting the lines in ascending order from the lowest number to the line that scans more than other lines and performs priority scan, and the mounted and unmounted state of each line obtained from the line adapter side. The storage means for storing the number of lines obtained by setting the lines in descending order from the oldest number to the line to be scanned and not scanned, and all the line numbers to be sequentially scanned according to the scanning clock based on the information from the storage means. And a means for sending to the line adapter, each line adapter,
When the line accommodated in this is a priority scan line, it is set in ascending order from the lowest number, and when it is a scan skip line, the line number set in descending order from the oldest number, and whether the line is mounted or not mounted. Having an information setting means for storing, and a comparing means for comparing the line number output from the line scanning circuit with the line number output from the information setting means, performing priority scanning in ascending order from the smallest number, A line scanning method characterized by performing a scan skip in descending order from the old number, and permitting an interrupt from the corresponding line when both line numbers match.