JPH0748753B2 - Line control device - Google Patents

Description

The present invention relates to a line control device for sequentially scanning a plurality of lines and sequentially processing interrupt requests from the lines.

[Prior Art] FIG. 2 is a schematic configuration diagram of a communication control device. In FIG. 2, 1 is a central processing unit (hereinafter referred to as CPU), 2 is a basic unit (hereinafter referred to as CCE), 3 ₁ , 3 ₂ , ..., 3 _n are line connection units (hereinafter referred to as LU). .

The CPU 1 and the CCE 2 are connected via the interface bus 4, and the CCE 2 and each of the LU 3 ₁ , 3 ₂ , ..., 3 _n are connected in parallel via the interface bus 5.

Next, FIG. 3 is a schematic configuration diagram of the CCE2 shown in FIG. In FIG. 3, 6 is a microprocessor for controlling CCE2, 7 is a local memory (hereinafter referred to as LM) which stores line control information, and 8 is a line number register (hereinafter referred to as LNR) which stores a line number. ), 9 is an interface control unit (hereinafter referred to as INT), and 10 is a line scanning circuit (hereinafter referred to as SCAN).

Interface bus 11 between microprocessor 6 and INT9
Interface bus between INT9 and CPU1
Connected via 12. Also, the microprocessor 6
And SCAN10 are connected via the interface bus 13,
The microprocessor 6 and the LM7 are connected via a data bus 14, and the microprocessor 6 and the LM7 and LNR are further connected.
8 are connected to each other via an address bus 16.

The microprocessor 6 is composed of, for example, a high-speed microprocessor such as a bit slice microprocessor, and has a control memory (hereinafter referred to as CM) 17 in which a procedure control program that can be used for general purpose is built.

Next, FIG. 4 is a block diagram of the conventional SCAN 10 shown in FIG. The SCAN 10 is described in "Line Scanning System" (Japanese Patent Laid-Open No. 61-56547) previously filed by the applicant of the present application.

The SCAN 10 is connected with four circuit boards 22a, 22b, 22c and 22d to which four lines are respectively connected, and a software interrupt storage circuit 23. 0 for each of these lines
It is specified by the line number from No. 15 to 15.

In FIG. 4, 24 is a scan mode register and 25 is RO.
M, 26 are scan registers, 27 is a common control circuit, 31a, 31b, 3
1c, 31d are line adapters, 32a, 32b, 32c, 32d are priority encoders (hereinafter referred to as ENCs), 33a, 33b, 3
3c and 33d are interrupt circuits (hereinafter referred to as INT), 34a, 34b and 34
c and 34d are AND circuits, 41 is an address switching circuit, and 42 is an interrupt memory.

The scan mode register 24 holds the number of priority scan lines for priority scan and the number of scan skip lines for scan skip.

The priority scan is a function that scans the high-speed line more frequently than other lines and preferentially receives an interrupt request from the high-speed line.

The scan skip is a function of efficiently performing line scanning by suppressing line scanning of unused line slots.

Lines that perform priority scanning (hereinafter, lines that perform priority scanning are referred to as priority lines, and lines that do not perform priority scanning are referred to as non-priority lines) are set in ascending order from line number 0 according to the number of priority scanning lines. For example, if the number of priority scan lines is set to 2, the lines with line numbers 0 and 1 will be the priority lines.

Lines for which scan skip is performed (hereinafter referred to as scan skip lines) are set in descending order from line number 15 according to the number of scan skip lines. For example, when the number of scan skip lines is set to 4, the lines with line numbers 15, 14, 13 and 12 are scan skip lines.

The number of priority scan lines and the number of scan skip lines are the number of priority scan lines and the number of scan skip lines set in the memory (not shown) at the time of system generation, and the mounting of each line detected by the microprocessor (not shown),
It is set in the scan mode register 24 according to the unmounted state.

The ROM 25 stores the signal line groups S ₆ and S from the scan mode register 24.
_The number of priority scan lines and the number of scan skip lines input via ₇ and the signal line group S from the scan register 25.
_{Based on the} number of priority scan slots and line scan time slot number (line number for line scan) input via ₁₁ and S ₉ , specify the priority scan slot value that specifies the line scan ratio and the line number for line scan. Outputs the indicated line scan time slot number.

The line scan ratio indicates how many times the line scan time slot is assigned to the priority line while the line scan time slot is assigned once to the non-priority line.

For example, when the line scan ratio is 4, the line scan time slot is assigned to the priority line four times while the line scan time slot is assigned to the non-priority line once.

When the line scanning ratio is 4, the priority scanning time slot value of the signal line group S ₁₁ is 0 to 1 while scanning all lines once,
It changes like a few. The priority line is scanned every time the priority scanning time slot value changes. Therefore, the priority line is scanned four times and the non-priority line is scanned once during one round of line scanning.

The scan register 26 samples the priority scan slot value and line scan slot number output from the ROM 25 in accordance with the scan clock output from the common control circuit 27, and outputs the signal line group S ₈
And S ₁₁ output the line scan time slot number and the priority scan slot number.

Signal line group S from which line scan time slot number is output
_8, corresponding to the Max line number 16 lines of SCAN10, and a respective 2 ^3, 2 ^2, 2 ^1, 2 ⁰ 4 signal lines weighted is the. Therefore, the line numbers 0 to 15 can be represented by the signals output from the signal line group S ₈ .

The line adapter 31a has an information setting circuit 35 and a comparison circuit 36. The information setting circuit 35 outputs the line number 0 assigned to itself to the signal line group S ₁ and outputs the mounted / unmounted state of the line to the signal line S ₁₀ . Further, the comparison circuit 36 is enabled when the mounting state is output to the signal line S ₁₀ , and the line number of its own output to the signal line group S ₉ and the line scanning time slot number output to the signal line S ₈ . comparing the door, both numbers to output a signal line S _a interrupt enable signal to match.

The other line adapters 31b~31d are also similarly information setting circuit and the comparison circuit and the line adapter 31a is provided, the signal line S _b, S _c, and outputs the interrupt enable signal to the S _d.

The ENC 32a outputs the interrupt code with the highest priority among the interrupt codes (interrupt request) IPT ₀₁ , IPT ₀₂ , ..., IPT _0n from the line (not shown) with the line number 0. ENC32b ~
32d has the same configuration.

Each of the AND circuits 34a to 34d outputs a common control circuit when an interrupt code is output while the interrupt enable signal is being output.
The interrupt code is output to 27.

Next, the operation of the conventional SCAN 10 will be described with reference to the timing charts of FIGS. 5 and 6.

First, the operation when the number of priority lines is 0 and the number of unused lines is 0, that is, when all 16 lines are mounted will be described with reference to FIG.

When both the number of priority lines and the number of unused lines are 0, the scan mode register 24 outputs 0 to the signal line groups S ₆ and S ₇ . Therefore, the scan register 26 sequentially outputs line scan time slot numbers in accordance with the scan clock to perform line scan.

Also, since the number of priority lines is 0, one line scan time slot number is assigned to each line adapter until the number of priority scan slots changes from 0 to 1, 2, 3 and becomes 0 again. Will be given.

The line scanning time slot number is compared with the line number stored in the information setting circuit of each line, and only the line adapter having the same line number is granted the interrupt request right. For example, the line adapter 31a has a comparison circuit 36
Compares the line scanning time slot number with the line number of the information setting circuit 35, and outputs an interrupt permission signal when the line numbers match.

Interrupt control signal output by interrupt enable signal
It is output to 27. Further, the common control circuit 27 outputs an interrupt request to the microprocessor 6, and the microprocessor 6 executes the interrupt processing.

Next, the operation when the number of priority lines is 2, the number of unused lines is 4, that is, when the number of accommodated lines is 12 will be described with reference to the timing chart of FIG.

When the number of priority lines is 2 and the number of skip lines is 4, the scan mode register 24 outputs 2 and 15 to the signal line groups S ₆ and S ₇ .

Therefore, the line scan time slot number is output to the priority lines (lines with line numbers 0 and 1) every time the number of priority scan slots changes. For non-priority lines (lines with line numbers 3 to 11), the line scan time is changed only once before the number of priority scan slots changes from 0 to 1, 2, and 3 and becomes 0 again. The slot number will be output. Furthermore, the line scan time slot numbers are not output to the scan skip lines (lines with line numbers 12 to 15). As a result, the line scan ratio becomes 4, and the line scan for the scan skip line is suppressed.

When the above-mentioned interrupt request is output, as shown in the flowchart of FIG. 7, the microprocessor 6 reads an interrupt code indicating the type of interrupt request, and interrupt codes 0, 1,
..., the process according to n is performed.

By the way, in the multi-line control, since it is necessary to execute the interrupt process from each line within a predetermined time, there is a restriction on the processing time for one time. Therefore, a process that requires a long processing time is executed as a split interrupt process. That is, the split interrupt process is composed of a process executed by an interrupt request from the line and a process executed by a software interrupt request.

FIG. 8 is a flow chart showing the operation of the microprocessor 6 when executing the divided interrupt processing.

(1) When the common control circuit 27 detects the interrupt request IPT ₀₁ from the line 0 by the line scan, it stops the output of the scanning clock to suppress the line scan and outputs the interrupt code to the microprocessor 6.

(2) The interrupt code of the microprocessor 6 is read, and the execution of the process B ₁ corresponding to the interrupt request from the line 0 is started. When the execution of the process B ₁ is completed, the microprocessor 6 accesses the interrupt memory 42 with the line number 0 as an address through the address switching circuit 41 and sets the corresponding bit. This is done by executing a software interrupt set instruction.

(3) When the microprocessor 6 completes the process B ₁ , SC
AN10 starts the line scan again. During the line scan, the address switching circuit 41 outputs the line scan time slot number output from the scan register 26 as the address of the interrupt memory 42. Therefore, when the line with the line number 0 is scanned, the software interrupt request stored in the interrupt memory 42 is output to the ENCs 32a to 32d. Since the software interrupt request has the highest priority, the common control circuit 27 detects this.

(4) When the common control circuit 27 detects the software interrupt request, it stops the output of the scan clock to suppress the line scan and outputs the interrupt code to the microprocessor 6.

The microprocessor 6 reads the interrupt code, recognizes that it is a software interrupt request, and executes the process B ₂ .

(5) When the process B ₂ is completed, the microprocessor 6 accesses the interrupt memory 42 with the line number 0 as an address through the address switching circuit 41 and resets the corresponding bit. This is done by executing a software interrupt reset instruction.

In addition, the interrupt process is divided into more divided interrupt processes B ₁ , B ₂ ,
.., B _n , this bit remains set until the processing of the division interrupt processing B _n is completed.

[Problems to be Solved by the Invention] By the way, as described above, in the split interrupt process, the process B ₁ is executed by the first interrupt, and the process B ₂ is executed by the _second interrupt. In this case, a new interrupt request may be output from the line with line number 0 during the execution of the split interrupt process. Software interrupt is set to the highest priority for interrupt requests IPT _{01 to} IPT _0n from the line. Therefore, a new interrupt request from the line cannot be accepted until the division interrupt process by the software interrupt is completed.

However, if the processing corresponding to the read / write processing request for the transmission / reception data to the line control LSI is made to wait, there is a problem that overrun or underrun may occur during high traffic.

The present invention has been made to solve the above problems,
An object of the present invention is to provide a line control device capable of accepting a new process request from a line even when executing an interrupt process by software interrupt.

[Means for Solving the Problem] A line control device according to the present invention is directed to a first process executed by output of a line interrupt request and a software interrupt request output after completion of execution of the first process. A plurality of interrupt requests from a line including a divided interrupt process composed of a second process executed by output and corresponding to a plurality of processes each having a priority set are output by a line scan. In a line controller having interrupt request output means and interrupt processing execution means for executing processing corresponding to the interrupt request, a priority setting for setting the priority of the second processing corresponding to the software interrupt request. Means for determining whether there is an interrupt request from the line when the software interrupt request is output by the line scan, and determines that there is an interrupt request from the line. When it is determined, the priority of the third processing executed by the output of the interrupt request from the line is compared with the priority of the second processing, and if the priority of the third processing is high, the The interrupt processing execution means is given priority to execute the third processing, and if the priority of the second processing is high, the second processing is executed by the interrupt processing execution means, and an interrupt request from the line is issued. And processing control means for causing the interrupt processing execution means to execute the second processing when it is determined to be absent.

[Operation] In the line control device having the above configuration, when the interrupt request output means outputs an interrupt request by a line scan, the interrupt process execution means executes the process corresponding to the interrupt request. When the split interrupt process is executed by the interrupt request, a software interrupt request is output. At this time, the priority setting means sets the priority of the process corresponding to the software interrupt request. Furthermore, if a software interrupt request is output by a line scan, it is determined whether there is an interrupt request from the line, and if it is determined that there is an interrupt request from the line, it is executed by outputting an interrupt request from the line. The priority of the third process and the priority of the second process are compared, and if the priority of the third process is high, the third process is prioritized to be executed by the interrupt process executing means, and the second process is executed. If the priority of the processing is high, the second processing is executed by the interruption processing execution means, and if it is judged that there is no interruption request from the line, the second processing is executed by the interruption processing execution means.

[Embodiment] An embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a block diagram of a line control device according to an embodiment of the present invention.

Incidentally, in FIG. 1, parts having the same functions as those in FIG. 4 are designated by the same reference numerals, and the description thereof will be omitted.
Further, in FIG. 1, 61 is a CPU, 62 is a memory, and 63 is an interface.

The memory 62 is a software interrupt request setting program 64 that sets and sets a software interrupt request in the divided interrupt processing, a priority setting program 65 that sets the priority of processing executed by the software interrupt request, and a line scan. When an interrupt request and a software interrupt request from the line are output, the comparison program 66 for executing the process with the higher priority is stored.

Next, the operation of the line controller shown in FIG. 1 will be described with reference to the flowchart of FIG.

In the flowchart of FIG. 9, the divided interrupt process B is processed as processes B ₁ and B _2.
It shows the operation when an interrupt request of the process A having a higher priority than the process B ₂ is output during the processing divided into and.

Process B ₁ is a process executed by an interrupt request from the line, and process B ₂ is a process executed by a software interrupt request.

(1) When the common control circuit 27 detects the interrupt request IPT ₀₁ from the line 0 by the line scan, it stops the output of the scanning clock to suppress the line scan and outputs the interrupt request to the microprocessor 6. The microprocessor 6 reads the interrupt code and starts execution of the process B ₁ corresponding to the interrupt request from the line 0.

When the microprocessor 6 finishes executing the process B ₁ , the priority of the process to be executed next, that is, the process B ₂ is set to LM7.
(See FIG. 3) to generate a software interrupt request.

(3) When the microprocessor 6 finishes executing the process B ₁ , the SCAN 10 starts the line scan again. During line scanning, the address switching circuit 41 operates as a scan register.
Interrupt memory for line scan time slot number output by 26
Output as 42 address.

When the line with the line number 0 is scanned, the software interrupt request stored in the interrupt memory 42 is output to the ENC 32a. In this case, even if the line with the line number 0 outputs the high-level interrupt request IPT ₀₁ , the priority encoder 32a outputs the software interrupt request code.

The high-level interrupt request means 1 from the line control LSI.
If it is a character transmission / reception completion interrupt or the like and the interrupt processing in response to a high-level interrupt request is not performed within a certain period of time, a line error occurs. Especially in high-speed lines, if you do not process in a short time, overruns on the line,
Underrun occurs.

When the common control circuit 27 detects the software interrupt request,
The output of the scan clock is stopped to suppress the line scan, and an interrupt request is output to the microprocessor 6.

When executing the process corresponding to the software interrupt request, the microprocessor 6 determines whether or not there is an interrupt request from the line. Determination of interrupt requests whether from the line, for example temporarily resets the appropriate bit in the interrupt memory 42, while releasing the software interrupt request can be realized by reading the output of the re ENC32 _a.

Since the microprocessor 6 outputs the interrupt request from the line, it compares the priority of the process A corresponding to the interrupt request with the priority of the process B ₂ corresponding to the software interrupt request stored in the LM7. . Since the microprocessor 6 priority process A is higher than the priority of the process B _2, it executes the process A as the second processing.

When the microprocessor 6 finishes executing the process A, SC
AN10 scans the line again. Since there is no new interrupt request from the line, the microprocessor 6 executes the process B ₂ as the third process.

[Effects of the Invention] As described above, according to the present invention, the priority of the software interrupt request is set in accordance with the execution of the divided interrupt processing, and when the software interrupt request is output, the interrupt from the line is issued. Whether or not there is an interrupt request is determined, and when it is determined that there is an interrupt request from the line, the priority of the process executed by the output of the interrupt request from the line and the priority of the process of the software interrupt request are compared. If the priority of the interrupt request from the line is high, the interrupt request from the line is processed with priority, and if the priority of the software interrupt request is high, the software interrupt request is processed. When it is determined that there is no interrupt request from the software, the software interrupt request processing is executed. The effect of being able to obtain an arrangement is obtained.

[Brief description of drawings]

1 is a block diagram of a line control device according to an embodiment of the present invention, FIG. 2 is a schematic configuration diagram of a communication control device, FIG. 3 is a schematic configuration diagram of the basic unit shown in FIG. 2, and FIG. FIG. 5 is a schematic configuration diagram of a conventional line control device, and FIGS. 5 and 6 are second diagrams.
Timing charts showing the operation of the conventional line controller shown in the figure, FIGS. 7 and 8 are flowcharts of the split interrupt processing by the conventional line controller, and FIG. 9 is the line controller shown in FIG. 3 is a flowchart showing the operation of FIG. 10 …… Line scanning circuit (SCAN), 22a, 22b, 22c, 22d ……
Circuit board, 23 ... Software interrupt storage circuit, 24 ... Scan mode register, 25 ... ROM, 26 ... Scan register, 27 ... Common control circuit, 31a, 31b, 31c, 31d ... Line adapter, 32a , 32b, 32c, 32d ... Priority encoder, 33a, 33b, 33c, 33d ... Interrupt circuit, 34a, 34b,
34c, 34d …… AND circuit, 35 …… information setting circuit, 36 …… comparison circuit, 41 …… address switching circuit, 42 …… interrupt memory,
61 …… CPU, 62 …… Memory, 63 …… Interface, 6
4 …… Software interrupt request setting program, 65 …… Priority setting program, 66 …… Comparison program.

Claims (1)

[Claims] 1. A first method executed by outputting a line interrupt request.
And a divided interrupt process composed of a second process executed by the output of the software interrupt request output after the execution of the first process, and a plurality of priorities are set. In a line control device having a plurality of interrupt request output means for outputting an interrupt request from a line corresponding to each process by a line scan, and an interrupt process execution means for executing a process corresponding to the interrupt request A priority setting means for setting the priority of the second processing corresponding to the software interrupt request; and, if the software interrupt request is output by the line scan, it is judged whether or not there is an interrupt request from the line, When it is determined that there is an interrupt request from the above, the priority of the third process executed by the output of the interrupt request from the line and the previous By comparing the priority of the second process,
If the priority of the third process is high, the third process is prioritized to be executed by the interrupt process execution means, and if the priority of the second process is high, the second process is executed. And a processing control means for causing the interruption processing execution means to execute the second processing when it is determined that there is no interruption request from the line. .