JPH0658686B2 - Image processing device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an image processing apparatus that performs spatial filtering processing used for image quality improvement, cooperation, noise removal, feature extraction, and the like.

[Technical Background of the Invention and its Problems] In general, for a digital image X that is composed of a two-dimensional area of N pixels in the horizontal direction and M pixels in the vertical direction, (2K +
The processed image Y after applying the spatial filter by 1) × (2L-1) matrisk can be expressed by the following equation.

Where Xi, j; original image Yi, j; processed image (i = 0,1, ..., Nj = 0,1, ..., M) Ck, l; filter coefficient (k = -K, -K + 1, ...) 0, ..., K1 = -L, -L + 1, ... 0, ..., L) In the above formula (1), by setting the value of the filter coefficient Ck, l to a predetermined value, a high-pass filter, a low-pass filter or a band-pass filter can be obtained. Any form of filter can be realized.

However, to apply the desired filter (1)
In the equation, it is necessary to select the values K and L that determine the size of the filter. For example, when K = 1 and L = 1 are selected, a filter having a size of 3 × 3 is formed, but with this size, it is difficult to construct a filter having a sharp shoulder characteristic on the spatial frequency. Therefore, in order to obtain steep characteristics, a filter having a size of 7 × 7 or 9 × 9 is required. On the other hand, if the characteristic is not so steep, the characteristic of 3 × 3 is sufficient.

In this way, in order to apply the space filter properly and efficiently, it is desirable to have a structure in which the values of K and L in the equation (1) can be selected, and the values of the filter coefficient Ck, l are also different. It is desirable to be able to set arbitrarily for each image.

Conventionally, the variable size of the filter and the selection of the filter coefficient Ck, l are performed by software, so that there is a drawback in that the calculation takes time.

[Object of the Invention]

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an image processing apparatus capable of shortening the time required for calculation by performing spatial filtering on an image by hardware. is there.

[Outline of Invention]

The outline of the present invention for achieving the above object is an image processing apparatus that performs spatial filtering by an n × m matrix on an original image in which a plurality of pixels are arranged in a matrix by a process of n × m steps. The steps are updated by changing the bias address signal that is determined corresponding to the first storage means that stores the image, the second storage means that stores the processed image for each step, and the step. In each step, the steady address signal is sequentially changed corresponding to the pixel position to be read, and the effective address obtained by adding the bias address signal to the steady address signal is stored in the first recording means. It is common to perform the read control by moving the original image in parallel in the direction corresponding to the bias address by the number of pixels corresponding to the bias address. A control means for controlling reading and writing of the second storage means by the steady address signal; and, for each step, the original image data read from the first storage means, and the bias address of an n × m matrix. And a hydrochloric acid means for multiplying the signal by a filter coefficient corresponding to the signal, adding the signal to the processed image written in the previous step read from the second storage means, and outputting the result to the second storage means. It is characterized by. In this way, if the method of moving the original image itself in parallel and performing each processing is adopted, the method of performing each processing in parallel with the segment has to be stored once for each processing step. It is possible to solve the problem that the read / write operation or the circuit and its processing are complicated.

Example of Invention

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment in which the image processing apparatus according to the present invention is applied to an X-ray diagnostic apparatus.

In FIG. 1, the X-ray generated from the X-ray tube 1 is transmitted through the subject A and then converted into an electric signal by the II-image pickup tube system 2. The A / D converter 3 digitally converts the electric signal and outputs it. The A / D converter 3 can input not only signals from the I / I imaging system 2 but also signals read from the image storage unit 9 such as VDR, VTR, and DISK. The signal analog-digital converted by the A / D converter 3 is stored for each pixel in one frame memory of the frame memory group 7. The frame memory group 7 is composed of a plurality of frame memories having the same configuration as described later in detail. The frame memory for storing the original image is the first storage means 7a, and the calculation result of the calculation means 8 described later is stored in the frame memory group 7. The frame memory to be stored will be referred to as second storage means 7b. First
Storage means 7a is composed of frame memories 7-1, 7-2 ... And second storage means 7b is composed of a first working memory 7-W ₁ and a second working memory 7-W ₂ . .

Next, the structure of the frame memory group 7 will be described with reference to FIG. FIG. 2 is a schematic explanatory view showing the structure of one of the frame memories 7 such as the frame memory 7-1.
In FIG. 2, the frame memory 7-1 includes a memory chip 24, adder circuits 16 and 17 for adding horizontal and vertical address signals, respectively, which will be described later, and a selector 23 for selecting one of two systems of input data 22. It comprises an output buffer 25 which outputs one or both of two output data 26.

A constant address signal 10 for designating an address in the horizontal direction of an image is input to the adder circuit 16. The adder circuit 16 has a bias address signal 1
A bias address circuit 14a for inputting 2 and a bias enable signal that negates this is provided. When the bias enable signal 15 is input,
The stationary address signal 10 is output as an effective address signal 18 from the adder circuit 16. When the bias enable signal 15 is not input, the stationary address signal 10 and the bias address signal 12 are added, and the added value is output as the effective address signal 18.

The adder circuit 17 is provided with an effective address 1 in the vertical direction of the image.
9, a bias address circuit 14b having a function similar to that of the adder circuit 16 is provided, and a vertical stationary address signal 11 and a bias address signal 13 as input signals and a bias enable signal for negating the same. It is designed to input 15. Further, the frame memory 7-1 is adapted to receive a write command signal 20 and a read command signal 21 for instructing writing and reading of pixel data. The write command signal 20 is
The read command signal 21 issues a command to select and write one of the two systems of inputs 22 input to the selector 23, and the read command signal 21 issues a command to read one or both of the two systems of output from the output buffer 25. The stationary address signals 10 and 11 and the bias address signals 12 and 1
3, the bias enable signal 15 and the write / read command signals 20 and 21 are output from the controller 4 (see FIG. 1) as the control means.

Next, the configuration of the calculating means 8 will be described with reference to FIG.

In FIG. 3, the calculating means 8 is a two-system input line 27.
Buffer 2 for inputting data via -1, 27-2
8, 28 and a register 29 for accumulating operation parameters (details will be described later) and outputting predetermined operation parameters based on a control signal from the controller 4 input via a control line 30. It comprises an arithmetic unit 31 which outputs output data 32.

The arithmetic unit 31 is adapted to perform the following arithmetic operations.

y = (A ₁ x ₁ + B ₁ ) + (A ₂ x ₂ + B ₂ ) ... (2) In the equation (2), x ₁ and x ₂ are input lines 27-1 and 27-.
Shows the data of 2 lines respectively input via 2.
A ₁ , B ₁ , A ₁ , and B ₂ represent the calculation parameters, respectively.
The calculation result y is output from the calculation means 8 as the output data 32 and stored in the second storage means 7b.

The operation of the image processing apparatus configured as above will be described.

As an example, 512 (pixels) × 512 (pixels)
Applying a low-pass filter to one image will be described. The low pass filter is applied to a 3 × 3 area, and if this is expressed in the form of the above equation (1), Becomes Where the filter coefficient Ck, l is Shall be given.

In the above formula (3), the pixel data Xi, j of an arbitrary pixel
Pixel data of surrounding pixels used for spatial filtering
The relationship between Xi-k, jl and the corresponding filter coefficient Ck, l is as shown in FIG.

First, based on the write command signal 20 from the controller 4, the original image X including a plurality of pixel data to be processed is stored in the frame memory 7-1 for each pixel. Next, the original image X is read from the frame memory 7-1 and the calculation means 8 performs the calculation. At this time, in order to obtain the ^first processed image Y ¹ i, j corresponding to the address (i, j) from the frame memory 7-1, the pixel of the pixel obtained by moving the address in parallel by 1 pixel to the right is obtained. Data Xi ＋
Read 1, j. This operation is performed by the horizontal and vertical stationary address signals 10 and 11 from the controller 4.
To specify the address (i, j), and the bias address signals 12 and 13 to specify the parallel displacement of one pixel to the right. In addition, at the time of this reading,
The bias enable signal 15 is not input.

The above reading is performed for all the pixels of the frame memory 7-1. That is, the pixel data for one frame of the image is read out by sequentially changing the pixel address corresponding to the pixel position where the stationary address is read out. This is calculated through the one input line 27-1 in the calculating means 8
To enter. The computing means 8 uses the pixel data Xi + 1, j as x ₁ in the equation (2) to perform the computation of the equation (2).
Here, the calculation parameters A ₁ , B ₁ , A ₂ , B ₂ are set as follows via the control line 30 from the control 4.

A ₁ = C _-1,0 = 0.1, B ₁ = A ₂ = B ₂ = 0 Therefore, as the first processed image Y ¹ i + j output from the calculating means 8, Y ¹ i, j = Xi + 1, We can get j · C _-1,0 .

The output of the computing means 8 is the first working memory 7-
Written to W ₁ . The address designation at the time of writing is performed by the address signals 10 and 11 and the bias address signal 1 used for reading the frame memory 7-1.
2 and 13 are used, the bias signals 12 and 13 are input by inputting the bias enable signal 15 at the same time.
Is denied, and the address signals 10 and 11 are eventually used as the effective address signals 18 and 19 as they are.

The above operation completes the first step. At the end of the first step, the first working memory stores the pixel data for one frame for which the processing in the first step has been completed.

Next, the second step will be described. In the second step, the original image X stored in the frame memory 7-1 is read out by shifting it horizontally by 1 pixel to the left,
It is input to the calculating means 8 from one input line 27-1.
Further, the preceding processed pixel stored in the working memory 7-W ₁ is read out without shifting the address position, and is input to the calculating means 8 through the other input line 27-2. When reading both images, the same address signals 10 and 1 are used.
Using the first bias address signals 12 and 13, and the bias enable signal 1 only in the working memory 7-W ₁
5 is input to negate the bias address signals 12 and 13.

The calculation means 8 carries out the calculation of the equation (2). Here, the calculation parameters A ₁ , B ₁ , A ₁ , B ₂ are given by the signal from the controller 4 as follows.

Therefore, the calculation means 8 performs the following calculation in order to obtain the ^second processed image Y ² i, j.

Y ² i, j = (Xi + 1, _{jC -1,0} ) + C _1,0Xi -1, j Then, the second processed image is written in the _second working memory 7-W ₂ . Incidentally, in advance to erase the first contents of the working memory 7-W ₂ therebetween.

Next, in the third step, the frame memory 7-1
The original image X stored in 1 is vertically shifted by 1 pixel and read out, and is input to the calculating means 8 through one input line 27-1. Furthermore, the second working memory 7
The operation result of the second step stored in -W ₂ is read out without shifting the address position, and the other input line 27
-2 is input to the calculating means 8. Addressing at the time of reading is performed in the same manner as the second step. or,
The hydrochloric acid parameters A ₁ , B ₁ , A ₂ , B ₂ are determined by the controller 4 as follows.

Therefore, the calculation means 8 performs the following calculation to obtain the ^third processed image Y ³ i, j.

^{Y 3 i, j = Xi,} j-1 · C 0, -1 + Y 2 i, j then the third processed image Y ³ i, j is stored in the first working memory 7-W _1.

In the same manner, the fourth to ninth steps shown in the following table are executed in the same manner to perform the spatial filtering of the 3 × 3 area.

The tenth step shown in the table is a step for writing the calculation result of the ninth step in the frame memory 7-1. In this case, the original image X is destroyed.

As described above, when the filter of the 3 × 3 area can be written, the calculation of the equation (3) can be completed in 9 frames. Similarly, a filter for a 5 × 5 area requires 25 frames, which is generally (2K + 1) × (2
To apply a filter in the (L + 1) area, use (2K +
Calculation can be performed in 1) × (2L + 1) frames. In the present embodiment, the case where filtering is performed on the images stored in the frame memory 7-1 has been described, but similarly, the frame memories 7-2, 7-3 ... You can also apply space filters one by one. When the number of target images is m (2K + 1) ×
If the filter of the area of (2L-1) is applied, the required calculation time is m * (2K + 1) * (2L + 1) frame time.

It is needless to say that the present invention is not limited to the above-mentioned embodiments and includes various modifications within the scope of the gist of the present invention. In the above embodiment, the two working memory 7-W ₁ the operation result of the operation unit 8, 7-W ₂ in is written alternately were line summer, timing Torere if one memory of the erasing and writing of stored content It can be done by means.

〔The invention's effect〕

As described above, according to the present invention, it is possible to provide an image processing apparatus which is excellent in versatility and has a high processing speed, without complicating the circuit and its processing required for the writing / reading operation of the storage unit.

[Brief description of drawings]

FIG. 1 is a block diagram of an X-ray diagnostic apparatus to which an image processing apparatus according to an embodiment of the present invention is applied, FIG. 2 is a schematic explanatory view showing one frame memory of a frame memory group 7, and FIG. Fourth, schematic explanatory view showing details of the means 8.
The figure is an explanatory diagram showing the relationship between each pixel and the filter coefficient when a filter is applied to a 3 × 3 area. 4 ... control means, 7a ... first storage means, 7b ... second
Storage means, 8 ... Calculation means.

Claims (1)

[Claims] 1. An image processing apparatus for performing spatial filtering by an n × m matrix on an original image in which a plurality of pixels are arranged in a matrix by a process of n × m steps, the first storage storing the original image. Means, a second storage means for storing a processed image for each step, and the step is updated by changing the bias address signal determined in correspondence with the step. Corresponding to the pixel position to be read, and the effective address obtained by adding the bias address signal to the stationary address signal corresponds the original image stored in the first storage means to the bias address. In parallel with the bias address, the number of pixels corresponding to the bias address is moved in parallel for read control, and Therefore, the control means for controlling the reading and writing of the second storage means, and the filter coefficient corresponding to the bias address signal of the n × m matrix in the original image data read from the first storage means at each step. And an arithmetic means for multiplying by and adding it to the processed image written in the previous step read from the second storage means and outputting the result to the second storage means. apparatus.