JPH0658910B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0658910B2 JPH0658910B2 JP59167886A JP16788684A JPH0658910B2 JP H0658910 B2 JPH0658910 B2 JP H0658910B2 JP 59167886 A JP59167886 A JP 59167886A JP 16788684 A JP16788684 A JP 16788684A JP H0658910 B2 JPH0658910 B2 JP H0658910B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon oxide
- oxide film
- semiconductor device
- thickness
- junction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W42/00—Arrangements for protection of devices
- H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/113—Isolations within a component, i.e. internal isolations
- H10D62/115—Dielectric isolations, e.g. air gaps
Landscapes
- Bipolar Transistors (AREA)
- Formation Of Insulating Films (AREA)
Description
【発明の詳細な説明】 (産業上の利用分野) 本発明は半導体装置詳しくは、放射線環境における特性
劣化を低減した半導体装置に関するものである。The present invention relates to a semiconductor device, and more particularly to a semiconductor device with reduced characteristic deterioration in a radiation environment.
(従来技術) 従来の半導体装置は、第2図に示すように、半導体表面
の保護用として1μm程度の厚さの酸化膜2及び素子を
分離するための1μm程度の厚さのシリコン酸化膜3を
有しているのが一般的である。(Prior Art) As shown in FIG. 2, a conventional semiconductor device has an oxide film 2 having a thickness of about 1 μm for protecting a semiconductor surface and a silicon oxide film 3 having a thickness of about 1 μm for separating elements. It is common to have
(発明が解決しようとする問題点) 叙上のような構造では、放射線環境、とりわけα線等の
重粒子、電子線γ線による放射線照射をされると、シリ
コン酸化膜2,3内に電子正孔対が発生し、移動度が電
子に比べて100万分の1と小さい正孔が、半導体基板1
とシリコン酸化膜2,3との界面付近に存在している正
孔トラツプに捕促されやすく、また、その正孔の発生量
はシリコン酸化膜の厚さに比例する。しかして正孔トラ
ツプに捕促された正孔は、半導体基板1の表面をよりN
形化し、例えばP形半導体基板では、第2図に示す半導
体基板1に形成されたNPNパイボーラトランジスタにお
いて、P形のベース領域6と接するシリコン酸化膜2と
の界面が反転し、リーク電流の増加及び直流電流増幅率
の低下が生ずる欠点があつた。また、第2図に示すよう
に隣接するトランジスタを分離するシリコン酸化膜3が
例えばP形半導体基板では、半導体基板1とシリコン酸
化膜3との界面をパスとして導通状態となり、素子間分
離が不可能となる欠点があつた。そこでシリコン酸化膜
2,3内で発生する正孔の量を減少させるために、シリ
コン酸化膜を薄くすることを考える。素子間分離用シリ
コン酸化膜3の場合には配線4と半導体基板1との容量
が増し、動作速度が低下し、また電気的に分離が低下す
る欠点があつた。また、バイポーラトランジスタの表面
保護膜としてのシリコン酸化膜2の場合には、シリコン
酸化膜はベース6あるいはエミツタ5を形成する時のド
ープ材のマスクとして使用されるため、シリコン酸化膜
の厚さは主にマスクとしての効果という観点から決定さ
れており、深い接合を有するトランジスタほどシリコン
酸化膜厚は大きくなつている。このためシリコン酸化膜
を薄くするためには、従来トランジスタの活性領域上の
シリコン酸化膜2を取りさつたのち20nm以下の膜厚に
再度形成する方法がなされているが、この方法によると
半導体基板表面が表われていることから、表面の汚染に
伴うリーク電流が発生する欠点があつた。(Problems to be Solved by the Invention) In the above structure, when the radiation environment, particularly heavy particles such as α-rays, and electron rays γ-rays are irradiated, the electrons are emitted in the silicon oxide films 2 and 3. Hole pairs are generated, and the mobility of which is smaller than that of electrons, which is one millionth, is smaller than that of electrons.
Are easily trapped by the hole traps existing near the interface between the silicon oxide films 2 and 3, and the amount of generated holes is proportional to the thickness of the silicon oxide film. Then, the holes trapped by the hole traps are more likely to be absorbed on the surface of the semiconductor substrate 1 by N.
For example, in the case of a P-type semiconductor substrate, the interface between the P-type base region 6 and the silicon oxide film 2 in contact with the NPN pyramidal transistor formed on the semiconductor substrate 1 shown in FIG. There is a drawback in that the increase and the decrease in the direct current amplification factor occur. Further, as shown in FIG. 2, in the case where the silicon oxide film 3 for separating the adjacent transistors is, for example, a P-type semiconductor substrate, the interface between the semiconductor substrate 1 and the silicon oxide film 3 is used as a path to establish a conduction state, and isolation between elements is not achieved. There was a possible drawback. Therefore, in order to reduce the amount of holes generated in the silicon oxide films 2 and 3, it is considered to thin the silicon oxide film. In the case of the element isolation silicon oxide film 3, there are drawbacks that the capacitance between the wiring 4 and the semiconductor substrate 1 increases, the operating speed decreases, and the electrical isolation decreases. Further, in the case of the silicon oxide film 2 as the surface protection film of the bipolar transistor, the silicon oxide film is used as a mask of the doping material when the base 6 or the emitter 5 is formed. It is mainly determined from the viewpoint of the effect as a mask, and the transistor having a deeper junction has a larger silicon oxide film thickness. Therefore, in order to reduce the thickness of the silicon oxide film, a conventional method is to remove the silicon oxide film 2 on the active region of the transistor and then re-form it to a film thickness of 20 nm or less. Since the surface is exposed, there is a drawback that a leak current is generated due to contamination of the surface.
(問題点を解決するための手段) 本発明は上記の欠点を改善するために提案されたもの
で、放射線環境においても、特定の劣化することを低減
した半導体装置を提供することを目的とする。(Means for Solving Problems) The present invention has been proposed in order to improve the above-mentioned drawbacks, and an object of the present invention is to provide a semiconductor device in which specific deterioration is reduced even in a radiation environment. .
上記の目的を達成するため、本発明はシリコン酸化膜に
より半導体表面を保護するバイポーラトランジスタを有
する半導体装置において、少くともエミツタ・ベースと
の間の接合部付近及びベース・コレクタとの間の接合部
付近に形成されているシリコン酸化膜の厚さを20nm以
下とすることを特徴とする半導体装置を発明の要旨とす
るものである。In order to achieve the above object, the present invention provides a semiconductor device having a bipolar transistor which protects a semiconductor surface with a silicon oxide film, in a semiconductor device having at least a junction with an emitter base and a junction with a base collector. The gist of the invention is a semiconductor device characterized in that the thickness of a silicon oxide film formed in the vicinity thereof is 20 nm or less.
さらに本発明はシリコン酸化膜により素子間分離を行つ
た半導体装置において、素子間分離用シリコン酸化膜に
囲まれた素子と、前記の素子間分離用シリコン酸化膜と
の間の接合部付近に形成されているシリコン酸化膜の厚
さを20nm以下とすることを特徴とする半導体装置を発
明の要旨とするものである。Further, according to the present invention, in a semiconductor device in which an element isolation is performed by a silicon oxide film, it is formed near a junction between an element surrounded by an element isolation silicon oxide film and the element isolation silicon oxide film. The gist of the invention is a semiconductor device characterized in that the thickness of the formed silicon oxide film is 20 nm or less.
次に本発明の実施例を説明する。なお実施例は一つの例
示であつて、本発明の精神を逸脱しない範囲で、種々の
変更あるいは改良を行いうることは云うまでもない。Next, examples of the present invention will be described. It is needless to say that the embodiment is merely an example, and various modifications and improvements can be made without departing from the spirit of the present invention.
次に実施例について説明する。Next, examples will be described.
第1図は本発明の実施例であつて、図において11は半
導体基板、12,22,13はシリコン酸化膜、14は
配線金属、15はエミツタ領域、16はベース領域、1
7はコレクタ領域である。本発明においてはエミツタ領
域15とベース領域16との接合部付近のシリコン酸化
膜22,ベース領域16とコレクタ領域17との接合部
付近のシリコン酸化膜22,コレクタ領域17と半導体
基板11との接合部付近のシリコン酸化膜22及び素子
間分離用シリコン酸化膜13に囲まれた素子と、前記の
素子間分離用シリコン酸化膜13との間の接合部付近に
形成されているシリコン酸化膜22の厚さを20nm以下
としている点に特徴がある。これにより放射線照射の影
響を低減するものである。この場合シリコン酸化膜の厚
さが20nmを超えた場合、放射線照射により直流電流増
巾率の低下がいちじるしい。又酸化膜の厚さが5nm以
下のきわめてうすい場合は半導体装置に対する保護効果
が少いものである。FIG. 1 shows an embodiment of the present invention, in which 11 is a semiconductor substrate, 12, 22 and 13 are silicon oxide films, 14 is a wiring metal, 15 is an emitter region, 16 is a base region, 1
7 is a collector region. In the present invention, the silicon oxide film 22 near the junction between the emitter region 15 and the base region 16, the silicon oxide film 22 near the junction between the base region 16 and the collector region 17, and the junction between the collector region 17 and the semiconductor substrate 11. Of the silicon oxide film 22 formed near the junction between the element surrounded by the silicon oxide film 22 and the element isolation silicon oxide film 13 and the element isolation silicon oxide film 13 described above. The feature is that the thickness is 20 nm or less. This reduces the effect of radiation irradiation. In this case, when the thickness of the silicon oxide film exceeds 20 nm, the direct current amplification factor is remarkably lowered by the irradiation of radiation. If the oxide film has a thickness of 5 nm or less, the effect of protecting the semiconductor device is small.
次に本発明装置の製造方法について述べる。Next, a method of manufacturing the device of the present invention will be described.
従来の製造工程によりコンタクト窓形成前の第1図(a)
までは従来方法と同様であるが、本発明では第1図(c)
に示すように、シリコン酸化膜22を形成するのに2つ
の方法がある。第1の方法では既知のエツチレートをも
つエツチング装置で12のシリコン酸化膜を残して20n
m以下の薄い酸化膜を形成する領域のみをエツチし、第
2図(c)のようにするか、あるいは第2図(b)に示すよう
に20nm以下の薄いシリコン酸化膜を形成する領域のシ
リコン酸化膜を、12の部分のみ残してすべて取り除
き、次に熱酸化または化学蒸着のような方法により第2
図(c)に示すようにシリコン酸化膜22を形成する。Figure 1 (a) before contact window formation by conventional manufacturing process
Up to this is the same as the conventional method, but in the present invention, FIG. 1 (c)
There are two methods for forming the silicon oxide film 22, as shown in FIG. In the first method, an etching apparatus having a known ethylate is used to leave 12 silicon oxide films,
Etching only the region where a thin oxide film of m or less is formed, as shown in FIG. 2 (c), or as shown in FIG. 2 (b), a region of a thin silicon oxide film of 20 nm or less is formed. The silicon oxide film is completely removed, leaving only 12 parts, and then a second layer is formed by a method such as thermal oxidation or chemical vapor deposition.
A silicon oxide film 22 is formed as shown in FIG.
第2図(d)は本発明の製造工程を適用した後、コンタク
ト窓あけし、配線14を形成したものである。FIG. 2 (d) shows that after the manufacturing process of the present invention is applied, the contact window is opened and the wiring 14 is formed.
このように本発明を実施すると、シリコン酸化膜が20n
m以下と薄いため、放射線に対する耐性が高く、シリコ
ン酸化膜をすべて取り除かないため、表面汚染等による
リーク電流が発生しにくい利点がある。When the present invention is implemented in this way, the silicon oxide film is
Since it is as thin as m or less, it has high resistance to radiation, and since the silicon oxide film is not completely removed, there is an advantage that a leak current due to surface contamination or the like is unlikely to occur.
(発明の効果) 叙上のように本発明によれば、半導体装置において、装
置の表面側のシリコン酸化膜の厚さを20nm以下にする
ことにより、放射線照射による半導体装置の特性劣化を
低減する利点がある。(Advantages of the Invention) As described above, according to the present invention, in a semiconductor device, by reducing the thickness of the silicon oxide film on the surface side of the device to 20 nm or less, deterioration of characteristics of the semiconductor device due to radiation irradiation is reduced. There are advantages.
さらにまた製造工程の大巾な変更を行う必要もなく、製
造上からも有益である。Furthermore, there is no need to make drastic changes in the manufacturing process, which is beneficial from the viewpoint of manufacturing.
第1図は本発明の一実施例の断面図、第2図は従来の半
導体装置の断面図を示す。 1,11……半導体基板、2,12,22……シリコン
酸化膜、3,13……素子間分離用シリコン酸化膜、
4,14……配線、5,15……エミツタ領域、6,1
6……ベース領域、7,17……コレクタ領域、8,1
8……半導体基板表面に現われている接合FIG. 1 is a sectional view of an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional semiconductor device. 1, 11 ... Semiconductor substrate, 2, 12, 22 ... Silicon oxide film, 3, 13 ... Silicon oxide film for element isolation,
4, 14 ... Wiring, 5, 15 ... Emitter area, 6, 1
6 ... Base region, 7, 17 ... Collector region, 8, 1
8: Bonding appearing on the surface of the semiconductor substrate
Claims (2)
るバイポーラトランジスタを有する半導体装置におい
て、少くともエミツタ・ベースとの間の接合部付近及び
ベース・コレクタとの間の接合部付近に形成されている
シリコン酸化膜の厚さを20nm以下とすることを特徴と
する半導体装置。1. A semiconductor device having a bipolar transistor for protecting a semiconductor surface with a silicon oxide film, the semiconductor device being formed at least near a junction between an emitter and a base and a junction between a base and a collector. A semiconductor device characterized in that the thickness of the silicon oxide film is 20 nm or less.
半導体装置において、素子間分離用シリコン酸化膜に囲
まれた素子と、前記の素子間分離用シリコン酸化膜との
間の接合部付近に形成されているシリコン酸化膜の厚さ
を20nm以下とすることを特徴とする半導体装置。2. A semiconductor device in which elements are separated by a silicon oxide film, in the vicinity of a junction between an element surrounded by the element isolation silicon oxide film and the element isolation silicon oxide film. A semiconductor device, wherein the thickness of the formed silicon oxide film is 20 nm or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59167886A JPH0658910B2 (en) | 1984-08-13 | 1984-08-13 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59167886A JPH0658910B2 (en) | 1984-08-13 | 1984-08-13 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6147665A JPS6147665A (en) | 1986-03-08 |
| JPH0658910B2 true JPH0658910B2 (en) | 1994-08-03 |
Family
ID=15857893
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59167886A Expired - Lifetime JPH0658910B2 (en) | 1984-08-13 | 1984-08-13 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0658910B2 (en) |
-
1984
- 1984-08-13 JP JP59167886A patent/JPH0658910B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6147665A (en) | 1986-03-08 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |