JPH0587974B2 - - Google Patents
Info
- Publication number
- JPH0587974B2 JPH0587974B2 JP60063424A JP6342485A JPH0587974B2 JP H0587974 B2 JPH0587974 B2 JP H0587974B2 JP 60063424 A JP60063424 A JP 60063424A JP 6342485 A JP6342485 A JP 6342485A JP H0587974 B2 JPH0587974 B2 JP H0587974B2
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- layer
- silicon oxide
- semiconductor device
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Bipolar Transistors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、耐輻射線性を有する半導体装置に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device having radiation resistance.
第１図は従来より用いられているバイポーラ半
導体装置の１例であり、アール・エス・ミユーラ
ー及び、テイー・アイ・カミンスによる“デバイ
ス エレクトロニクス フオー インテグレーテ
イツド サーキツツ”（ジヨン ウイレイ アン
ド ソンズ）第230頁（R.S.Muller ＆ T.I.
Kamins“Device Electronics for Integrated
Circuits”（John Wiley ＆ Sons）pp.230）に
示されている。
Figure 1 shows an example of a bipolar semiconductor device that has been used in the past, and is shown in "Device Electronics for Integrated Circuits" by R.S. Miller and T.I. Cummins (John Wiley and Sons), page 230. (RS Muller & T.I.
Kamins “Device Electronics for Integrated
Circuits” (John Wiley & Sons) pp.230).
ここで、２はｎ形エピタキシヤル層、４，６は
高濃度ｎ形領域、５はＰ形領域、３は酸化膜、７
は電極である。この半導体装置は、輻射線照射等
により酸化膜３とシリコン膜２，４，５，６の間
に形成された界面準位や、酸化膜３中に形成され
た正電荷のために、低電流領域でベース電流が増
加し、電流増幅率の低下が生じる。特に、第１図
に示されるようなnpnトランジスタは、エミツ
タ・コレクタ間にチヤネルが形成され、コレクタ
電流が増加するという欠点を持つていた。 Here, 2 is an n-type epitaxial layer, 4 and 6 are high concentration n-type regions, 5 is a P-type region, 3 is an oxide film, and 7
is an electrode. This semiconductor device has a low current due to the interface states formed between the oxide film 3 and the silicon films 2, 4, 5, and 6 due to radiation irradiation, and the positive charges formed in the oxide film 3. In this region, the base current increases and the current amplification factor decreases. In particular, the npn transistor shown in FIG. 1 has the disadvantage that a channel is formed between the emitter and the collector, resulting in an increase in collector current.
本発明の目的は、上記従来の半導体装置の問題
点を改善した半導体装置を提供することにある。
An object of the present invention is to provide a semiconductor device that improves the problems of the conventional semiconductor device described above.
前述のごとく、一般に、バイポーラトランジス
タに波長の短い紫外線や電磁波、Ｘ線、高速荷電
粒子線高速中性子線等（明細書中にて、輻射線と
いう。）を照射すると、電流増幅率の低下が生じ
ることが知られている。この原因は、輻射線照射
により半導体基板と酸化膜との間に界面準位が形
成されると共に、酸化膜中に正の固定電荷が多く
形成、蓄積され、この界面準位及び正の固定電荷
を通して、正孔、電子の再結合が生じ表面再結合
電流が増加することによると考えられている。し
かし、これらの界面準位及び正の固定電荷は、酸
化膜厚が薄いほど蓄積されにくいため、輻射線量
を増すために薄い酸化膜を形成することが必要と
なる。
As mentioned above, in general, when a bipolar transistor is irradiated with short-wavelength ultraviolet rays, electromagnetic waves, X-rays, fast charged particle beams, fast neutron beams, etc. (referred to as radiation in the specification), the current amplification factor decreases. It is known. The reason for this is that an interface state is formed between the semiconductor substrate and the oxide film due to radiation irradiation, and a large amount of positive fixed charges are formed and accumulated in the oxide film. This is thought to be due to the fact that holes and electrons recombine through the process, resulting in an increase in surface recombination current. However, these interface states and positive fixed charges are less likely to accumulate as the oxide film becomes thinner, so it is necessary to form a thin oxide film in order to increase the radiation dose.
しかし、酸化膜を単に薄くすると、各電極間配
線により表面ポテンシヤルが変化してしまい信頼
性の低下を招いてしまう。 However, if the oxide film is simply made thinner, the surface potential changes due to the wiring between each electrode, resulting in a decrease in reliability.
そこで、本発明では、素子間配線のない表面は
薄い酸化膜で覆い、素子間配線下は、厚い酸化膜
とすることにより、配線容量を減少させたもので
ある。 Therefore, in the present invention, the surface where there is no inter-element wiring is covered with a thin oxide film, and the area under the inter-element wiring is formed with a thick oxide film, thereby reducing the wiring capacitance.
以下、本発明の実施例を詳細に説明する。 Examples of the present invention will be described in detail below.
第２図は本発明の第１の実施例を示す断面構造
図である。本実施例の半導体装置は、素子の形成
された表面に、膜厚の薄い、例えば50〜200Åの
シリコン酸化膜１１を有し、各電極からの配線７
直下に膜厚の厚い、例えば2000〜5000Åのシリコ
ン酸化膜１３が形成されている。この薄膜酸化膜
により輻射線照射による固定電荷の蓄積が減少
し、界面の影響が抑えられバイポーラトランジス
タの電流増幅率の低下を抑えることができる。な
お、本実施例では、バイポーラトランジスタとし
て縦型npnトランジスタが例示されているが、縦
型pnp、横型pnp、横型npn、ダイオード、抵抗
等すべてのバイポーラ型素子に有効であることは
いうまでもない。 FIG. 2 is a cross-sectional structural diagram showing the first embodiment of the present invention. The semiconductor device of this embodiment has a thin silicon oxide film 11 of, for example, 50 to 200 Å thick, on the surface on which elements are formed, and has wiring lines 7 from each electrode.
A thick silicon oxide film 13 having a thickness of, for example, 2000 to 5000 Å is formed directly below. This thin oxide film reduces the accumulation of fixed charges caused by radiation irradiation, suppresses the influence of the interface, and suppresses a decrease in the current amplification factor of the bipolar transistor. In this embodiment, a vertical NPN transistor is exemplified as a bipolar transistor, but it goes without saying that it is effective for all bipolar elements such as vertical PNP, horizontal PNP, horizontal NPN, diode, and resistor. .
次に、本発明の第１の実施例の半導体装置の製
造方法を説明する。 Next, a method for manufacturing a semiconductor device according to a first embodiment of the present invention will be described.
第３図ａ〜ｅは、第２図に示された本発明のバ
イポーラトランジスタの製造工程を工程順に示し
た断面構造図である。主要工程を図番にしたがつ
て説明する。 FIGS. 3a to 3e are cross-sectional structural views showing the manufacturing process of the bipolar transistor of the present invention shown in FIG. 2 in order of process. The main processes will be explained using drawing numbers.
(a)：高濃度ｎ形基板又はｎ型埋込層１上にｎ形エ
ピタキシヤル層２を成長させ、全面にシリコ
ン酸化層３を形成する。次に、ホトレジスト
を塗布し、ベース領域形成用の穴明けを行い
ベース不純物を添加しでベース領域（ｐ形領
域）５を形成し、ホトレジストを除去する。
続いて、ホトレジストを塗布し、エミツタ及
びコレクタ領域形成用の穴明けを行いエミツ
タ不純物を添加してエミツタ領域６及びコレ
クタ取り出し領域４を形成し、ホトレジスト
を除去する。(a): An n-type epitaxial layer 2 is grown on a heavily doped n-type substrate or an n-type buried layer 1, and a silicon oxide layer 3 is formed on the entire surface. Next, a photoresist is applied, a hole is made for forming a base region, a base impurity is added to form a base region (p-type region) 5, and the photoresist is removed.
Subsequently, photoresist is applied, holes are made for forming emitter and collector regions, emitter impurities are added to form emitter regions 6 and collector extraction regions 4, and the photoresist is removed.
(b)：表面シリコン酸化膜３を全面除去し、再び全
面に950℃以上の高温条件下で50〜200Åの膜
厚を有するシリコン酸化膜１１を形成し、シ
リコン酸化膜１１上にシリコン窒化膜１２及
び600℃以下の低温条件下で、2000Å以上の
膜厚を有するシリコン酸化膜１３を堆積させ
る。(b): The surface silicon oxide film 3 is completely removed, a silicon oxide film 11 having a thickness of 50 to 200 Å is formed again on the entire surface under high temperature conditions of 950°C or higher, and a silicon nitride film is formed on the silicon oxide film 11. A silicon oxide film 13 having a thickness of 2000 Å or more is deposited under low temperature conditions of 12 and 600° C. or less.
(c)：全面にホトレジストを塗布し、エミツタ・ベ
ース・コレクタ領域取り出し電極用の穴明け
を行い、順次、シリコン酸化膜１３、シリコ
ン窒化膜１２、シリコン酸化膜１１の穴明け
を行つた後ホトレジストを除去する。(c): Apply photoresist to the entire surface, make holes for the emitter, base, and collector region extraction electrodes, and then sequentially make holes for silicon oxide film 13, silicon nitride film 12, and silicon oxide film 11, and then apply photoresist. remove.
(d)：配線用導電体を例えば蒸着させ、配線のパタ
ーニングを行う。次に、シリコン酸化膜１３
をエツチングして、配線直下以外のシリコン
酸化膜１３を除去する。(d): A conductor for wiring is deposited, for example, and the wiring is patterned. Next, silicon oxide film 13
The silicon oxide film 13 other than directly under the wiring is removed by etching.
本発明のよれば、半導体装置表面が膜厚の薄い
酸化膜で覆われているために、輻射線照射による
正の固定電荷の蓄積、界面準位の増加を防止し、
トランジスタの電流増幅率の低下を防止すること
ができる。
According to the present invention, since the surface of the semiconductor device is covered with a thin oxide film, accumulation of positive fixed charges and increase in interface states due to radiation irradiation are prevented,
A decrease in the current amplification factor of the transistor can be prevented.
具体的には、再酸化により形成された酸化膜を
100Åの厚さで形成し、配線下の酸化膜厚を、
3000Åに形成し、npnトランジスタに、輻射線を
１×105rad照射したとき、電流増幅率が初期値の
85％になり、従来50％まで低下していたのに比べ
大幅な改善が得られた。 Specifically, the oxide film formed by reoxidation is
Formed to a thickness of 100 Å, the oxide film thickness under the wiring is
When the npn transistor is formed with a thickness of 3000 Å and irradiated with radiation of 1×10 5 rad, the current amplification factor becomes the initial value.
The ratio was now 85%, which was a significant improvement compared to the previous 50%.
第１図は従来の半導体装置の一例を示す断面
図、第２図は本発明の半導体装置の第１の実施例
を示す断面図、第３図ａ〜ｄは、第２図に示した
本発明の半導体装置の製造方法を示す断面図であ
る。
１……高濃度ｎ形層、２……ｎ形エピタキシヤ
ル層、３，１１，１３……シリコン酸化膜、４…
…コクレタ取り出し領域、６……エミツタ領域、
５……ベース領域、７……電極、１２……シリコ
ン窒化膜。
FIG. 1 is a sectional view showing an example of a conventional semiconductor device, FIG. 2 is a sectional view showing a first embodiment of the semiconductor device of the present invention, and FIGS. 1 is a cross-sectional view showing a method for manufacturing a semiconductor device of the invention. 1... High concentration n-type layer, 2... N-type epitaxial layer, 3, 11, 13... Silicon oxide film, 4...
...Kokureta extraction area, 6...Emitsuta area,
5... Base region, 7... Electrode, 12... Silicon nitride film.
Claims (1)
長層と、 該エピタキシヤル成長層に設けられたベース領
域と、 該ベース領域内に設けられたエミツタ領域と、 上記ベース及びエミツタ領域に接続された配線
層とを有するバイポーラトランジスタにおいて、 上記配線層とエピタキシヤル成長層の間をシリ
コン酸化膜とシリコン窒化膜とシリコン酸化膜の
３層構造から成り、 上記配線層以外の上記エピタキシヤル成長層上
にはシリコン窒化膜とシリコン酸化膜の２層構造
から成ることを特徴とする半導体装置。[Scope of Claims] 1. an epitaxial growth layer formed on a semiconductor substrate; a base region provided in the epitaxial growth layer; an emitter region provided in the base region; and the base and emitter region. In a bipolar transistor having a wiring layer connected to the wiring layer, a three-layer structure consisting of a silicon oxide film, a silicon nitride film, and a silicon oxide film is provided between the wiring layer and the epitaxial growth layer, and the epitaxial layer other than the wiring layer is connected to the epitaxial growth layer. A semiconductor device comprising a two-layer structure of a silicon nitride film and a silicon oxide film on a growth layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60063424A JPS61224340A (en) | 1985-03-29 | 1985-03-29 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60063424A JPS61224340A (en) | 1985-03-29 | 1985-03-29 | Semiconductor device and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61224340A JPS61224340A (en) | 1986-10-06 |
| JPH0587974B2 true JPH0587974B2 (en) | 1993-12-20 |
Family
ID=13228889
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60063424A Granted JPS61224340A (en) | 1985-03-29 | 1985-03-29 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61224340A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01205466A (en) * | 1988-02-10 | 1989-08-17 | Nec Corp | Semiconductor device and its manufacture |
| JPH03126228A (en) * | 1989-10-12 | 1991-05-29 | Nec Corp | Method for manufacturing semiconductor integrated circuit device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57183050A (en) * | 1981-05-02 | 1982-11-11 | Fujitsu Ltd | Integrated circuit |
-
1985
- 1985-03-29 JP JP60063424A patent/JPS61224340A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61224340A (en) | 1986-10-06 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |