JPH0658917B2 - Bipolar transistor and manufacturing method thereof - Google Patents

Description

The present invention relates to a bipolar transistor and a manufacturing method thereof, and more particularly to a heterojunction bipolar transistor using a compound semiconductor and a manufacturing method thereof.

[Conventional technology]

In recent years, research and development of a heterojunction bipolar transistor (HBT) using a junction of two kinds of semiconductors having different band gaps, such as a combination of AlGaAs / GaAs, has been actively conducted. Such a device has a subcollector layer, a collector layer, a base layer, and an emitter layer which are sequentially grown on a substrate by using a molecular beam epitaxial growth (MBE) technique or a metal organic CVD technique. This HBT has an excellent high frequency characteristic without decreasing the current gain even if the base resistance is reduced by increasing the doping concentration of the base.

FIG. 7 is a sectional view of an example of a conventional heterojunction bipolar transistor.

N ⁺ -GaAs as a subcollector layer on the semi-insulating GaAs substrate 9
Layer 8, n-GaAs layer 12 serving as collector layer, and base layer
The p ⁺ -GaAs layer 5, the n-Al _0.3 Ga _0.7 As layer 4 serving as the emitter layer and the n ⁺ -GaAs layer 11 serving as the cap layer for facilitating ohmic contact are grown by the MBE method. The emitter electrode 1, the base electrode 2, and the collector electrode 3 are provided on the exposed emitter layer, base layer, and subcollector layer, respectively.

[Problems to be solved by the invention]

When the HBT is made to perform a high electron injection operation, the number of electrons injected into the collector increases and the potential distribution in the collector sky layer changes.

FIG. 7 shows a group of equipotential lines 21 in the collector layer analyzed by a two-dimensional device simulator and a group of vectors 10 showing the movement of electrons.

As shown in FIG. 7, the equipotential lines are curved in the substrate vertical direction in the peripheral portion of the intrinsic HBT region located directly below the emitter electrode 1, and the equipotential lines have a two-dimensional distribution. Therefore, the movement of electrons has not only the vertical component of the substrate but also the horizontal component of the substrate. Therefore, the movement of the electrons in the collector does not have one-dimensional uniformity, and the collector depletion transit time of the electrons traveling in each direction is various.
It has a drawback that the phases when amplifying an ultra high frequency signal are not uniform. This means that the current gain cutoff frequency is lowered, which is a problem.

Furthermore, since the current distribution in the base region is unnecessarily widened due to the current distribution in the collector region being widened, the recombination region is expanded, the recombination current is increased, and the current gain itself is also reduced. It was a problem.

These become more obvious as the emitter size is reduced. Therefore, even if the emitter size is set to the submicron level and the current density is increased to significantly improve the high frequency characteristics of the HBT, the high frequency characteristics are not improved as expected. In addition, the parasitic base-collector junction capacitance in the external base region has also been a problem as a cause of deterioration of high frequency characteristics.

It is an object of the present invention to provide a bipolar transistor in which the uniformity of the current in the collector depletion layer region and the base region is not deteriorated even when the emitter size is miniaturized, and the parasitic capacitance is reduced, and a manufacturing method thereof.

[Means for solving problems]

A bipolar transistor according to a first invention is an npn bipolar transistor having a subcollector layer, a collector layer, a base layer and an emitter layer sequentially formed on a semiconductor substrate, and is located below an external base layer not in contact with the emitter layer. Between the collector layer and the collector layer located below the intrinsic base layer in contact with the emitter layer, a semiconductor layer having an electron affinity lower than that of the collector layer located below the intrinsic base layer is formed. is there.

A method of manufacturing a bipolar transistor according to a second aspect of the present invention includes a step of sequentially forming an n-type subcollector layer and a non-doped spacer layer on a semiconductor substrate, and a mask made of an insulating film is selectively formed on the spacer layer. A step of etching the spacer layer by an anisotropic etching method using the mask to form an opening reaching the subcollector layer; and anisotropy etching after forming a semiconductor layer on the entire surface including the opening. A side wall of the semiconductor layer is formed on the side surface of the opening by etching by a method, a step of filling the opening with an epitaxial layer having an electron affinity higher than that of the semiconductor forming the side wall and forming an intrinsic collector region; After removing the mask, sequentially forming an inverted p-type base layer and an n-type emitter layer on the entire surface including the intrinsic collector region. In constructed.

A method for manufacturing a bipolar transistor according to a third aspect of the present invention comprises a step of sequentially forming an n-type subcollector layer, a non-doped spacer layer, and a p-type external base layer forming a part of an external base region on a semiconductor substrate, Step of selectively forming a mask made of an insulating film on the external base layer, and etching the external base layer and the spacer layer by anisotropic etching using the mask to form an opening reaching the subcollector layer And a step of forming a side wall made of a semiconductor layer on the side surface of the opening by forming a semiconductor layer on the entire surface including the opening and then etching by an anisotropic etching method. Filling the opening with an epitaxial layer having a high affinity to form an intrinsic collector region, and removing the mask, then the intrinsic collector region Configured to include a step of sequentially forming a p-type base layer and the n-type emitter layer on the entire surface including.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a first embodiment of a bipolar transistor of the first invention.

In FIG. 1, n ⁺ -with a thickness of 5000 Å to be a subcollector and a doping concentration of 1 × 10 ¹⁹ cm ^-3 is formed on the semi-insulating GaAs substrate 9.
A GaAs layer 8 is formed, and on this n ⁺ -GaAs layer 8,
Immediately below the intrinsic base region in contact with the emitter layer, a thickness of 4000 Å to become an intrinsic collector and a doping concentration of 5 × 10 ¹⁶ c
n-GaAs layer 12 m _-3 is provided, a non-doped thick 4000Å in part just below the external base region not in contact with the emitter layer
A GaAs layer 6 is provided.

On top of these, a thickness of 1000 Å to be the base layer, a p ⁺ -GaAs layer 5 with a doping concentration of 1 × 10 ¹⁹ cm ^-3 and a thickness of 2000 Å to be the emitter layer, and an n-with a doping concentration of 3 × 10 ¹⁷ cm ^-3 . Al _0.3 Ga
_{A 0.7} As layer 4 and an n ⁺ -GaAs layer 11 having a thickness of 1500 Å and a doping concentration of 5 × 10 ¹⁸ cm ^-3 to be the cap layer are provided. In addition, 1 is an ohmic emitter electrode made of AuGe-Ni,
2 is an ohmic base electrode made of AuZn-Ni, 3 is AuGe-Ni
Is an ohmic collector electrode composed of

And, between the non-doped GaAs layer 6 and the n-GaAs layer 12,
Non-doped Al _0.3 G with electron affinity smaller than that of n-GaAs layer 12
a _0.7 As layer 7 is provided. The electron affinity of Al _0.3 Ga _0.7 As is 3.83 eV, while that of GaAs is 4.05 eV.
Is.

A semiconductor band diagram along the line AA 'in FIG. 1 is shown in FIG.

Since the electron affinity of Al _0.3 Ga _0.7 As is smaller than GaAs by about 0.22 eV, the barrier for 0.22 eV is the n-GaAs layer 12 and non-doped Al.
Electrons 34 are generated between _0.3 Ga _0.7 As layer 7 and n-GaAs layer 1
Can be confined only in 2. Therefore, the electron flow is the first
As shown at 10 in the figure, it has no two-dimensional distribution and becomes uniform in the intrinsic collector.

In the embodiment shown in FIG. 1, the collector layer located below the external base region below the base electrode is made of non-doped GaAs 6 to reduce the parasitic base-collector capacitance.

FIG. 3 is a sectional view of a second embodiment of the bipolar transistor of the first invention.

In FIG. 3, p ⁺ -under the base electrode 2 and under the GaAs layer 5 p ⁺ -
It is the same as the above-described first embodiment except that the GaAs layer 13 is provided. In FIG. 3, the p ⁺ -GaAs layer 13 is additionally provided as a part of the external base to reduce the base resistance.

The semiconductor band diagram on the line AA 'in FIG. 3 is the same as that in FIG. Further, the band diagram on the line BB 'is as shown in FIG.

Also in this case, the electrons are trapped in the n-GaAs layer 12 by the barrier attributed to the difference in electron affinity between GaAs and Al _0.3 Ga _0.7 As, and the electron flow 10 becomes uniform. In addition, the parasitic capacitance between the p ⁺ -GaAs layer 13 introduced to reduce the base resistance and the n-GaAs layer 12 serving as the intrinsic collector is undoped Al.
It is reduced by the presence of the _0.3 Ga _0.7 As layer 7.

5 (a) to 5 (f) are cross-sectional views of a semiconductor chip showing the order of steps for explaining one embodiment of the method for manufacturing a bipolar transistor of the second invention.

As shown in FIG. 5 (a), first, an n ⁺ -GaAs layer 8 to be a subcollector layer and a non-doped GaAs layer 6 to be a spacer layer are epitaxially grown on the semi-insulating GaAs substrate 9 by the MBE method.

Next, as shown in FIG. 5 (b), S is deposited on the non-doped GaAs layer 6.
After forming a mask 25 made of iO ₂ , this mask 2
5, the anisotropic selective etching is performed in the substrate vertical direction by RIE using CCl ₂ F ₂ gas until the n ⁺ -GaAs layer 8 is exposed to form an opening 20.

Next, as shown in FIG. 5 (c), Al _0.3 Ga was formed by the MBE method.
_{A 0.7} As layer 7 is deposited on the entire surface including the opening 20. At this time, the Al _0.3 Ga _0.7 As layer 7 in the portion in contact with the non-doped GaAs layer 6 and the n ⁺ -GaAs layer 8 is single-crystallized, but the other portions remain amorphous Al _0.3 Ga _0.7 As. .

Next, as shown in FIG. 5 (d), anisotropic etching is performed from the direction perpendicular to the substrate by the RIE method using CCl ₂ F ₂ gas to form the opening 2
A side wall made of Al _0.3 Ga _0.7 As layer 7 is formed on the side surface of 0.

Next, as shown in FIG. 5 (e), Al _0.3 Ga is formed by the MOCVD method.
_An n-GaAs layer 12 having an electron affinity larger than _0.7 As is selectively epitaxially grown to form an intrinsic collector region.

Next, as shown in FIG. 5 (f), after removing the mask 25, the p ⁺ -GaAs layer 5, n-Al _0.3 Ga _0.7 As layer 4 and n are formed on the entire surface including the n-GaAs layer 12 by the MBE method. ^{A +} -GaAs layer 11 is grown to form a base layer, an emitter layer and a cap layer, respectively.

After each semiconductor layer is formed in this way, etching and electrode formation using a matching mask are performed to form the bipolar transistor of the first embodiment of the first invention shown in FIG. it can.

6 (a) to 6 (f) are cross-sectional views of a semiconductor chip showing the order of steps for explaining one embodiment of the method for manufacturing a bipolar transistor of the third invention.

First, as shown in FIG. 6 (a), n is placed on the semi-insulating GaAs substrate 9.
⁺ -GaAs layer 8, non-doped GaAs layer 6, p ⁺ -GaAs layer 13
It grows by the BE method.

Next, as shown in FIG. 6 (b), a mask 25 made of SiO ₂
The p ⁺ -GaAs layer 13 and the non-doped GaAs layer 6 by using C
The n ⁺ -GaAs layer 8 is exposed by vertical etching by the RIE method using Cl ₂ F ₂ gas.

Next, as shown in FIG. 6 (c), the Al _0.3 Ga _0.7 As layer 7 is MB
It was deposited by the E method, and then CCl ₂ F ₂ as shown in Fig. 6 (d).
The side wall 7 is formed by etching by RIE using gas.

Next, as shown in FIG. 6 (e), the n-GaAs layer 1 is formed by the MOCVD method.
2 is selectively epitaxially grown. Next, after removing the mask 25, the p ⁺ -GaAs layer 5 and n-Al _0.3 Ga _0.7 A are formed by the MBE method.
The s layer 4 and the n ⁺ -GaAs layer 11 are grown.

After that, etching and electrode formation are performed using the alignment mask to form the bipolar transistor of the second embodiment of the first invention shown in FIG.

Although the embodiment of the present invention has been described by taking the AlGaAs / GaAs-based HBT as an example, the material is not limited to this and other semiconductor materials may be used. The present invention is not limited to HBTs, but can be applied to homojunction bipolar transistors.

〔The invention's effect〕

As described above, in the present invention, the current can be confined in the intrinsic region in the collector region, so that the current density can be increased, and the parasitic capacitance can be reduced while reducing the parasitic resistance. This has the effect of dramatically improving high-frequency characteristics.

[Brief description of drawings]

1 is a sectional view of a first embodiment of the first invention, FIG. 2 is a lateral band diagram in its collector region, and FIG. 3 is a sectional view of a second embodiment of the first invention. Fourth
FIG. 5 shows a lateral band diagram in the collector region, FIG. 5 is a sectional view of a semiconductor chip for explaining an embodiment of the second invention, and FIG. 6 shows an embodiment of the third invention. FIG. 7 is a cross-sectional view of a semiconductor chip for use in the conventional bipolar transistor. 1 ... Emitter electrode, 2 ... Base electrode, 3 ... Collector electrode, 4 ... n-Al _0.3 Ga _0.7 As layer, 5 ... P ⁺ -GaAs layer,
6 ... Non-doped GaAs layer, 7 ... Non-doped Al _0.3 Ga _0.7
As layer, 8 ... n ⁺ -GaAs layer, 9 ... semi-insulating GaAs substrate, 1
0 …… electron flow, 11 …… n ⁺ -GaAs layer, 12 …… n-GaA
s layer, 13 ... p ⁺ -GaAs layer.

Claims (3)

[Claims] 1. A sub-collector layer, a collector layer, a base layer and an emitter layer which are sequentially formed on a semiconductor substrate.
In the npn bipolar transistor, between the collector layer located below the external base layer not in contact with the emitter layer and the collector layer located below the intrinsic base layer in contact with the emitter layer, the collector layer is located below the intrinsic base layer. A bipolar transistor characterized in that a semiconductor layer having an electron affinity smaller than that of the collector layer located is formed. 2. A step of sequentially forming an n-type subcollector layer and a non-doped spacer layer on a semiconductor substrate, a step of selectively forming a mask made of an insulating film on the spacer layer, and using the mask. A step of etching the spacer layer by an anisotropic etching method to form an opening reaching the sub-collector layer; and a step of forming a semiconductor layer on the entire surface including the opening and then etching by an anisotropic etching method. A side wall made of a semiconductor layer on a side surface of the substrate, a step of filling the opening with an epitaxial layer having an electron affinity higher than that of the semiconductor forming the side wall to form an intrinsic collector region, and after removing the mask, the intrinsic collector region is removed. A step of sequentially forming a p-type base layer and an n-type emitter layer on the entire surface including the region. Production method. 3. An n-type subcollector layer, a non-doped spacer layer, and a part of an external base region are formed on a semiconductor substrate.
a step of sequentially forming a p-type external base layer, a step of selectively forming a mask made of an insulating film on the external base layer, and the external base layer and the spacer layer by anisotropic etching using the mask And forming an opening reaching the sub-collector layer, and forming a semiconductor layer on the entire surface including the opening and etching by an anisotropic etching method to form a side wall of the semiconductor layer on the side surface of the opening. A step of forming an intrinsic collector region by filling the opening with an epitaxial layer having an electron affinity higher than that of the semiconductor forming the sidewall, and after removing the mask, a p-type base is formed on the entire surface including the intrinsic collector region. A step of sequentially forming a layer and an n-type emitter layer.