JPH0659051B2 - Clock reproduction circuit - Google Patents

Description

The present invention relates to a clock recovery circuit in a digital transmission device.

[Prior Art] Conventionally, as a technology in such a field, there is one described in Japanese Patent Application No. 59-178467 proposed by the inventors of the present application. The configuration will be described below.

Japanese Patent Application No. 59-178467 relates to a timing extraction method for extracting timing from a received AMI signal.

In this type of timing extraction method, the pattern of the received AMI signal is detected, and the timing is extracted only from the code sequence with small inter-bit interference and avoiding error codes. In this way, if the clock signal is reproduced using the conventional clock reproduction circuit composed of the digital phase synchronization circuit based on the timing signal extracted from only the specific pattern with less inter-bit interference, the pattern effect is small,
A clock signal with low jitter can be obtained.

[Problems to be Solved by the Invention] However, the circuit having the above configuration has the following problems.

If the clock signal is reproduced based on the timing signal extracted from only the specific pattern, the pattern effect is small, and the clock signal with small jitter can be obtained. On the other hand, if the specific pattern is not obtained, not only the timing signal cannot be extracted, It becomes impossible to reproduce the clock signal based on this timing signal, and there is a risk of loss of synchronization.

In order to prevent this, a method of inserting the specific pattern into the transmission frame can be considered, but this method cannot be adopted when the configuration of the transmission frame is already decided.

The present invention provides a clock recovery circuit that solves the problem that the above-mentioned conventional art has, that is, out of synchronization when a specific pattern cannot be obtained.

[Means for Solving Problems] In order to solve the above problems, the present invention inputs a timing signal extracted from a specific pattern of an input code string and reproduces a clock signal synchronized with the timing signal. In the circuit, a phase comparator for comparing the phases of the timing signal and the feedback signal and outputting a signal of the comparison result, and a counter for integrating the comparison result and outputting an overflow signal when the integrated value becomes a certain value or more. And a fixed oscillator that outputs an oscillation signal of a constant frequency,
A pulse insertion / removal circuit for inserting / removing a predetermined number of pulse signals to / from the oscillation signal based on the overflow signal, and dividing the output signal of the pulse insertion / removal circuit into a signal of a predetermined frequency and feeding it back to the feedback. A frequency divider for feeding back the signal to the phase comparator as a signal and an out-of-synchronization prevention circuit are provided. Here, the synchronization loss prevention circuit monitors whether or not the overflow signal is output for a certain period of time, and when the overflow signal is not output for the certain period of time, based on the contents of the counter at that time, the pulse is output. It has the function of operating the insertion / removal circuit to forcibly insert or remove the pulse signal.

[Operation] According to the present invention, since the clock recovery circuit is configured as described above, the pulse insertion / removal circuit inserts or removes a pulse in the oscillation signal based on the overflow signal from the counter, and divides it. By dividing with a vessel,
Synchronize by lagging or advancing the phase of the oscillation signal. The out-of-synchronization prevention circuit forces the phase control based on the contents of the counter when the phase control as described above is not performed within a certain time. As a result, even if the timing signal cannot be extracted due to a certain probability, the loss of synchronism can be prevented, and the reproduced clock signal can be stabilized. Therefore, the above problems can be eliminated.

[Embodiment] The drawings are circuit configuration diagrams of a clock recovery circuit showing an embodiment of the present invention.

In the figure, 1 is an input terminal for inputting an input signal a composed of, for example, an AMI signal, a timing extraction circuit 2 is connected to this input terminal 1, and a clock recovery circuit 10 is provided on the output side of the timing extraction circuit 2. It is connected.

The timing extraction circuit 2 is a circuit that receives the input signal a and obtains the timing signal 2a with less jitter extracted from the pulse rising edge of only the code pattern with less inter-bit interference, for example, Japanese Patent Application No. 59-178467. It is composed of a calligraphy circuit.

The clock reproduction circuit 10 has an input terminal 11 for inputting a timing signal 2a and an output terminal 12 for outputting an output signal 18a, and a phase comparator 13, a racing counter 14 between the input and output terminals 11 and 12. , Out of sync circuit 15, fixed oscillator
16, a pulse insertion / removal circuit 17, and a frequency divider 18 are connected.

The input side of the phase comparator 13 has an input terminal 11 and a frequency divider 18
Is a circuit which is respectively connected to the output side of the circuit, performs a phase comparison between the timing signal 2a and the output signal (feedback signal) 18a of the frequency divider 18, and outputs the signals 13a and 13b according to the comparison result.

The racing counter 14 includes, for example, counters 20 and 21 and OR.
It consists of a gate 22. Each of the counters 20 and 21 inputs the output signals 13a and 13b of the phase comparator 13, respectively, counts them, outputs signals 20a and 21a representing the counted values, and supplies them to the pulse insertion / removal circuit 17. When the count value overflows, the overflow signals 20b and 21b are output and given to the OR gate 22, the synchronization loss prevention circuit 15 and the pulse insertion / removal circuit 17. The OR gate 22 takes the logical sum of the overflow signals 20b and 21b and the output signal of the loss-of-synchronization prevention circuit 15, and outputs the logical sum of the output signals 22a.
This is a circuit that resets 1.

The synchronization loss prevention circuit 15 includes, for example, an OR gate 30 and a timer 31.
It is composed of. The OR gate 30 receives the overflow signal 20
This is a circuit that takes the logical sum of b and 21b and outputs the output signal 30a to the timer 31. The timer 31 is a circuit that inputs the signal 30a, counts time, outputs the signal 31a, and supplies the signal 31a to the OR gate 22 and the pulse insertion / removal circuit 17. The signal 30a changes to logic "1" during a certain period of time. Otherwise, the output signal 31a becomes logic "1" and is reset, and the time is counted again,
When the signal 30a becomes a logical "1" during a fixed time, the timer 31 is reset at that point and the time is counted again.

The pulse insertion / removal circuit 17 outputs the output signals 20 of the counters 20 and 21.
Based on a, 20b, 21a, 21b and the output signal 31a of the timer 31, an oscillation signal of a constant frequency output from the fixed oscillator 16.
A circuit that inserts or removes a pulse signal from 16a and supplies the output signal 17a to the frequency divider 18.

The frequency divider 18 frequency-divides the output signal 17a of the pulse insertion / removal circuit 17 into a signal of a predetermined frequency and supplies the signal 18a as a feedback signal to the phase comparator 13 and at the same time as the output terminal 12
Is a circuit that outputs to. This frequency divider 18 and fixed oscillator 16
The pulse insertion / removal circuit 17 constitutes a clock oscillator.

The operation of the clock recovery circuit configured as above will be described.

First, when the input signal a is applied to the input terminal 1, the timing extraction circuit 2 extracts the timing signal 2a only from the signal with small inter-bit interference. Here, the timing extraction circuit 2 is composed of a circuit described in Japanese Patent Application No. 59-178467 (hereinafter referred to as the first circuit) and other general circuits (hereinafter referred to as the second circuit). The following is a comparison of the extracted probabilities of the timing signal 2a in the case. When the input signal a has a ramdom pattern, when the timing signal 2a is extracted from all the rising edges of the code "1" by the second circuit, the extraction probability becomes 0.5. On the other hand, in the first circuit, "00001" is used as the specific pattern to be selected, and the code of the pattern is "1".
When the timing signal is extracted from the rising edge of, the extraction probability is 0.03125. Therefore, when the timing signal is extracted from the specific pattern (for example, 00001) in the first circuit, the extraction probability is 1/16 of that in the second circuit.
Therefore, if the number of integration stages of the digital phase-locked loop is the same, the synchronization frequency range becomes approximately 1/16, and the timing signal may not be extracted with a certain probability. Therefore, it is necessary to estimate the synchronization range to be smaller as the standard value actually applied to the device.

Therefore, the circuit of this embodiment operates as follows in order to compensate for the decrease in the synchronous frequency range.

Timing signal extracted by the timing extraction circuit 2
When 2a is input to the phase comparator 13, the phase comparator 13 performs a phase comparison between the timing signal 2a and the output signal 18a of the frequency divider 18. The phase comparison in the phase comparator 13 is performed every time the timing signal 2a is input.If the phase of the output signal 18a is delayed with respect to the timing signal 2a, the signal 13a is output, and if it is advanced, the signal 13b is output. Output and those signals 13
a and 13b are given to the counters 20 and 21, respectively.

When one of the counters 20, 21 overflows first, the overflow signal 20b
Is input to the counter 20 through the OR gate 22 and is also applied to the pulse insertion / removal circuit 17. Then, the counter 20 is set, and the pulse insertion / removal circuit 17 outputs the signal 17a obtained by removing one pulse from the oscillation signal 16a and inputs it to the frequency divider 18. Since the frequency divider 18 divides the signal 17a, the phase of the clock oscillator equivalently advances. When the other counter 21 overflows, an overflow signal 21b is output from the counter 21, which is input to the counter 21 through the OR gate 22 and also given to the pulse insertion / removal circuit 17.
Then, the counter 21 is reset, and the pulse insertion / removal circuit 17 outputs the signal 17a in which one pulse is inserted to the oscillation signal 16a and inputs the signal 17a to the frequency divider 18. Since the frequency divider 18 divides the frequency of the signal 17a, the clock reproduced equivalently is delayed. Therefore, since the output signal 18a of the frequency divider 18 is fed back to the phase comparator 13, the input signal a
Is synchronized with.

On the other hand, the overflow signals 20b and 21b are given to the timer 31 through the OR gate 30. If the output signal of the OR gate 30 does not become the logic "1" within a certain time, the timer 31 outputs the signal 31a of the logic "1", inputs it to the counters 20 and 21 through the OR gate 22, and outputs the pulse. Insertion removal circuit
Give to 17. In the pulse insertion / removal circuit 17, the magnitudes of the counter output signals 20a and 21a representing the count value are compared and
When a> 21a, only one pulse is removed from the oscillation signal 16a, and when 20a <21a, one pulse is inserted into the oscillation signal 16a to output those signals 17a, which are given to the frequency divider 18. Also,
At the same time, the counters 20 and 21 are reset by the signal 31a of logic "1" output from the timer 31, and wait for the subsequent phase comparison information.

Next, assuming the waiting time of the timer 31 to be Tw, the relationship between the Tw and the synchronous frequency range will be described.

When the frequency of occurrence of the specific pattern for timing extraction decreases, the control frequency decreases, and when the clock recovery circuit composed of the conventional digital phase locked loop is used, the average frequency of the input signal a and the fixed oscillator signal are divided. If there is a difference in the frequency (free run frequency), it becomes easy to lose synchronization. However, in this embodiment, the out-of-synchronization prevention circuit 15 is provided, and the out-of-synchronization prevention circuit 15 forcibly performs the phase control when the phase control is not performed for a certain time. Is possible.

For example, the overflow count number of the counters 20 and 21 is Ck, the waiting time of the timer 31 is Tw, the frequency division ratio of the frequency divider 18 is R, and the timing extraction pattern is "00001".
Consider the synchronization frequency range f1 when the appearance probability of the pattern is P = 1/32.

Condition Ck = 32 P = 1/32 Tw = 5120Ts However, Ts; clock signal period R = 1/72 The frequency divider output phase Δφc that can be controlled by one pulse insertion or removal is Δφc = 360 × R = 5 ( If this is replaced with a controllable time ΔTc, then ΔTc = Ts × R. Therefore, if the difference between the phase of the input signal a and the output phase of the frequency divider becomes ΔTc or more during Tw = 5120Ts, the synchronization cannot be established, and the frequency stability St required for the synchronization is as follows.

St = ΔTc / 5120Ts = (Ts × R) / 5120Ts = 1 / (72 × 5120) = 0.000002713 Therefore, the phase St is forcibly controlled at each waiting time Tw to secure the stability St for the fixed oscillator 16. Good. The synchronous frequency range 1 at this time is 1 = 0.000002713 × (1 / Ts).

In the conventional clock recovery circuit, since the phase control cycle is the average phase control cycle obtained from the timing extraction probability, it is not always possible to control to that cycle, and therefore in the synchronous frequency range where the synchronous frequency range can always be guaranteed. Absent. On the other hand, according to the present embodiment, since there is no ambiguity in the conventional synchronization range, the frequency stability St can be guaranteed by design. Therefore, the frequency divider
A stable reproduced clock signal can be obtained through the output terminal 12 on the 18th side.

In the present invention, the racing counter 14, the out-of-synchronization prevention circuit 15 and the like can be modified in various ways other than the illustrated circuits.

[Effects of the Invention] As described in detail above, based on a timing signal extracted from only a code string with small inter-bit interference, while performing integration by a counter, phase control is performed by the integrated output, and timing is performed with a certain probability. When the signal cannot be extracted, the out-of-synchronization prevention circuit forcibly controls the phase with the counter count value, so that the stability of the reproduced clock signal can be significantly improved.

[Brief description of drawings]

The drawing is a circuit configuration diagram of a clock recovery circuit showing an embodiment of the present invention. 2 ... Timing extraction circuit, 10 ... Clock recovery circuit, 13 ...
Phase comparator, 14 ... Racing counter, 15 ... Loss of synchronization prevention circuit, 16 ... Fixed oscillator, 17 ... Pulse insertion removal circuit, 18
… Divider.

Claims (1)

[Claims] 1. A clock recovery circuit for inputting a timing signal extracted from a specific pattern of an input code string and reproducing a clock signal synchronized with the timing signal, comparing the phases of the timing signal and the feedback signal, and A phase comparator that outputs a signal of a comparison result, a counter that integrates the comparison result and outputs an overflow signal when the integrated value becomes a constant value or more, a fixed oscillator that outputs an oscillation signal of a constant frequency, the overflow signal A pulse insertion / removal circuit for inserting / removing a predetermined number of pulse signals to / from the oscillation signal, and dividing the output signal of the pulse insertion / removal circuit into a signal of a predetermined frequency, which is used as the feedback signal. The frequency divider that feeds back to the phase comparator and the output of the overflow signal for a certain time Monitoring the insertion of the counter the pulse insertion removal circuit is operated to forcibly pulse signal based on the contents of that time when said overflow signal is not output during said predetermined time,
A clock recovery circuit, which is provided with an out-of-synchronization prevention circuit for performing removal.