JPH0660917B2 - Spectrum analyzer - Google Patents

Description

TECHNICAL FIELD The present invention relates to an improvement of a superheterodyne spectrum analyzer.

[Prior Art] FIG. 6 shows a circuit diagram of a conventional spectrum analyzer.
In the figure, a sweep oscillator 7 outputs a ramp waveform, which is applied to a voltage controlled oscillator (hereinafter referred to as VCO) 5. VC
Since the ramp waveform is applied to O5, the frequency _V that changes according to the applied voltage is output and added to the mixer 3.

On the other hand, the input signal S _i (usually, S _i includes many frequency components) is added to the low-pass filter 1. The low-pass filter 1 is for passing frequencies in the range that the spectrum analyzer is going to measure and for cutting other frequency components. The frequency of the output signal of the low-pass filter 1 is _L.

The mixer 3 performs mixing by the calculation of the equation (1),
The output signal (frequency _{M 1} ) is applied to a bandpass filter (hereinafter referred to as BPF) 4. BPF4 has a certain frequency
Only the frequencies around ₁ around ₁ are passed. Note Usually, this _one (1) lower the frequency of the frequency represented by the formula - the frequency value included in the _{(V L). M} = _V ± _L (1) The amplifier 8 amplifies the signal from the BPF 4.

Furthermore, in order to increase the frequency selectivity and gain,
The mixer 11, the oscillator 13, the BPF 15, and the amplifier 16 constitute a so-called double superheterodyne system.

The frequency resolution of the spectrum analyzer thus constructed is determined by the filter bandwidth of the BPF 15. Therefore, the BPF 15 is configured so that the pass bandwidth can be changed so that the frequency resolution of the spectrum analyzer can be freely set.

The amplitude of the output of the amplifier 16 is detected by the detector 17, the noise component is removed by the video filter 19, and the output is added to the vertical axis of the CRT 20. The signal of the sweep oscillator 7 is added to the horizontal axis of the CRT 20, and the waveform data as shown in FIG. 6 is displayed.

[Problems to be Solved by the Invention] As described above, the frequency resolution of the spectrum analyzer of FIG. 6 is set by changing the bandwidth of the BPF 15.

However, if the range in which the resolution can be set is increased, there is a problem that the configuration of the BPF 15 becomes large. Further, when LC or a crystal oscillator is used for the BPF 15, there is a problem that temperature drift occurs in the bandwidth and the center frequency, and highly accurate measurement cannot be performed. Further, it is not practical to calibrate such a change at regular intervals or to perform a correction calculation.

An object of the present invention is to provide a spectrum analyzer capable of increasing the stability of filter characteristics, reducing the number of adjustment points, and performing detection at high speed by digitizing the BPF 15 that determines the frequency resolution.

[Means for Solving the Problems] In order to solve the above problems, the present invention provides a superheterodyne spectrum analyzer in which a circuit of a mixer and a bandpass filter for introducing the mixer output is connected, The oscillating means for outputting two signals having a frequency equal to the center frequency of the final stage bandpass filter having a predetermined bandwidth and having phases different from each other by 90 °, and these two signals and the final stage bandpass filter are provided. Two mixers that mix the passed signal and the output terminals of these mixers are connected, and the band of each mixer output is limited by removing the frequency signal that is more than twice the center frequency of the final stage bandpass filter. Connected to the output terminals of these low-pass filters and each low-pass filter Two A for converting the output of the digital signal
A / D converters, two digital filter means connected to the output terminals of these A / D converters, the filter characteristics of which can be controlled by an externally applied control signal, and the sum of squares of the outputs of these digital filter means. The present invention is characterized by including a calculating means for calculating and a peak holding means for holding a peak value of a calculation output of the calculating means.

[Examples] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a spectrum analyzer according to the present invention, and the same parts as those in FIG. 6 are designated by the same reference numerals. The configuration of FIG. 1 is different from the configuration of FIG. 6 in the mixer 11 and thereafter.

Explaining the different configuration, a signal whose frequency value is fixed by the reference frequency generator 34 and the oscillator 36 is added to the mixer 11. A known circuit such as a PLL can be used as the oscillator 36. The output of mixer 11 is applied to BPF 30. The BPF 30 is a filter having a fixed bandwidth, unlike the conventional BPF 15 (FIG. 6) having a variable bandwidth. Therefore, it has a very simple structure as compared with the conventional BPF 15. The output of BPF 30 is applied to amplifier 32. Reference numeral 38 denotes an oscillator, which introduces a signal s1 having a stable frequency from the reference frequency generator 34 and outputs signals s2 and s3 whose phases are different from each other by 90 ° to the mixers 40 and 41. The frequencies of the signals s2 and s3 are set to be the same as the center frequency of the BPF 30. The means for outputting the two signals, which are 90 ° out of phase with each other and whose frequency is the same as the center frequency of the BPF 30, can be easily constructed by using known circuit technology. The description of the physical configuration example is omitted.

The mixers 40 and 41 perform the same calculation as in the equation (1) and add the output to the low-pass filters 43 and 44 at the next stage. The outputs of the low-pass filters 43 and 44 are converted into digital signals by the AD converters 46 and 47. The outputs of the AD converters 46 and 47 are introduced into the digital filters 50 and 51. Digital filter 50, 51
Can easily control its filter characteristics by a control signal (not shown) given from the outside, and its filter characteristics are essentially stable. Known circuits can be used for the digital filters 50 and 51, and since the individual configurations of the digital filters are not characteristic in the present invention, the description of the specific configuration is omitted. The outputs of the digital filters 50 and 51 are introduced into a calculator 53, where the sum of squares is calculated. The output of the calculator 53 is applied to the peak hold circuit 54 to hold the peak value. The output signal of the peak hold circuit 54 is added to the video filter 55 to remove noise components, converted into an analog signal by the DA converter 56 and added to the vertical axis of the CRT 20. The output signal s1 of the reference frequency generator 34 is also added to the peak hold circuit 54. Also video filters 55
Uses a known digital filter technique, and is different from the video filter 19 of FIG.

The outline of the present invention configured as described above is as follows.

Conventional BP with large structure and unstable characteristics
Instead of F15, use digital filters 50 and 51 that have stable characteristics and can freely control the frequency resolution.

However, if the BPF 15 is simply replaced by the digital filters 50 and 51, a digital filter that can handle high frequency signals is expensive because it requires a high calculation speed.
The benefits of using digital filters are reduced. Therefore,
By mixing a signal having a frequency equal to the center frequency of the final stage BPF 30 and having a phase difference of 90 ° and a signal which has passed through the BPF 30, two direct current signals are produced and passed through a low pass filter by a digital filter. The amplitude of the input signal is obtained by taking the square sum of the two signals.

The peak hold circuit 54 is provided so that the peak of the impulsive signal can be detected. That is, the maximum value can be displayed instead of the effective value in a certain section.

In FIG. 1, a signal s4 having a center frequency of the bandwidth of the BPF 30 and applied to the mixers 40 and 41 via the amplifier 32 is represented by the equation (2).

s4 = W ₁ sin ωt (2) On the other hand, the phase of the signal s4 equal to the frequency of the signal s4, the phases applied to the mixers 40 and 41 from the oscillator 38 differ by 90 °
2, s3 are expressed by Eqs. (3) and (4).

s2 = W ₂ sin (ωt−θ) (3) s3 = W ₂ sin (ωt−θ−π / 2) (4) θ is the phase difference between the signal s4 and the signals s2 and s3. Here, in order to make the explanation easy to understand, the amplitudes of the signals s2 and s3 are W ₂ = 1.
And

Since the output signal s5 of the mixer 40 has the double frequency signal removed by the low-pass filter 43, the output signal s7 of the low-pass filter 43 is expressed by equation (5).

s7 = W ₁ sin {ωt− (ωt−θ)} = W ₁ sin θ (5) Similarly, the output signal s8 of the low pass filter 44 is expressed by the equation (6).

s8 = W ₁ cos θ (6) These signals s7 and s8 are AD converters 46 and 47 and a digital filter.
After passing through 50 and 51, the arithmetic unit 53 performs the sum of squares operation, so that the signal s9 represented by the equation (7) is extracted from the arithmetic unit 53.

s9 = (W ₁ sin θ) ² + (W ₁ cos θ) ² W ₁ ² (7) That is, the signal s9 proportional to the power of the input signal S _i is extracted from the calculator 53. This signal s9 is applied to the peak hold circuit 54 to hold its peak value. The output signal of the peak hold circuit 54 is added to the video filter 55 to remove noise, and further converted into an analog signal by the DA converter 56 to become a power signal having a spectrum waveform.

The low-pass filters 43 and 44 operate so as to remove the double frequency in the mixers 40 and 41, and also operate as an anti-aliasing filter, and further determine the widest frequency resolution bandwidth.

The digital filters 50 and 51 determine the frequency resolution of the spectrum analyzer. If this setting is the widest, the frequency resolution bandwidth of the low-pass filters 43 and 44 is matched, and the digital filters 50 and 51 become through. In other cases, the digital filters 50 and 51 determine the frequency resolution. As long as the clock is accurate, the digital filter has no deterioration in frequency characteristics (aging, temperature characteristics).
The frequency 2 _C of twice the cutoff frequency _C of the digital filters 50, 51 as shown in FIG. 2 is a frequency resolution bandwidth of the spectrum analyzer.

FIG. 3 is a block diagram showing a specific example of the peak hold circuit 54. In FIG. 3, 57 is the output signal of the calculator 53.
This is a latch circuit for latching s9, and in the initial state, it is cleared by the clear signal added from the frequency divider 58 which divides the output signal s1 of the reference frequency generator 34, and the content is zero. The output signal of the latch circuit 54 is a magnitude comparison circuit 59.
It is applied to one of the input terminals and is output to the video filter 55 in the next stage. The output signal s9 of the calculator 53 is applied to the other input terminal of the magnitude comparison circuit 59, and when the output signal s9 of the calculator 53 is larger than the output signal of the latch circuit 57, the latch signal is input to the latch circuit 57. Output to. As a result, the peak value of the output signal s9 of the calculator 53 is always latched in the latch circuit 57. The content of the latch circuit 54 is held until it is cleared by the clear signal applied from the frequency divider 58, and the cycle of the clear signal becomes the peak hold time constant.

In FIG. 1, the two digital filters 50 and 51, the calculator 53 and the video filter 55 are shown as separate components, but these are all modules that perform digital calculation, and some or all of them may be used if speed permits. You can share everything. That is, as long as it has a digital means capable of performing such a function, it does not have to have an independent configuration.

Further, depending on the application (for example, at low speed), the configuration after the AD converters 46 and 47 can be loaded into a processor (not shown) and processed by software.

Further, by utilizing the present invention, the phase difference θ between the oscillation signal of the oscillator 38 and the output signal of the BPF 30 [see the expressions (5) and (6)] can be known. An example of this circuit is shown in FIG. In FIG. 4, the circuit up to the digital filters 50 and 51 is the same as in FIG. Assuming that the output signal of the digital filter 50 is I and the output signal of the digital filter 51 is Q, a calculator 6 having a calculation function of tan ^-1 (I / Q) as shown in FIG.
If 1 is provided, the above-mentioned θ can be obtained as the output.

Furthermore, by combining FIG. 4 and FIG. 1, it is possible to measure the phase difference between the two introduced signals S _i and S _i ′. An example of this structure is shown in FIG.

In FIG. 5, 66 and 67 are signal processing circuits, and this block circuit is composed of the circuit of FIG. However, these two circuits 66 and 67 are configured to share the VCO 5 and the oscillators 36 and 38. From the output of the signal processing circuit 66, the phase difference θ ₁ between the input signal S _i and the output signal s2 of the oscillator 38 is obtained. Similarly, the phase difference θ ₂ between the input signal S _i ′ and the output signal s _{2 of the} oscillator 38 is obtained from the output of the signal processing circuit 67. Then, the subtracter 70 calculates the difference between θ ₁ and θ ₂ to obtain the phase difference θ ₃ between the input signals S _i and S _i ′.

With this configuration, since a digital filter is used as the resolution bandwidth filter, it is stable (small changes in temperature and aging) and the number of adjustment points is reduced, and a narrow band filter that is difficult to achieve with analog circuits is easy to implement. Can be realized.

Further, since the center is DC after mixing, the requirements regarding the conversion speed of the AD converter and the calculation speed of the digital filter are relaxed, and inexpensive AD converters and digital filters can be used.

Further, since the amplitude of the input signal is calculated by the sum of squares, the power of the input signal can be obtained only by the calculation time, high speed operation can be obtained, and the sweep speed can be improved.

In addition, since the mixer and the digital filter are used in two systems, noise between them and errors due to digital calculation cancel each other out, and the S / N resulting from this is Decrease to. That is, assuming that the noise between the two systems is uncorrelated and the power is equal, compared to the case where the signal processing is performed by only one system, Be improved.

If the S / N ratio for one system is S / N, the S / N ratio for two systems is From becoming become.

Furthermore, since the output signal of the arithmetic unit is added to the peak hold circuit and peak-held, the detection characteristic equivalent to the peak value detection can be obtained. As a result, the maximum value can be displayed instead of the effective value in a certain section.

Moreover, since the peak hold circuit is provided, CR
Display resolution of display such as T (frequency width per point)
The spectrum can always be displayed even if is wider than the resolution bandwidth. That is, when the display resolution is wide with respect to the resolution bandwidth, there are many observation points but the number of display points is small, and therefore a representative must be selected as one display point. At this time, if the final value of the corresponding section is selected, the peak may be missed, but the maximum value can be selected by configuring the present invention.

[Effects of the Invention] As described above, according to the present invention, a spectrum analyzer that is excellent in stability of a bandpass filter that determines frequency resolution, has few adjustment points, and can perform peak value detection at high speed is realized. it can.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration example of a spectrum analyzer according to the present invention, FIG. 2 is a diagram showing a relationship between a cutoff frequency of a digital filter and a resolution bandwidth of a spectrum analyzer, and FIG. 3 is a diagram showing the present invention. A block diagram of a specific example of a peak hold circuit used, FIG. 4 is a diagram showing a circuit example for obtaining a phase difference by using the present invention, and FIG. 5 is a configuration diagram for measuring the phase difference between two introduced signals. FIG. 6 is a diagram showing a configuration example of a conventional spectrum analyzer. 1,43,44 …… Low-pass filter, 3,11,40,41 ……
Mixer, 5 ... VCO (voltage controlled oscillator), 4,30 ...
BPF (band pass filter), 34 ... Reference frequency generator, 36, 38 ... Oscillator, 50, 51 ... Digital filter,
53 …… Calculator, 54 …… Peak hold circuit, 55 …… Video filter.

Claims (1)

[Claims] 1. A super-heterodyne spectrum analyzer in which a circuit of a mixer and a bandpass filter for introducing the mixer output is connected, and a frequency equal to a center frequency of a bandpass filter at a final stage having a predetermined bandwidth. , And two mixers that output two signals whose phases are different from each other by 90 °, two mixers that mix these two signals and the signal that has passed through the bandpass filter at the final stage, and the output terminals of these mixers. Two low-pass filters that are connected and limit the band of each mixer output by removing a frequency signal that is more than twice the center frequency of the last-stage band-pass filter, and are connected to the output terminals of these low-pass filters. Two A's that convert the output of the low-pass filter into a digital signal
A / D converters, two digital filter means connected to the output terminals of these A / D converters, the filter characteristics of which can be controlled by an externally applied control signal, and the sum of squares of the outputs of these digital filter means. A spectrum analyzer comprising: a calculation means for calculating and a peak hold means for holding a peak value of a calculation output of the calculation means.