JPH0661079B2 - Data processing device - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention is a dual-sided device that operates as a dedicated processing device that performs large-capacity data processing such as image processing at high speed, and sometimes as a general-purpose multifunctional processing device. The present invention relates to a data processing device having.

[Technical background of the invention and its problems]

In general, a general-purpose computer system as a data processing device has only one processing device or processing unit for performing calculations, except for input / output devices and peripheral devices. Therefore, if the amount of input data exceeds a certain value, it takes a long processing time even if a high-speed processing device is included. Currently, two methods are used to solve these problems.

The first method is the method shown in FIG.
1 is connected to the processing units 12, 13, 14, 15 for performing the arithmetic operation, and the data processing is executed in parallel in each of the processing units 12-15.

In this case, when the processing units 12 to 15 have the same function, the same processing is performed in parallel in each unit.

If the processing units 12 to 15 have different functions, the data to be processed are sequentially processed to the processing units 12, 13, 14, 15 via the bus 11.

This method enables multi-functional processing. In this case, the data is always input to the processing unit via the bus 11 and processed. Therefore, even if the processing speed of the data processing unit is increased, or even if the number of processing units is increased, it is dependent on the data transfer speed of the bus and is limited.

The second method is to connect the processing units 22, 23, 24, and 25 in series and sequentially perform data processing, as shown in FIG. The data processed by the processing unit 22 passes through the bus 26 and is processed by the next processing unit 23.
The data is processed by the bus 27, the processing unit 24, the bus 28, and the processing unit 25, and then the data flows while being processed.

Here, 21 is a control unit for controlling each of the processing units 22 to 25, and performs timing control of the data flow and the like with a control signal 29.

This method is generally called a pipeline method and is suitable for performing a certain fixed data processing at high speed, but has a drawback that it cannot be applied to versatile multi-functional data processing.

[Object of the Invention]

The present invention has been made in order to eliminate the above-mentioned conventional drawbacks, and an object of the present invention is to provide a data processing device capable of processing a large amount of data at high speed and with multiple functions and multiple days. .

[Outline of Invention]

In a data processing device according to the present invention, a plurality of four or more data processing units each having an arithmetic processing function of input / output data are arranged in a matrix, and adjacent units are connected by a first data bus. However, the first bus switching device is interposed in each of the first data buses, and the first bus switching devices adjacent to each other are provided with the second bus switching devices.
Data bus, and a second bus switching device is interposed at the intersection of each second data bus.
The bus path of the bus switching device is controlled to be switched.

Example of Invention

An embodiment of a data processing device of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the embodiment.

In FIG. 1, the processing units 32 to 35 having an arithmetic processing function are arranged in a matrix, and a bus switch 36 is connected between the processing units 32 and 33 via a bus 41. A bus switch 37 is connected between 32 and 34 via a bus 41.

Similarly, bus switches 40 and 39 are connected between the processing units 34 and 35 and between the processing units 33 and 35, respectively, via a bus 41. A bus switch 38 is connected between the bus switches 36 and 40, and between 37 and 39.

In addition, each processing unit 32 to 35, bus switcher 36 to 4
Each 0 is controlled by a control signal 42 from the controller 31.

Next, the operation of the data processing apparatus of the present invention configured as above will be described. As one operation of the processing units 32 to 35, the same processing as the conventional parallel processing method can be executed.

First, in the data input processing cycle, the bus switch 3
The data signal input from the left side of FIG.
The bus switches 36, 37, 38, 40 are switched so as to be led to the processing units 32, 34 by 7 and to the processing units 33, 35 via the bus switches 38, 36, 40, respectively. By controlling, the input data is supplied to the four processing units 32, 33, 34, 35, and each processing unit performs parallel processing.

Next, in the data output processing cycle, the processing data obtained in the processing units 32 and 34 are led to the bus switch 38 by the bus switches 36 and 40, respectively, and further from this bus switch 38 to the bus switch 39. Then, each bus switch 36, 38, 39, 40 is switch-controlled so that the bus switch 39 outputs the processed data obtained by the processing units 33, 35 to the right side in the drawing. This allows
It is possible to perform processing equivalent to that of the conventional parallel processing method, and to realize multi-functional processing.

It is also possible to execute the same processing as the conventional pipeline method.

First, the data input from the right side of the bus switch 37 in the figure is led to the processing unit 32 by the bus switch 37, and the processing result of this processing unit 32 is led to the processing unit 33 via the bus switch 36. The processing result of the processing unit 33 is led to the processing unit 35 via the bus switch 39, the processing result of the processing unit 35 is led to the processing unit 34 via the bus switch 40, and the processing of the processing unit 34 is performed. In order to derive the result to the left side in the drawing by the bus switching 37, the bus switching devices 36, 37, 39, 40 are controlled by appropriately adjusting the time. As a result, the input data is processed in the order of the processing units 32, 33, 35, 34, and data processing equivalent to that of the conventional pipeline method can be realized.

In this way, when the bus switches 36 to 40 can be independently switched and connected in any direction,
It can perform versatile multi-functional data processing, and also can perform dedicated high-speed data processing.

In addition, the controller 31 controls the bus switch 3 within one data processing period.
If the control for sequentially switching 6 to 40 is performed, multifunctional and high-speed data processing can be performed.

It should be noted that the data switching units 36 to 40 can be connected to any number of processing units, such as simultaneous connection to each processing unit or individual connection of each processing unit, depending on how much the function and performance of the data processing device are extended. You may be able to connect.

Further, the connection processing units 32 to 35 may be automatically and sequentially switched, or may be switched and connected by an instruction from the outside via the control unit.

Further, the number of processing units and the number of bus switches can be applied to any number of two or more.

〔The invention's effect〕

As described above, according to the data processing device of the present invention, a large number of processing units are organically and optimally connected to each other by switching control of the bus switcher, so that a large amount of data can be processed at high speed. It is versatile and versatile.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a data processing apparatus of the present invention, and FIGS. 2 and 3 are system diagrams of conventional data processing systems. 31 ... Controller, 32-35 ... Processing unit, 36-
40: Bus switcher.

Claims (1)

[Claims] 1. A plurality of four or more data processing units each having an arithmetic processing function of input / output data and arranged in a matrix, and between the units adjacent to each other among the plurality of data processing units. A plurality of first data buses connected to each other; a plurality of first bus switches respectively interposed between the plurality of first data buses and switching a bus path according to a control signal; A plurality of second data buses respectively connected between adjacent first bus switches of the first bus switch and a plurality of second data buses are interposed at the intersections of the plurality of second data buses and respond to a control signal. Data processing device including one or more second bus switchers for switching bus paths by a bus, and a controller for sending a control signal to the first and second bus switchers to switch and control the bus paths .