JPH0823883B2 - Video rate image processor - Google Patents

Description

The present invention relates to an image processor that executes image data processing for automation of visual inspection of products on a production line at a video rate, and frees calculation contents as inspection targets (contents) are diversified. With the object of providing a video rate image processor having the flexibility to be changed to various types, various arithmetic operations are performed under the control of a computer, and a plurality of arithmetic control means having a signal decoding means and a bus switching means and data are stored. A video rate image processor is constituted by a plurality of storage means having a signal decoding means and a bus switching means, an output bus switching means, and an equal number of local buses, a control bus, an input bus and outputs as the arithmetic control means.

[Industrial applications]

The present invention performs image data processing at a video rate for automation of visual inspection of products on a production line,
The present invention relates to improvement of an image processor.

Visual inspection in a production line is becoming more important, but with the diversification of inspection objects (contents), there is a demand for a video-rate image processor having the flexibility to freely change the operation contents.

[Conventional technology]

FIG. 5 is a block diagram of a conventional image processor.

In FIG. 5A, the product on the production line is imaged by the television camera 1, and the obtained analog image is converted into digital data by an analog / digital converter (not shown). This data is stored in the frame memory 3 for the input image by switching the switch 2 so that the switches a and b become conductive when necessary.

Alternatively, the switch 2 is switched so that a and c are conductive, and is input to the arithmetic modules 4-1 and 4-2 for convolution, which are connected in cascade and perform the product / sum operation. The result is input to the frame memory 5 for the output image, the data is stored and output as necessary.

The CPU (not shown) controls data input / output to / from the arithmetic modules 4-1 to 4-3, the frame memories 3 and 5, and the switch 2.

FIG. 5 (b) shows a case where the above-described two-stage convolution operation modules 4-1 and 4-2 are connected in parallel, and the operation principle is the same as the case of the cascade connection shown in FIG. 5 (a). Almost unchanged. In this way, automated visual inspection of products has been performed at video rates (~ 12 Mb / s).

[Problems to be solved by the invention]

However, when there are many types of inspection objects (contents), for example, in order to realize three-dimensional measurement of a wire rod as shown in FIG. 6, image frame difference calculation for extracting slit rays + convolution calculation + comparison calculation. , And logical operation between image frames to extract slit rays on a wire +
It is necessary to combine various operation modules such as isolated point removal (noise etc.) removal and select a frame memory. However, in the above video rate image processor, the processing route is fixed, so the corresponding processing However, there is a problem in that it is not flexible enough to change the operation contents freely.

Therefore, it is an object of the present invention to provide a video rate image processor having the flexibility to freely change the calculation contents.

[Means for solving problems]

According to the present invention, the above-mentioned problems are caused by a plurality of arithmetic control means and storage means each having a signal decoding means and a bus switching means, an output bus switching means, and a number equal to the number of arithmetic control means as an image data bus. A local bus, a control bus to which a control signal from the computer is input, an output bus, and an input bus are provided, and the output is connected to one of the corresponding local buses in the operation control means, and the other local buses are in the operation control. Connected to the input of the bus switching means of the means, all the local buses are connected to the input of the output bus switching means, and the outputs are connected to the output buses, and the bus switching means of the storage means is connected to the output bus from the output bus. An input is given and the output from the bus switching means is connected to the input bus, and the input bus is connected to each arithmetic control means. The control bus, which is connected to the input of the bus switching means and receives the control signal from the computer, is connected to all the arithmetic control means and the signal decoding means of the storage means. When the coincidence between the control signal number from the computer and the own machine number is decoded, the arithmetic processing is started, the bus switching means selects one of the corresponding inputs from the local bus and the input bus, and the output is the local bus. The output bus switching means selects any of the inputs from all the local buses, the output is output to the output bus, and the storage means outputs the signal decoding means from the computer via the control bus. When the match between the control signal and the own machine number is decoded, the bus switching means inputs from the output bus or to the input bus. Is solved by a video rate image processor, which is characterized by making the connections of the outputs of the.

[Action]

In FIG. 1, control signals from a computer (CPU) (not shown) via the control bus 800 are arithmetic control means 400-1 to 400-n and storage means 300-1 to 300-.
input to n. The arithmetic control means decodes the control signal by the built-in signal decoding means 420-1 to 420-n, and when the number designated by the control signal matches the machine number of the corresponding arithmetic control means, the arithmetic control means Perform a predetermined calculation. If necessary, in the storage means 300-1 to 300-n, the bus switching means 310-1 to 310-n switch to a predetermined bus, and the data from the storage means designated by the control signal Second input buses 900-1 to 900-n
Through a predetermined arithmetic control means.

Similar calculations are performed in other calculation control means. The results of the arithmetic operations performed by these arithmetic control means are input to the output bus switching means 600 via the first to nth buses 700-1 to 700-n as local buses.

The output bus switching means 600 performs input / output switching, and the resulting data is input and stored in a predetermined storage means via the first and second output buses 950-1 and 950-2.

In this way, the image data bus is divided into a local bus, an input bus and an output bus, one of the local buses is connected to the output side of the corresponding one arithmetic and control means, and the others are all connected to the input side. Therefore, all local buses are connected to the input side of the output bus switching means, and the output side is connected to the output bus.

On the other hand, the output side is connected to the input side of the bus switching means of the storage means, the output side is connected to the input bus, and all the input buses are connected to the bus switching means of the arithmetic control means.

Therefore, the bus switching means of the arithmetic control means only needs to switch the inputs from the local bus and the input bus, and does not need to switch the outputs. This is because the output from each arithmetic control means is given to one of the corresponding local buses, and the data from the local buses are collectively selected by the output bus switching means.

The output from the output bus switching means is given to the bus switching means of the storage means via the output bus, and the output from the bus switching means is given to the input bus. Therefore, the bus switching means of the storage means Need only switch the input from the output bus and the output to the input bus.

Therefore, the control of the arithmetic control means, the output bus switching means, and the bus switching means in the storage means becomes extremely simple.

As a result, it is possible to store the results of the arithmetic operations performed by the plurality of arithmetic control means in the storage means, and it is possible to easily realize arithmetic operations between arbitrary image data.

〔Example〕

FIG. 2 is a block diagram showing the configuration of the video rate image processor according to the embodiment of the present invention.

FIG. 3 is a circuit configuration block diagram of an address decoder used in the embodiment.

FIG. 4 is a circuit block diagram of the bus selector used in the embodiment.

 The same reference numerals denote the same objects throughout the drawings.

FIG. 2 shows the case of four types of arithmetic modules 40-1 to 40-4 as arithmetic control means and four types of frame memories 30-1 to 30-4 as storage means. The contents (calculation contents) of the calculation module are not particularly limited.

In this embodiment, as a local bus in the image data bus, LOOP-A is used as a bus for connecting arithmetic modules.
Bus-LOOP-D bus, and IN-A, IN-B, OUT-A, and OUT-B buses are provided as input and output buses for transferring data between the frame memory and the arithmetic module. are doing. Each arithmetic module is dedicated
It is connected to the LOOP bus. For example, the arithmetic module 40
-1 is a LOOP-A bus, 40-2 is a LOOP-B bus, 40-
3 is connected to the LOOP-C bus, and 40-4 is connected to the LOOP-D bus.

In addition, the IN-
The A and IN-B buses are used for image data input, and the OUT-A and OUT-B buses as output buses are used for image data output.

The control bus is composed of a frame memory and 8 bits for an address and 8 bits for a data for a board for setting the arithmetic module.

The configuration of the arithmetic modules and the address decoders 42-1 to 42-4 and 32-1 to 32-4 in the frame memory is the third.
Shown in the figure. In the control bus for address, the upper 4 bits are assigned to the board number and the lower 4 bits are assigned to the register number on the board. The board number is set by the DIP switch 33 installed on each board. Comparator 34
In, by comparing the upper 4-bit input A of the address control bus with the 4-bit data B set by the DIP switch 33, when they are equal,
This board is selected and outputs "H" level signal.

Next, the lower 4-bit data of the address control bus is input to the decoder 36 for decoding, and a strobe signal from a CPU (not shown) for latching the data is input through the inverter 35, The 4-bit decoded data is latched. When the "H" level signal is input from the comparator 34, the register having the number corresponding to the lower 4 bits of data installed on the board is selected. (In the present case, 5 registers 37-1 to 37
It is installed at -5. ) As a result, regardless of the position of the slot in which the frame memory is inserted in the housing in which the board is set, the CPU can change the data settings for all registers installed on the board by software. You can

The circuits of the bus selectors 41-1 to 41-4 in the arithmetic module are connected to a bus (for example, LOOP-A in the arithmetic module 40-1) connected to itself, as shown in FIG.
Bus other than LOOP-B, LOOP-C, LOOP-D,
Also, an arbitrary bus is selected from the IN-A and IN-B buses for image input from the frame memory.

For example, the arithmetic module 40-1 is an arithmetic circuit between image frames, 40-2 is convolution, and 40-3 is binarization.
Assuming that the comparison calculation and 40-4 are logic filter circuits, 40-1 is IN-A, 402- is LOOP-A bus, and 40-
If LOOP-B bus is selected in 3 and LOOP-C bus is selected in 40-4, the image difference + convolution + peak value / 2 value + isolated point removal processing that could not be realized in the past is performed once. At a video rate of ~ 12 Mb / s.

Next, the bus selector 31 in the frame memory on the board
-1 to 31-4 are IN-A, IN-B, OUT-A, and OUT-
It is a circuit for selecting input / output of the contents of the frame memory for each bus of B. Frame memory 30-1
IN-A, IN-B, OUT- for each of ~ 30-4
By controlling the input and output of data to and from the A and OUT-B buses, the contents of any frame memory can be processed and stored in any frame memory.

For example, if you want to find the difference between the image frames of the frame memories 30-1 and 30-2 and store the result in 30-3, turn on the gate (not shown) provided at the input of the arithmetic module 40-1. Then, the data in the frame memory 30-1 is input to the arithmetic module 40-1 via the IN-A bus. Further, the gate (not shown) provided at the input of the arithmetic module 40-2 is turned on, and the data in the frame memory 30-2 is input to the arithmetic module 40-2 via the IN-B bus. Then, in 40-1 and 40-2, the inter-frame difference calculation is performed, and the output is output to the LOOP-A bus and
Input to the output bus selector 60 via the LOOP-B bus. In the output bus selector 60, LOOP-A bus, LOOP-B
Inputs from the bus are connected to the OUT-A bus and the OUT-B bus, respectively, and input and stored in the frame memory 30-3.

In this way, calculation between arbitrary image data can be easily realized.

〔The invention's effect〕

As described above, according to the present invention, it is possible to easily change / add an arithmetic module and add a frame memory according to the purpose of use of the processor by changing the DIP switch on the board.

Further, the configuration of the arithmetic module and the selection of the frame memory can be flexibly performed by controlling the CPU.

Furthermore, the board position can be chosen independently of the slot position of the housing.

[Brief description of drawings]

1 is a principle diagram of the present invention, FIG. 2 is a block diagram showing a configuration of a video rate image processor of an embodiment of the present invention, FIG. 3 is a configuration block diagram of an address decoder circuit used in the embodiment, FIG. FIG. 4 is a circuit block diagram of a bus selector used in the embodiment, FIG. 5 is a block diagram of a conventional image processor, and FIG. 6 is a diagram showing a configuration of a wire rod three-dimensional measuring method as an example. . In the figure, 300-1 to 300-n are storage means, 400-1 to 400-n are arithmetic control means, 310-1 to 310-n, 410-1 to 410-n are bus switching means, 320-1 to 320 -N, 420-1 to 420-n are signal decoding means, 600 is output bus switching means, 700-1 to 700-n are first to nth local buses, 800 is control bus, 900-1, 900- Reference numeral 2 designates first and second input buses, and 950-1, 950-2 designates first and second output buses.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-60-159973 (JP, A) JP-A-62-14279 (JP, A) JP-A-61-156363 (JP, A)

Claims (1)

[Claims] 1. A plurality of arithmetic control means and storage means each having a signal decoding means and a bus switching means, an output bus switching means, and a number of local buses equal to the number of arithmetic control means as an image data bus. , A control bus to which a control signal from a computer is input, an output bus and an input bus are provided, and the output of the arithmetic control means is one of the corresponding local buses.
The other local buses are connected to the inputs of the bus switching means of the arithmetic control means, all the local buses are connected to the inputs of the output bus switching means, and the outputs are connected to the output buses. The input from the output bus is given to the bus switching means of the storage means, the output from the bus switching means is connected to the input bus, and the input bus is connected to the input of the bus switching means of each arithmetic control means. The control bus to which the control signal is input is connected to all the arithmetic control means and the signal decoding means of the storage means, and the arithmetic control means uses the signal decoding means and the number of the control signal from the computer through the control bus. When the matching machine number is decoded, the arithmetic processing is started and the bus switching means supports from the local bus and the input bus. Select one of the inputs, the output is output to the corresponding one of the local buses, the output bus switching means selects any of the inputs from all the local buses, and the output is output to the output bus, The storage means is characterized in that, when the signal decoding means decodes a match between the control signal from the computer via the control bus and its own machine number, the bus switching means connects the input from the output bus or the output to the input bus. Video rate image processor.