JPH0664117B2 - Transistor testing equipment - Google Patents

Description

TECHNICAL FIELD The present invention relates to a transistor testing device for testing an abnormality of a transistor or the like through a temperature change of an element.

[Summary of Disclosure] The present specification and the drawings provide a plurality of comparing means for comparing outputs from a circuit under test with a circuit unit including a circuit element corresponding to the circuit under test, and selected before and after energizing the circuit under test A technique for inspecting the state of a circuit element under test corresponding to the comparing means by measuring the output from one comparing means, and detecting an abnormality in a short time without destroying the circuit under test with a simple configuration. It is disclosed.

[Prior Art] When detecting an abnormality in a circuit element such as a conventional transistor, for example, thermal runaway, energize a circuit under test including the transistor and measure the temperature of the transistor to detect thermal runaway and a parameter that changes with temperature. Etc. were measured to judge the abnormality.

[Problems to be solved by the invention] However, in such a method, when thermal runaway of a transistor is detected, the measurement transistor and the circuit under test may be destroyed, and until an abnormality such as thermal runaway is detected. There was a problem that required a lot of time.

[Means for Solving Problems] In order to solve the above problems, the present invention applies a bias voltage to a plurality of transistors under test and reference transistors respectively corresponding to the plurality of transistors under test. Biasing means, first voltage detecting means for detecting the base-emitter voltage of each transistor under test, and second voltage detecting means for detecting the base-emitter voltage of each reference transistor, Comparing means provided for each set of the transistors under test and reference transistors for comparing the voltage detected by the first voltage detecting means and the voltage detected by the second voltage detecting means; Means for storing the comparison result from the comparing means, and the bias for each set of the transistor under test and the reference transistor. The comparison result from the comparing means before applying the bias voltage to the transistor under test and the reference transistor by the means is stored in the storage means, and the bias voltage is applied to the transistor under test and the reference transistor by the bias means. Switching means provided between each of the comparison means of each set and the storage means for storing the comparison result from the comparison means after application for a predetermined time, and a bias voltage stored in the storage means. And a test means for testing the temperature change of each of the transistors under test by comparing the comparison results by the respective comparing means before and after applying the voltage.

[Operation] According to the above configuration, the base-emitter voltages of the plurality of transistors under test and the transistors before and after applying the bias voltage to the corresponding reference transistors are compared for each group, and the comparison result is obtained. Based on the above, the temperature change of each transistor under test can be inspected to detect an abnormality of the transistor.

[Examples] The present invention will be described in detail below with reference to the examples shown in the drawings.

FIG. 1 shows a schematic configuration of the device of the present invention as a block diagram. Reference numeral 1 denotes a circuit under test, and the circuit under test 1 is configured as a circuit element to be tested, for example, an inverter. The connected transistor 1a is connected. The circuit under test 1 is connected to the abnormality detector 2.

The abnormality detection unit 2 includes resistors R1 to R9 and capacitors C1 to C3,
It is composed of a differential amplifier circuit composed of an operational amplifier Q2.

The negative input terminal of the operational amplifier Q2 is connected to the base of the transistor 1a of the circuit under test via the resistor R3, while the positive input terminal is connected to the ground via the resistors R4 and R6. The connection point between resistors R4 and R6 is transistor Q1.
Is connected to the base of, and this collector is connected to ground through a resistor R7.

This transistor Q1 has the same type and characteristics as the transistor under test 1a, and the resistors R7 and R6 connected to the collector and base of the transistor Q1 are resistors for satisfying the same conditions as the circuit under test. There is. Also the resistance R
Reference numerals 1 and R2 are resistors provided to apply the same bias voltage to the transistor under test 1a and the transistor Q1 of the same type as that. The output of the operational amplifier Q2 is output from the terminal 2a via the smoothing circuit including the resistor R8, the capacitor C2, the resistor R9, and the capacitor C3.

In this embodiment, a plurality of such abnormality detection units are provided,
One of them is shown in FIG. 1 as 2 '. This abnormality detecting section 2'has the same structure as the abnormality detecting section 2, and has a
.About.R17, capacitors C4 to C6 and a differential amplifier Q4. This differential amplifier Q4 includes a transistor under test 1 '
a and the transistor Q3 of the same type or characteristics as those of the transistor a, respectively, are compared with each other in the emitter-base voltage, and the difference is compared with the terminal 2'a.
Output to.

The outputs of the abnormality detection units 2 and 2'are input to the A / D converter 3 via the switches 8a and 9a driven by the relays 8 and 9, and then to the microcomputer 4. The microcomputer 4 compares the output obtained from the A / D converter 3, that is, the difference between the base-emitter voltages of the transistors 1a, 1'a and Q1, Q3 with a predetermined value, and the comparison result is compared with the predetermined value. When it becomes large, an abnormal signal is generated.

This abnormality signal is input to the display unit 5, and the abnormality is displayed there. The microcomputer 4 has resistors R18 to R21,
Relay drive unit 6 consisting of transistor Q5 and relay 6a
When the relay driver 6 receives a signal from the microcomputer 4, the transistor Q5 conducts, the relay 6a operates, and the switch 1b turns on, thereby energizing the circuit under test 1.

The relays 8 and 9 are operated by a microcomputer according to a predetermined sequence or program.

In such a configuration, the transistors under test 1a, 1a '
And the same type of transistor provided as a comparison reference
Q1 and Q3 are provided, and these circuit conditions and bias conditions are set to be the same so that high-precision measurement is performed. Further, the measurement is made by measuring the base-emitter voltage of both transistors 1a, 1'a and Q1, Q3 by a differential amplifier composed of operational amplifiers Q2, Q4. Since the voltage between the base and the emitter usually remarkably depends on the temperature, this voltage difference corresponds to the temperature difference.

The basic operation of measurement is as follows.

That is, first, the output of the abnormality detecting section 2 before the energization of the circuit under test including the transistors under test 1a, 1'a is switched to the switch 8
After passing through a and 9a, it is taken into the microcomputer 4 via the A / D converter 3 and the value is stored in the memory in the computer. Then, the microcomputer drives the relay drive unit 6 to turn on the switch 1b for a predetermined time to energize the circuit under test 1. Subsequently, the output of the abnormality detection unit 2 after completion of energization is taken into the microcomputer 4 and stored,
The outputs of the anomaly detectors before and after energization are compared, and when the difference between the two exceeds a predetermined value, an anomaly is notified, and by repeating this sequence several times, the temperature rises at fixed time intervals are measured or stored. I have to.

Next, a more detailed operation will be described with reference to the flowchart of FIG. First, in step S1, determination of abnormality, temperature measurement, output selection such as temperature rise curve at fixed time intervals,
Make initial settings such as input of measurement date and time and conditions. Then, in step S2, the output of the abnormality detecting section 2 before the circuit 1 under test is energized, that is, the difference between the emitter-base voltage of the transistor under test 1a and the emitter base voltage of the transistor Q1 is controlled by the microcomputer via the switch 9a and the A / D converter 3. 4 and store the value. Subsequently, in step S3, the relay driving unit 6 is operated for a predetermined time, and the switch 1b is turned on to energize the circuit under test 1 for a predetermined time to operate the transistor under test 1a. When a predetermined time has elapsed, the energization is stopped in step S4, and the output of the abnormality detection unit 2 is taken into the microcomputer 4 via the switch 9a and the A / D converter 3 in the same manner as before energization in step S5, and the output is measured. Remember. Then, in step S6, it is determined whether or not the measurement circuit by the initial setting is performed. That is, the above operation is performed a plurality of times when temperature data is obtained at regular time intervals, and if the number of times of measurement is not satisfied, steps S3 to S5 are repeated to perform a predetermined number of times of measurement.

Then, in step S7, another transistor 1'a
Also, it is determined whether or not to test. To test other transistors, in step S8, activate the relay 8 and deactivate the relay 9 to turn on the switch 8a.
Turn a off. Then, in steps S2 to S6, the output of the abnormality detection unit 2'is measured.

When an abnormality is detected, the values of the circuit under test before and after energization are compared to determine the abnormality. That is, as shown in FIG. 2, the abnormality detection unit output E rises as the energization time T elapses, but for example, the output change value of the abnormality detection unit is obtained during a predetermined time from t _{0 to} t ₁ , Compare with the set value.
For example, in the case of B, the output voltage at that time is E ₁ , and A is the output value E ₂ . This value is compared with a preset value, and if it exceeds a predetermined value, it is determined that, for example, thermal runaway has occurred, the result is displayed on the display unit 5 and an abnormality is determined (step S9).

Further, in the output of the measurement result, not only such an abnormality determination, but it may be desired to output the temperature of the transistor under test 1a or the data obtained by a plurality of measurements to a printer or a storage medium. These data are output to a printer or stored in a storage medium.

[Effects of the Invention] As described above, according to the present invention, a plurality of transistors under test and a base-emitter of a transistor before and after applying a bias voltage to each set of reference transistors corresponding to the transistors are tested. Since the voltage is compared for each group and the temperature change of each transistor under test is inspected based on the comparison result, a simple configuration allows a plurality of transistors to be tested in a short time without destroying the transistor under test. There is an excellent effect that an abnormality of the transistor under test can be detected.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall configuration of the circuit test apparatus according to the present invention, FIG. 2 is a characteristic diagram showing the relationship between the energization time and the output of the abnormality detection unit, and FIG. 3 is a flow chart diagram showing the flow of control. is there. 1 ... Test circuit 1a ... Transistor under test 2 ... Abnormality detection part, 3 ... A / D converter 4 ... Microcomputer 5 ... Display part, 6 ... Relay drive part 8, 9 ... Relay

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Satoshi Mori 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Hiroshi Mano 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon (72) Inventor Kazuyoshi Takahashi 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Tadashi Ishikawa 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. ( 72) Inventor Shunichi Komatsu 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Makoto Miura 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Hideki Adachi 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Hiroko Nishikawa 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. In Inc. (56) References Patent Sho 54-21147 (JP, A) JP Akira 58-83281 (JP, A)

Claims (1)

[Claims] 1. A bias means for applying a bias voltage to a plurality of transistors under test and reference transistors respectively corresponding to the plurality of transistors under test, and a voltage between a base and an emitter of each of the transistors under test. First voltage detecting means, second voltage detecting means for detecting the voltage between the base and emitter of each of the reference transistors, the voltage detected by the first voltage detecting means, and the second voltage detecting means Comparing means provided for each set of each of the transistors under test and each of the reference transistors to compare the detected voltage, a storage means for storing the comparison result from the comparing means, and each of the transistors under test and For each set of reference transistors, the biasing means applies a bias to the transistor under test and the reference transistor. The comparison result from the comparison unit before applying the ass voltage is stored in the storage unit, and the comparison result from the comparison unit after the bias voltage is applied to the transistor under test and the reference transistor for a predetermined time by the bias unit. Switching means provided between each of the comparison means of each set to store the comparison result in the storage means, and comparison results by each comparison means before and after applying the bias voltage stored in the storage means And a means for inspecting each of the transistors under test for temperature change.