JPH0664550B2 - Buffer memory control system - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a buffer storage control system, and is particularly suitable for a store-in system buffer storage commonly used by a plurality of central processing units, input / output processing units, and the like. Control system.

[Background of the Invention]

A system having a main memory and a buffer memory for holding a part of the data in the main memory, and a plurality of central processing units or input / output processing devices sharing the buffer memory is well known.
The store-in method is a method of storing write data only in the buffer storage when the corresponding block is in the buffer storage during the write operation.

In the store-in method, if the requested data is not in the buffer memory (not in BS), one block in the buffer memory is selected as a replacement target, and the block is stored in the past and the contents of the main memory are stored. If they are different, the block is written back to the main memory, and then one block containing the requested data is transferred from the main memory to the area where the block selected as the replacement target of the buffer memory was stored. If the block in the buffer memory selected as the replacement target has not been stored in the past and the content is the same as the main memory, the main memory is not written back to the main memory. Overwrites the block read from.

At this time, regarding the address array in which the address in the main memory of the data held in the buffer memory is registered, conventionally, until the required block is transferred from the main memory to the buffer memory and the address of the block is registered. In the meantime, the corresponding entry of the address array is invalidated so that the block that is the replacement target is not stored by another memory access request. This is to prevent the stored data from being lost by overwriting the block transferred from the main memory.

FIG. 3 shows an example of the configuration of the prior art, in which the buffer storage is shared by two central processing units (CPU1 and CPU2). In the figure, 101 and 102 are CPs, respectively
U1 and CPU2 are memory access address registers. A selector 103 selects a memory access request from either the CPU 1 or the CPU 2. 11
Reference numeral 0 is an address array for buffer storage, and in this example, a 4-row configuration is shown. 120 to 123 are compare circuits, 13
1 is a low address encoder, 132 to 133 are O
R gate, 140 is not in BS control logic, 150
Is a buffer storage address register, 151 is a buffer storage access permission signal register, and 160 is a buffer storage.

A timing chart for explaining the operation of FIG. 3 is shown in FIG. At timing 200, the memory access request of the CPU 1 is selected by the selector 103, a part of the address of the register 101 is indexed as a column address of the address array 110, and the remaining addresses are stored in the four entries read from the address array 110. The address is compared with the corresponding address in the compare circuits 120 to 123. Each entry of the address array 110 has a valid flag and indicates whether the address registered in the entry is valid or invalid. The compare circuits 120 to 123 are
The valid flag of each entry read from the address array 110 is used as an enable signal. At this time, when a match is detected by any of the compare circuits, the corresponding row address is generated by the encoder 131 and set in the register 150 as a part of the address in the buffer memory 160. or,
The buffer storage access permission signal is set to 151,
The buffer memory 160 is accessed at timing 201.

Next, at timing 210, the memory access request of the CPU 2 is selected, and as a result of indexing the address array 110 as in the case of the memory access request of the CPU 1, if no entry matches the entry, the not in BS control logic unit 140 Is activated. In the logic unit 140,
It is determined whether the replacement block needs to be determined and the replacement block needs to be written back to the main memory. If necessary, at timing 211, the buffer memory 160 is read to write back to the main memory. Further address array 11
Timing 21 due to 0 replacement block invalidation
At 2, the valid flag of the corresponding entry in the address array 110 is reset. The subsequent memory access request from the CPU 1 is selected at timing 221.

By the way, in the above-mentioned conventional technique, the time for invalidating the address array has a drawback that the address array cannot be indexed by another memory access request, resulting in a decrease in the throughput of the address array. As a conventional example of a system in which the buffer storage is shared by a plurality of processing devices, there is, for example, Japanese Patent Laid-Open No. 57-33473.

[Object of the Invention]

An object of the present invention is to provide a buffer storage control method for preventing a decrease in the throughput of an address array by not invalidating the entry of the address array corresponding to the block to be replaced when not in BS. Especially.

[Outline of Invention]

The present invention provides a register for holding the address of the block to be replaced when not in BS, until the required block is transferred from the main memory to the buffer memory and the block address is registered in the address array. , The address held in the above register is compared with the address of another memory access request, and if they match, the buffer memory is not accessed and the entry corresponding to the block that is the replacement target of the address array is invalidated. It does not need to be converted.

The address of the block to be replaced may be held in the register, either all the block addresses or some of them. Alternatively, the address on the buffer storage may be held. In comparison with the register, the memory access request may be limited to a store, or may be compared with any case of fetch store.

Example of Invention

FIG. 1 is a block diagram of an embodiment of the present invention, in which a column address save register 300, a column address compare circuit 301, and an OR gate 302 are added to the conventional configuration of FIG. FIG. 2 shows a timing chart for explaining the operation of FIG.

The memory access request of the CPU 1 is selected at timing 200, and the buffer storage 160 is accessed at timing 201, as in the case of FIG. At timing 210, the memory access request of the CPU 2 is selected, and as a result of indexing the address array 110, it does not match any of the entries, so not in the BS control logic unit 1
40 is activated, the control signal 310 causes the register 1
A part of the access request address 02 (the part corresponding to the column address of the address ares in this example) is stored in the save register 300. As in the conventional case, if the replacement block is determined and the writing back to the main memory is necessary, the reading from the buffer memory 160 is performed at the timing 211. In this case, since the operation of resetting the valid flag of the entry corresponding to the replace block of the address array 140, which is performed at the timing 212 of FIG. 4, is unnecessary, the subsequent memory access request of the CPU 1 is 1
The address array 110 is searched by being selected at the timing 320 which is early in timing. Furthermore, no CPU2
The control signal 311 keeps the truth value “1” until the main memory is read, the buffer memory 160 is written, and the address array 110 is registered by the memory access request that becomes t in BS. The column address part of the subsequent memory access request is compared by the compare circuit 301. Compare circuits 120-123
If a match is detected in any of the above and no match is detected in the compare circuit 301, the required data is stored in the buffer storage 16
Since it exists in 0 and is accessible, timing 321
The buffer store 160 can be accessed at. When the compare circuit 301 detects a match, the CPU2 no
Until the in BS processing is completed, the memory access request of the CPU 1 is waited in the register 101, and the CPU 2 not in
After the BS processing is completed, it is selected again.

〔The invention's effect〕

According to the present invention, when not in BS occurs, the address array corresponding to the replace block is not invalidated, so that the address array can be searched without waiting for the subsequent memory access request, and the throughput of the address array and thus the buffer storage. Throughput can be improved.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of FIG. 1, FIG. 3 is a configuration diagram showing a conventional technique, and FIG. 4 is a configuration diagram of FIG. 6 is a timing chart for clarifying the operation. 110 ... Buffer storage address array, 140 ... Not in BS control logic unit, 160 ... Buffer storage, 300 ... Column address save register, 301 ... Column address compare circuit.

Claims (1)

[Claims] 1. A buffer memory for holding a part of data in a main memory, and an address array for holding a main memory address of the data held in the buffer memory. In the control method, a register that holds the address of the block to be replaced when the required data does not exist in the buffer storage is provided, and the transfer of the block containing the required data from the main storage to the buffer storage and the transfer to the address array. A buffer storage control method characterized in that the access to the address array for the block held in the register is suspended and another access is accepted until the address registration is completed.