JPS6017134B2 - Storage device control method - Google Patents

Description

[Detailed description of the invention] The present invention relates to a storage device control method.

More specifically, the main memory (which consists of multiple blocks)
The present invention relates to a storage device control method in a data processing device that has an MS) and a buffer storage device that holds a copy of partial data of the MS in units of blocks. The data processing device has a small capacity and high speed compared to the MS, and if desired data exists in S, the data can be used from the BS at high speed.

If the desired data does not already exist, the block containing the data is transferred from the MS to the BS as a unit;
You can take advantage of this. When data is rewritten, if the block BS containing the data exists, the data in the BS is rewritten and the data in the MS is also rewritten. If a block containing the data does not already exist, only the data in the MS is rewritten. The BS is a copy of the MS, and the data held by the BS must match the data on the MS. However, if a rewrite request is made to the MS while a block is being transferred from the MS to the mother, a mismatch (inconsistency) may occur in the data between the MS and the BS. That is, while a block is being transferred, the data being transferred is already unregistered, so the data being transferred is B.
Since it is determined that the data does not exist in S, the data in the BS is not rewritten, but only the data in the MS is rewritten, resulting in an inconsistency in the data on the mother. FIG. 1 shows the relationship between Shigeru 1 and MS2. Now, if a block transfer request (BT in the figure) is issued to block 21 of MS2 in order to replace the contents of block 11 with BSI, the BSI
The contents of block 11 are
The contents of block 21 of S are rewritten. However, at this time, while the MS is processing the block transfer request, the MS
When there is a request (ST in the figure) to rewrite the contents of the same block 21 of No. 2, MS 2 processes this request after the ongoing block transfer process is completed. As a result, the contents of block 21 are rewritten from A to B. Note that regarding the contents of the blocks, the symbols A, B, and x are symbols of the data contents. Therefore, as a result of processing the above two requests, the content of block 21 of MS2 is B, whereas the BS corresponding to this block
The contents of block 11 of I become A, and a contradiction occurs in the data contents. Figure 2 shows a time chart during this period, and a store request that occurs between a block transfer request and a block replacement (already replacing from X to A) is processed by the MS after the block transfer request is processed. Therefore, the contents of the corresponding blocks of BS and MS are rewritten as X→A, A→B, causing a contradiction in the data contents.

The purpose of the present invention is to provide a storage device control method that does not cause discrepancies in the data contents of corresponding blocks of MSs even if there is a request to rewrite the same block of MSs during block transfer processing. be.

A feature of the present invention is that when a request to rewrite the same block of an MS during block transfer processing occurs, registration of data in the BS by this block transfer is suppressed.

FIG. 3 shows an embodiment of the invention. In this example, BP
The access request to MS35 generated by U32 is sent to Satoshibe 31.
It is assumed that a request to rewrite the MS 35 that is processed through the CH 33 and other BPUs 34 and is input to the patch unit 31 as a block cancellation request.

Here, the basic operations of the BS unit 31 and block cancellation are well known, and detailed explanations will be omitted. BPU3
The request for discussion to MS35 issued by 2 is from Shigebe 31
After the address is accepted by the request receiving unit 311 and stored in the address register (SAR) 312, the BS address array (BAA) and the BS access unit 313 and the BAA and BS 314 determine whether or not the data of the desired address exists in the BS. This can be determined by indexing the BAA. The BAA holds the address on the MS of the data block held by the mother. If the data you are looking for does not already exist,
Block transfer request issuing logic 315 initiates a block transfer to MS 35 . MS in response to this block transfer request.
When the block transfer processing logic 31 finishes the offer processing, the block transfer processing logic 31
Control is passed to 9, which issues a block replacement request to the BAA and block access unit 313, and rewrites a certain block in the BS with new content (block replacement).
At the same time, register the address with BAA. Here, during this series of block transfer processing, from the BPU 32 to the MS 3
According to the present invention, if the address of a data rewrite request to 5 or a block cancel request from CH 33 or other PU 34 matches the address of the block of this block transfer, block replacement by this block transfer is suppressed. The main point is that this is achieved as follows. Spotted area 3
1, when a block transfer request is issued to the MS35, the address is stored in the block transfer address register (B
FAR) 361. Thereafter, while this block transfer request is being processed by the MS 35 and the mother unit 31,
When the request reception unit 311 accepts the next 1'' quest, the SA is set to the address of that request.
A circuit 31 compares the contents of R312 and BFAR316.
Compare with 7. If a match is detected here, match bit 3
18, the block replace signal 3191 issued by the block transfer processing logic 319 is suppressed by the NOT circuit 3182 and the AND circuit 3192,
Block replacement request signal 3193 is prevented from being issued. Next, according to FIG.
The peripherals and block replacement request signal suppression logic will be explained. The address comparison circuit 3 1 7 is SAR 3 1
2 and the portion of the BFAR 316 excluding the intra-block address portion.

It is preferable for the address part to be compared to be as wide as possible in order to avoid unnecessary matching detection, but there is no particular restriction. However, in a device that involves address translation from a virtual address to a real address, the comparison must be made using real addresses.
The match output signal from B17 indicates that the quest request corresponds to the address then stored in SAR312.
Data rewrite request from PU32 to MS35 BPUST
, or block cancel requests OCHBC and BPUBC from the CH 33 and other BPUs 34, they are ORed by the OR gate 41 and ANDed by the AND gate 42, and set in the coincidence latch 318. Block replace signal 3191 connects latch 43 to indicate the end of a block transfer within block transfer processing logic 319.
is set by setting the output 3181 of the match latch 318 and the output of the NOT gate 3182 of the output 3181 of the match latch 318 and the AN
A D gate 3191 performs an AND operation to generate a block replacement request signal 3193. That is, match latch 318
In the state where is set, even if the block replace signal 3191 is set, the issuance of the block replace request signal 3193 is inhibited, and the registration of data to the BS is inhibited. Note that the delay latch 44 of the matching latch 43
It is reset by the output of Note that various other methods can be considered for this reset, such as resetting at the time of issuing the next block transfer request. In this embodiment, the IJ quest from the CH33 and the pond BPU34 is a block cancellation request, but in a so-called BS share configuration between CHs or BPUs that uses BS31 data, MS rewriting from these devices is required. The request can be handled in exactly the same way as the MS rewrite request from the BPU 32 in this embodiment, and the present invention does not depend on the ugly usage patterns of various devices.

Furthermore, as an alternative to the coincidence latch 3181, there may be a method in which the MS rewrite request address during block transfer processing is also saved and the comparison result is held, but this is not the only method.

According to the present invention, when there is a request to rewrite the same block in the MS during block transfer processing, it is possible to prevent mismatch in the data contents of the corresponding blocks in the BS and the MS by suppressing registration in the BS. can.

Furthermore, by increasing the number of comparison bits for address comparison as much as possible, strict comparison becomes possible, unnecessary inhibition of block replacement can be avoided, and spots can be used effectively.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the background that makes the present invention necessary, FIG. 2 is a diagram explaining the time relationship thereof, and FIG. 3 is a block diagram showing one embodiment of the present invention. FIG. 4 is a block diagram showing a part of FIG. 3 in detail.
31... Buffer storage device (Shigebe), 35...
. . . Main memory (MS), 317 . . . Comparison circuit, 319 . . . Block transfer processing logic. Figure 1 fist figure 2 figure 4 figure figure 3 figure

Claims (1)

[Claims] 1. In a data processing device that has a main memory device consisting of a plurality of blocks and a buffer memory device that holds a copy of some data in the main memory device in units of blocks, a block is transferred from the main memory device to the buffer memory device. If a request to rewrite the main storage device data occurs while data transfer processing is being performed in units, the main storage device address during the data transfer processing and the main storage device address of the rewrite request are compared, and if they match, the A storage device control method is characterized in that registration of transferred data in a buffer storage device due to the data transfer is suppressed.