JPH0664605B2 - Image processing device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an image processing apparatus that obtains encoded data of a composite image of first and second images different from each other.

<Prior Art> Conventionally, the image A shown in FIG. 2 is processed on the image B shown in FIG. 3 by processing such as rotation and scaling, and the image is synthesized to obtain a synthesized image shown in FIG. I needed equipment. Also, the time required for the treatment was extremely long.

<Object> In view of the above-mentioned drawbacks of the prior art, the present invention obtains encoded data of a composite image of different first and second images in a relatively short time and without having a large-capacity memory. An object of the present invention is to provide an image processing device capable of performing the above.

<Embodiment> In this embodiment, the background image A shown in FIG. 2 is combined with the image B shown in FIG. 3 while being rotated and scaled to form an image C shown in FIG.

First, the method of rotation will be described.

In FIG. 5, 21 is an image block corresponding to one encoded data, 22 is the main scanning direction of the result image (C), 23 is the sub-scanning direction of the result image (C), and 24 is the original image (A). The main scanning direction, 25 is the sub-scanning direction of the original image (A), and 26, 27, 28, 29 are the permutations of pixels to be written in the image as a result of approximating the main scanning of the original image. FIG. 5 (A) shows the original image rotated by 30 °, and FIG. 5 (B) shows the original image rotated by 45 °. In addition to this method, when block coding of image data is performed, for example, 4 × 4 divided by a dashed line in FIG.
Encoding is done in pixel block units.

FIG. 1 shows the first embodiment. In FIG. 1, 1 is a buffer memory for storing density data, 3 is a demodulator for demodulating density data of N × M pixels from encoded data,
4 is an encoder for encoding density data of N × M pixels, 5
Is a memory for storing encoded data, 6 is a converter for rotating an image, and 7 is an image data input device. In the process of rotating and superimposing the image B on the image A, first, an appropriate area of the image A stored in 5 is demodulated by 4 and stored in 1. An appropriate area of the image B input by 7 is rotated by 6 and combined on the memory of 1. When the combining process is completed, the data on 1 is encoded by 4 and written on 5. The above is repeated an appropriate number of times to obtain the image C to be obtained. A second embodiment in which FIG. 1 is further improved is shown in FIG.

FIG. 6 shows a second embodiment of the present invention, in which 1 is a 2 × N buffer for storing density data, 2 is a flag memory for storing buffers and flags for controlling a modulator / demodulator, and 3 is an encoding. Demodulator for reproducing density data of N × M pixels from data, 4 is a modulator for coding density data of N × M pixels, 5 is a memory for storing coded data, 6 is a converter for rotating an image, etc. , 7 are image data input devices. Now, it is assumed that the encoded data memory 5 stores data corresponding to the base image A shown in FIG. Further, for simplicity of explanation, it is assumed that N = M = 4 and that encoding is performed by 4 × 4 16 pixels. In this embodiment, the buffer memory is controlled in units of N × M pixels, so that modulation / demodulation and image conversion processing can be simultaneously performed in parallel.

FIG. 7 shows the relationship between the buffer memory position and the pixel address position, and 26, 27, 28, 29 are 26, 27, 28, 29 in FIG.
The corresponding pixel writing order is shown. The buffer memory is controlled for each block row. Figure 5A below
Will be described with reference to FIG. 6A. Writing for synthesizing is performed from pixels in the image block address (i + 1) row (n-1) column. After that, writing is done according to the line of 26. Looking at FIG. 7, it can be seen that the patterns of all the weed lines are the same. When the pattern 26 moves from the third point to the fourth point, the block address sequence (n-1) to sequence (n)
Move on to. At this time, the row address remains unchanged from (i) in FIG. 5 (A). In FIG. 7 (A) in which the second embodiment is performed, the transition also occurs when the point moves from the 11th point to the 12th point, and in this case, the 0th row (n + 1) th column to the 1st row (n + th).
2) It happens in a row. The pattern of this transition may be obtained in real time when converting the first pattern by the logic that writing is performed from the first row block of the buffer when the column always changes when converting the first line pattern, or it may be determined in advance. It is also possible to memorize it. At this time, the background image A is demodulated before being written,
The buffer block that stores the demodulated image data needs to transit in the order described above. Specifically, referring to FIGS. 5 and 1 of the first embodiment, the image block ( i + 1) row (n-1) column to buffer block 1 row (n-1) column, i row n column to 1 row n
Column, i row (n + 1) column to 1 row (n + 1) column, (i-
1) row (n + 1) column to row 0 (n + 1) column, (i-1)
The row (n + 2) columns are demodulated by the demodulator 3 into one row (n + 2) columns and stored in the data buffer 1. At this time, in this example, only (n + 1) columns need demodulation for two blocks, but the maximum number of blocks that need to be simultaneously demodulated for one column is two blocks. This is because the number of patterns that pass through one block is maximum when the pattern is tilted 45 ° with respect to the block, and the number of patterns at that time is seven. It is possible to modulate one block, write it to the coding memory, demodulate the next block and hold it. Moreover, since each column has blocks for two rows, pixel data up to a maximum of 8 patterns can be held, and thus buffering can be performed. This relationship is such that the maximum number of scanning patterns that enables writing of one block is (N + M−1) when the blocks are written in N × M pixel units, and data is held while this scanning occurs {(N + M− 1) / N + 1} block buffers are required. For simplicity, N = M = 4 is set now. The scanning pattern is 8 shown in FIG.
There is only a street. In each of the 8 patterns in FIG. 8, the last pixel to be written is the lower right pixel. Since the lower right pixel is written, modulation for coding may be performed. In addition, the block row (n
-1) is not written to the lower right pixel, but writing is not performed to this column (n-1) during this synthesizing process, so the column (n-1) that was saved after the continuous synthesizing process is completed. The data of -1) may be modulated and written. In order to control the above, the buffer is provided with a flag for each column. FIG. 9 is a diagram showing the relationship between the buffer memory and the flag memory. The flag memory stores the difference between the address of the 2-block buffer memory and the image block address. It will be described with reference to FIG. FIG. 9 (A) illustrates writing pixels according to the line 26 of FIG. 5 (A). Buffer block φ rows (n-1)
The image block (i) row (n-1) column data is stored in the column and the image block (i) row (n-1) column is stored in the image block (i).
The data in the (+1) th row (n-1) th column is demodulated. Below, the image block (i-
The image block (i) row (n) column is demodulated in 1) row (n) column and buffer block 1 row (n) column.

In general, these are the contents of the flag memory of the nth column F (n)
Then, the image block F in the column φ row n column is
The image block (F (n) +1) rows and n columns is demodulated into (n) rows and n columns and the buffer block 1 rows and n columns. After that, the image data to be overwritten is written in a raster form, and FIG. 9A shows a state after the image data of the raster 26 in FIG. 5A is overwritten.

The pixel data in the k-th row and the j-th column of the image block is written in the corresponding position of the buffer block mod2 (k-F (j))-th row and the j-th column. Here, mod2 (k) is a function that returns φ if k is even and 1 if k is odd.

In FIG. 9A, since the buffer block φ row (n−1) column and φ row (n + 1) column are written in the lower right pixel, they are coded, and are respectively i row (n−1) column and (i -1)
It is stored as an image block in row (n + 1) column. Further, FIG. 9B shows a state after the image data on the line 28 in FIG. 5A is overwritten. Since the lower right pixel in the 1st row and nth column of the buffer block is written, this block is encoded and stored as an image block of ith row and nth column. Generally, if the buffer block written in the lower right pixel has j rows and n columns, the encoded data is stored in the image block of {F (n) + j} rows and n columns. At this time, if j = 1, F (n) is updated so that the new F (n) becomes the value of the old F (n) plus 2, so that new rasters are input one after another. It can be done and processed.

FIG. 10 shows a circuit configuration example for realizing the above. In FIG. 10, 1 to 7 are the same as those in FIG. Reference numeral 101 is a comparator that selects a signal matching the lower right position from the signal 204 indicating the position in the block and outputs it as a signal 207, and 102 is an image row address signal 206 and an output signal 209 of the flag memory 2.
An address calculator that outputs the buffer row address from
103 has a buffer row address of 1, and the lower right pixel signal 207
Is an address updater that increments the contents of the flag memory corresponding to that column by 2. The image signal 201 and the synchronizing signal 202 which are input and digitized by the image input device 7 are input to the image conversion device 6. The image conversion device 6 performs image conversion processing during rotational scaling, and outputs pixel data 203, a pixel intra-block position signal 204, a block column address 205, and a block row address 206. The content 209 of the flag memory selected by the column address 205 and the row address 206 are calculated by the address calculator 102 (subtraction and the remainder of 2 in the above description) to become the data buffer row address 208 and the pixels in the data buffer along with other signals 204 and 205. The pixel data 203 is selected and written. At this time, comparator 1
It is determined by 01 whether or not the signal 204 is a signal indicating the lower right pixel, and is output as the signal 207. The modulator 4 receives this signal, encodes the block data 212 at this time, and outputs it as the encoded data 213. The encoded data memory stores the encoded data 213 in 2 bits.
Write to block address position of 05,206. The address updater 103 outputs a buffer row address 208 and a block position signal.
From 207, it is determined that the flag memory is rewritten, and the flag is updated. In the configuration example described above, 2 is added to the contents of the flag memory.

In the above, the density data was adopted as the pixel data, but this can only be used in correspondence with the data encoded in block units, and it may be luminance data or color signals in pixel units, or in pixel units. It may be encoded data. Further, in an actual circuit configuration, it is possible to have a buffer memory for three rows of blocks and store one block for an intermediate result at the time of encoding. At this time, it is conceivable that the configuration of the address calculator 102 and the flag updater 103 may be changed to a circuit for taking the remainder of 3 after subtraction and a circuit for adding 3, respectively, and how many rows of buffers may be required. The conversion can be performed by the difference in capability between the modulator / demodulators 3 and 4 and the image conversion device 6.

As explained above, by providing a buffer memory,
Image conversion processing can be performed on image data encoded on a block-by-block basis.By adding a flag memory that stores a flag for each block to the buffer memory, the image can be overwritten and combined with the encoded image data. Can be processed in real time. Further, since the synthesizing process is the raster order process, there is also an effect that the entire block can be modulated and demodulated by determining whether or not the pixel at the specific position in the block has been written.

<Effect> As described above, according to the image processing apparatus of the present invention, of the image data of the first image stored in the first storage unit,
The image data corresponding to the partial image composed of a plurality of blocks is decoded by the decoding means, combined with the second image input by the input means on the second storage means, and re-encoded by the encoding means, By repeating the processing operation to be stored in the first storage means to obtain encoded image data of a composite image of a plurality of images, it has a large-capacity memory in a relatively short time. It is possible to obtain the encoded data of the combined image of the first and second images that are different from each other.

[Brief description of drawings]

FIG. 1 is a block diagram of the image processing apparatus of the first embodiment, and FIGS. 2, 3, and 4 are explanatory diagrams of the image processing of this embodiment.
5 (A) and 5 (B) are diagrams showing raster order processing, FIG. 6 is a block diagram of the second embodiment, and FIGS. 7 (A) and 7 (B) are line buffers with limited raster order processing. FIG. 8 is a diagram showing the shape of the raster in the buffer when the process is performed in FIG. 8, FIG. 8 is a diagram showing the order in which the pixels in the block are filled, and FIG.
FIG. 10B is a diagram showing a processing procedure in the buffer memory,
The figure is a detailed circuit diagram of FIG.

Claims (1)

[Claims] 1. Encoding means for encoding given image data in block units of N × M pixels; first storage means for storing image data encoded by the encoding means; Decoding means for decoding the image data stored in one storage means, second storage means for storing a predetermined amount of the image data decoded by the decoding means, and image data for each pixel is input. Image data corresponding to a partial image composed of a plurality of blocks among the image data of the first image stored in the first storage unit, the image data being decoded by the decoding unit, The second input by the input means on the second storage means
It is configured to obtain coded image data of a composite image of a plurality of images by repeating the processing operation of synthesizing the same with the image of No. 1, re-encoding by the encoding unit, and storing in the first storage unit. An image processing device characterized by the above.