JPH0664865B2 - Truck counter - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording / reproducing apparatus for recording / reproducing information in the form of tracks on a recording medium, and more particularly to a track counter for counting the number of transverse tracks of a recording / reproducing head. is there.

2. Description of the Related Art When performing a high-speed track search on a recording medium that records and reproduces information in the form of tracks such as an optical disc, the speed of the recording / reproducing head movement is controlled by the number of traverse tracks, and the number of traverse tracks is the target. When the number of moving tracks matches, the recording / playback head is stopped.

When performing a track search in this way, when the tracking signal is lost due to defects or stains on the recording medium,
Alternatively, when an information signal on a recording medium such as a sector mark is mixed with a tracking signal, an error may occur in the number of cross tracks, and an accurate track search may not be performed.

Conventionally, as a countermeasure against such a count mistake,
An LPF (low-pass filter) was used as shown in FIG. (For example, Japanese Examined Patent Publication No. 57-3232) That is, the LPF 2 removes the high frequency component causing the count error from the tracking signal output from the tracking signal detector 1, and the counter 3 counts the number of traversing tracks. is there.

Problems to be Solved by the Invention However, when the recording / reproducing head is moved at a high speed, the frequency band of the tracking signal becomes wide, so that the tracking signal itself is damaged in the above configuration, and the tracking signal is lost. However, there was a problem that the effect could not be obtained.

In consideration of the above problems, the present invention provides a track counter that counts the number of crossing tracks accurately by suppressing a count error due to a missing tracking signal or mixing of unnecessary signal components.

Means for Solving the Problems In order to solve the above problems, the track counter of the present invention comprises a tracking signal detector, two operation modes of a synchronous output operation and a frequency holding operation, and two operation modes as necessary. It is composed of a signal processing circuit for switching the operation and a counter for counting the number of crossing tracks by the output of the signal processing circuit.

Effect of the Invention With the above configuration, the present invention inputs an output signal synchronized with a tracking signal to a counter that normally counts the number of crossed tracks, and outputs the frequency immediately before the tracking signal is lost or an unnecessary signal component is mixed. By inputting a signal, counting errors are suppressed and accurate cross track number counting is possible.

Embodiment One embodiment of the present invention will be described below with reference to the drawings.

1 and 2 are block diagrams showing a track counter in the first embodiment of the present invention.

In FIG. 1, 1 is a tracking signal detector, 2 is a signal processing circuit, and 3 is a counter. The signal processing circuit 2 includes a phase comparator 21, an LPF 22, a sample hold circuit 23, a voltage controlled oscillator 24, and a switching control circuit 25.

FIG. 2 is a block diagram showing the configuration of the switching control circuit 25. 26 and 27 are cycle counters, 28 is a latch circuit, and 29 and 30.
Is a subtractor, 31 and 32 are comparison value registers, 33 and 34 are comparators,
Reference numeral 35 is a flip-flop, and 36 is an adder.

The operation of the track counter configured as described above will be described below with reference to FIGS. 1 and 2.

First, FIG. 1 shows an outline of the operation.

A tracking signal is generated by the tracking signal detector 1.

The output of the switching control circuit 25 switches between the sample operation and the hold operation of the sample hold circuit 23. During the sampling operation of the sample-hold circuit 23, the signal processing circuit 2 uses a PLL (phase-locked loop) including the phase comparator 21, the LPF 22, and the voltage-controlled oscillator 24 to output a signal synchronized with the input tracking signal to the counter 3 , And the signal processing circuit 2 performs a synchronous output operation. During the hold operation of the sample-hold circuit 23, the voltage held by the sample-hold circuit 23 causes
The voltage controlled oscillator 24 outputs a signal holding the frequency at the start of the hold to the counter 3, and the signal processing circuit 2 carries out the frequency holding operation.

The operation of the switching control circuit 25 for switching the synchronous output operation / frequency holding operation will be described with reference to the block diagram shown in FIG.

The cycle counter 26 detects the current cycle of the tracking signal 102, converts it into a digital signal for each cycle, and subtracts it from the subtracter 29.
Send to. The previously detected cycle is latched by the latch circuit 28 and sent to the subtractor 29, which is the absolute value of the difference from the current cycle.
201 is calculated. The absolute value of the difference 201 is calculated by the comparator 33 as
Compared with the comparison value 202 set in the comparison value register 31,
When the absolute value 201 of the difference is equal to or larger than the comparison value 202, the switching control signal 103 which is the output of the flip-flop 35 is set.
By setting the switching control signal 103, the sample hold circuit 23 switches to the hold operation, and the signal processing circuit 2
Performs frequency maintenance operation.

The adder 36 sums the previously detected cycle 205 and the comparison value 202, and outputs the sum as the control value of the cycle counter 26. The cycle counter 26 stops counting when the count value reaches the limit value, and outputs the count value at that time as a cycle.

The cycle counter 27 detects the held cycle from the output signal 101 of the signal processing circuit 2, converts it into a digital signal for each cycle, and sends the digital signal to the subtractor 30. In the subtracter 30, the cycle of the current tracking signal , The absolute value of the difference 203 is calculated.
The absolute value 203 of the difference is calculated by the comparator 34 in the comparison value register 32.
When the absolute value 203 of the difference is equal to or smaller than the comparison value 204, the switching control signal 103 which is the output of the flip-flop 35 is reset. When the switching control signal 103 is reset, the sample hold circuit 23 switches to the sampling operation, and the signal processing circuit 2 performs the synchronous output operation.

Since the frequency change of the tracking signal corresponds to the physical speed change of the recording / reproducing head, the speed of change is limited. Therefore, when the frequency of the tracking signal suddenly changes beyond its limit,
Alternatively, it is regarded as a disturbance due to mixing of unnecessary signals. Assuming that the change in the moving speed of the recording / reproducing head during the occurrence of the disturbance can be ignored, the count error can be suppressed by holding the frequency input to the counter during the occurrence of the disturbance. The PLL itself also has a frequency holding effect against disturbances such as missing and mixing, but if the disturbance lasts for a long period of time, it will eventually follow the input, so the effect of the PLL alone is insufficient as an effect of suppressing count errors.

The timing chart of each signal is shown in FIG. Here, the cycle is counted from the interval of the rising edges of the pulse. As a result of the missing of the tracking signal 102, at timing 301, it is detected that the difference between the current cycle of the tracking signal 102 and the previously detected cycle is equal to or more than a set value, and the switching control signal 103 is set to be missing. After the recovery from the above, at timing 302, it is detected that the difference between the cycle of the tracking signal 102 and the cycle of the signal holding the frequency is equal to or less than the set value, and the switching control signal 103 is reset. Similarly, as a result of the high-frequency signal being mixed in the tracking signal 102, at time 303, it is detected that the difference between the cycle of the tracking signal 102 and the cycle previously detected exceeds a set value, and the switching control signal 103 is set. Then, after recovering from the mixing of the high frequency signal, at timing 304, it is detected that the difference between the cycle of the tracking signal 102 and the cycle of the signal holding the frequency is less than or equal to a set value, and the switching control signal 103 is reset. is doing.
As a result, the output signal 101 of the signal processing circuit 2 becomes a signal having a fixed cycle, and counting errors are prevented.

As described above, according to the present embodiment, a tracking signal detector, a signal processing circuit having two operation modes of a synchronous output operation and a frequency holding operation, and switching between the two operations depending on the frequency of the input / output signal, and the signal processing By providing a counter for counting the number of crossing tracks by the output of the circuit, a counting error can be suppressed and an accurate count of crossing tracks can be made when the tracking signal is defective or an unnecessary signal component is mixed.

A second embodiment of the present invention will be described below with reference to the drawings.

FIG. 4 is a block diagram showing a switching control circuit in the configuration of the track counter for explaining the second embodiment of the present invention.

In FIG. 4, 26 is a cycle counter, 28 is a latch circuit,
29 is a subtractor, 31 is a comparison value register, 33 is a comparator, and 36 is an adder. The above is the same as the configuration of FIG.

The difference from the switching control circuit shown in FIG. 2 is that the switching control signal is reset by the monostable multivibrator 37 regardless of the cycle comparison.

The operation of the switching control circuit 25 configured as above will be described below with reference to FIG.

The operation when switching from the synchronized output operation to the frequency holding operation is the same as the operation in the first embodiment. That is, when the absolute value 201 of the difference between the current cycle of the tracking signal and the previously detected cycle is equal to or greater than the comparison value 202, the switching control signal 103 is set by the output of the comparator 33, and the signal processing circuit 2 determines the frequency. Hold operation is performed.

After a lapse of a fixed time after switching to the frequency holding operation, the monostable multivibrator 37 causes the switching control signal 103
Are reset and the signal processing circuit 2 switches to the synchronous output signal.

In an optical disc or the like, the above configuration is effective when the lack of a tracking signal does not pose a problem and only the mixing of unnecessary signal components such as sector marks poses a problem. The influence of unwanted signal components mixed by the sector mark and the address mark is limited to a certain time width, and the change in the moving speed of the recording / reproducing head during that period can be ignored. Therefore, by detecting the sector mark and the address mark, switching to the frequency holding operation, and after a certain period of time, the synchronous output operation is resumed, it is possible to prevent the sector mark and the address mark from affecting the tracking signal.

As described above, according to this embodiment, the switching from the frequency holding operation to the synchronous output operation is performed by the monostable multivibrator 37.
By doing so, the track counter according to the present invention can be realized with a simple structure.

In each embodiment, the period is detected and then converted into a digital signal, and addition / subtraction and comparison are performed by a logic circuit.
It is also possible to calculate and compare analog signals as they are.

Effects of the Invention As described above, the track counter of the present invention includes a tracking signal detector, a signal processing circuit that switches between two operations as necessary, that is, a synchronous output operation and a frequency holding operation, and a signal processing circuit. By providing a counter for counting the number of traversing tracks by the output of the processing circuit,
When a tracking signal is missing or an unnecessary signal component is mixed in, a count error is suppressed and an accurate number of traverse tracks can be counted.

[Brief description of drawings]

FIG. 1 is a block diagram showing a track counter in the first and second embodiments of the present invention, FIG. 2 is a block diagram of a switching control circuit in the first embodiment, and FIG. 3 is a tracking signal and a switching control signal. , And a timing chart showing changes in the output signal of the signal processing circuit, FIG. 4 is a block diagram of a switching control circuit in the second embodiment,
FIG. 5 is a block diagram showing an example of a conventional track counter. 1 ... Tracking signal detector, 2 ... Signal processing circuit,
3 ... Counter, 21 ... Phase comparator, 22 ... LPF, 23 ...
… Sample and hold circuit, 24… Voltage controlled oscillator, 25…
... Switching control circuit.

Claims (1)

[Claims] 1. A tracking signal detector for detecting a track crossing of a recording / reproducing head to generate a tracking signal, a synchronous output operation for outputting a signal synchronized with the tracking signal, and a frequency holding for outputting a signal of a stored frequency. When the tracking signal frequency has increased or decreased by a predetermined value or more within a predetermined time, the tracking signal frequency before the increase or decrease is stored as the output frequency of the frequency holding operation and the frequency holding operation starts from the synchronous output operation. When the difference between the frequency of the tracking signal and the stored frequency becomes less than a predetermined value, the number of crossing tracks is changed by the signal processing circuit that switches from the frequency holding operation to the synchronous output operation and the output of the signal processing circuit. A track counter comprising: a counter for counting.