JPH0664914B2 - Programmable monolithic integrated circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable monolithic integrated circuit, and more particularly to a programmable read-only memory (hereinafter
The present invention relates to a decoder circuit of a programmable monolithic integrated circuit in which information is written by making each memory cell of PROM) conductive (short circuit) or non-conductive (open) by a current.

[Conventional technology]

Generally, a PROM is composed of an address inverter, a decoder, a memory cell, an output buffer, a programming circuit, etc. The memory cell is connected to each intersection of the word line and the bit line, and the emitter / base is generated by the heat generated by the write current. It is classified into a junction breakdown type in which a junction is short-circuited or a fuse type in which evaporated metal or polycrystalline silicon is blown by a write current.

In such a programmable monolithic integrated circuit, it is necessary to reduce the size of the memory cell section and simplify and reduce the size of the decoder circuit as the storage capacity increases.

FIG. 2 is a diagram showing a circuit example of a conventional programmable monolithic integrated circuit, particularly a junction breakdown type PROM.

In FIG, Gate1～Gate4 inverter, the address signals A0 and A1, L1 to L4 bus line, 1 decoder _circuit, Q 1 to Q ₃ are _transistors, R 1 to R ₅ are resistors, D
_{1 to} D ₃ are diodes, 2 is a memory cell portion, and Q _{1 1 to} Q
₁ n to Qm _{1 to} Qmn are (m × n) memory cells, WL _{1 to} W
Lm indicates a word line, and DL _{1 to} DLn indicate bit lines. First, the write operation of this circuit will be described by taking as an example the case where the emitter-base junction of the memory Q _{1 1} of the memory cell section 2 is short-circuited to write information. Address signals A0 and A1 are
When applied to te1 and Gate3, bus line L1~L4 is set to a level corresponding to the signal level of the A ₀ and A _1. That is, if A ₀ is LOW level and A ₁ is LOW level, L ₁ is High.
Level, L ₂ is LOW level, L ₃ is High level, L ₄ is LOW
It becomes a level. In the decoder circuit in which the word line WL ₁ to which the memory cell Q _{1 1} to be selected is connected is connected, the cathodes of the diodes D ₂ and D ₃ acting as the input are the address signal line L ₁
Are connected to L ₃ and L ₃ and both are at a high level, the diodes D ₂ and D ₃ are turned off and a current is supplied from the power supply V _CC to the base of the transistor Q ₁ through the resistor R _1. Therefore, the transistor Q ₁ is turned on, which turns on the transistors Q ₂ and Q ₃ , that is, WL ₁ is selected. The write current of about 200mA at this time to the memory cell _{Q 1 1 LD 1 -Q 1 1} -Q flowed at ₃ and GND path, shorting the emitter-base junction of the memory cells _{Q 1 1,} writes. At this time, a base current of a magnitude sufficient to absorb a write current of about 200 mA flows through the final stage transistor Q ₃ of the decoder circuit, and the base current of the transistor Q ₃ is supplied by the transistors Q ₁ and Q _2. There is.

Next, the read operation of this circuit will be described with respect to the memory cell Q _{1 1} in which information is written as described above. Information can be read by detecting whether or not a current flows through the memory cell Q _{1 1.} Therefore, it is not necessary to supply a large current to the bit line as in the above writing. That is, when reading, LO to A ₀
Although the low level is applied to the W level and A ₁ , the diodes D ₂ and D ₃ are turned off and the transistors Q ₁ , Q ₂ and Q ₃ are turned on, which is the same as in the writing, but the bit line DL ₁ and word line WL ₁ is 0.5mA which is much smaller than that at writing
The extent of the read current flows through a path of _{DL 1 -Q 1 1 -Q 3 -GND} . At this time, the diode D _1, which was in the OFF state because WL ₁ was at a high potential at the time of writing, read WL ₁ at the time of reading.
There turned on because of low potential, the base current of Q ₂ to which is supplied via the R ₂ from V _CC is less than the time of writing, hence the base current also 0.5mA current about Q ₂ 'WL ₁
The current is small enough to pull in more.

That is, in a PROM in which the write current and the read current differ greatly from each other, such as 200 mA and 0.5 mA, the base current of the transistor Q ₃ that pulls in the read current during reading is
If a base current of a magnitude sufficient to draw the write current of 200 mA during writing is passed, the base current becomes excessive, the transistor Q ₃ saturates, and excess charge is accumulated in the base, turning off Q ₃ . In this case, the off-time becomes longer, which makes it unsuitable for high-speed operation. Therefore, in order to prevent this, a conventional decoder circuit is provided with a feedback circuit having a diode D ₁ so that appropriate base currents are supplied to Q ₃ at the time of writing and at the time of reading.

[Problems to be solved by the invention]

However, provision of such a feedback circuit complicates the circuit configuration and is not preferable for high integration of the circuit. Further, as is apparent from FIG. 2, the feedback circuit has to cross the wiring of the transistor Q ₂ in order to connect the collector of the transistor Q _{1 and} the collector of the transistor Q ₃ via the diode D ₁ , and the wiring is complicated. There was also a drawback such as. Of course, it is possible to switch the power supply Vcc between writing and reading without providing such a feedback circuit, but since the power supply Vcc is a voltage supplied to not only the decoder but also other circuits, There is a limit to switching in consideration of many circuit designs.

[Means for solving problems]

An object of the present invention is to provide a programmable monolithic integrated circuit which solves the above-mentioned drawbacks of the prior art and has a simple circuit configuration and can be highly integrated. A feature of the present invention is that in a programmable monolithic integrated circuit in which information is written by making each memory cell conductive or non-conductive, an inverter circuit portion in a decoder circuit connected to a word line has a collector and a emitter to a word line. The base of the first transistor connected to GND is connected to the emitter of the second transistor, the collector of the second transistor is connected to the cathode of the diode,
In the configuration in which the anode of the diode is connected to the collector of the first transistor, the word line is at a low potential at the time of reading, the diode is in an off state, and the first transistor supplies a sufficient current for drawing the read current. It may be supplied by a transistor that supplies the base current of the second transistor so that it flows to the base of the transistor. During writing, the word line is at a high potential, so the diode is in the ON state and part of the write current is in the second collector. , And the current supplied to the base of the second transistor, together with the current supplied to the base of the second transistor, is sufficient to supply the first transistor with sufficient current to draw most of the write current.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. First
The drawing shows one embodiment of a programmable monolithic integrated circuit according to the present invention, in particular, a decoder circuit in which word lines WL ₁ are connected, and the same reference numerals as those in FIG. 2 denote the same elements.
Although the memory cells with Q _{1 1} or less are not shown,
Exists as in the figure.

This embodiment is characterized in the first transistor to Q ₁ 2 Figure the transistor Q diode D ₁ is connected between the collector of ₂ and transistor resistance R ₃ connected between the collector and the current Vcc of Q ₂ showing a conventional example lost, connecting the collector of the transistor Q ₂ to the cathode of the diode D _5, there anode of the diode D ₅ collector of the transistor Q _3, i.e. that connected to the word line WL _1. The resistor R ₆
Is a transistor that helps high speed operation when the transistor Q ₃ turns off.
llup resistance and diode D ₄ are resistance R of write current during writing
It is to prevent it from flowing into the power supply Vcc through ₆ . In such a circuit, since the word line WL ₁ is at a low potential during reading, the diode D ₅ is turned off, and the current flowing from Vcc through the resistor R ₁ and the current flowing from Vcc through the resistor R ₂ are the transistors. is supplied to the base of Q _3, draw 0.5mA about the read current from WL ₁ is turned oN transistor Q _3. On the other hand, when writing, the word line
Since WL ₁ is at a high potential, the diode D ₅ is turned on, and the current supply to the base of the transistor Q ₂ is the same as that at the time of reading, but part of the write current is diode D ₅
A current of about 200 mA can be drawn by the transistor Q ₃ by flowing into the collector of the transistor Q ₂ through the base current and flowing into the base of the transistor Q ₃ together with the base current of the transistor Q ₂ .

As described above, according to the present invention, in the programmable monolithic integrated circuit for writing information by setting each memory cell into a conductive state or a non-conductive state, a decoder circuit connected to a word line has a collector connected to the word line. The emitter is
The base of the first transistor, which is connected to GND, is connected to the emitter of the second transistor, the collector of the second transistor is connected to the cathode of the diode, and the anode of the diode is the collector or word line of the first transistor. Since the connected configuration eliminates the need for a feedback circuit for switching the base current of the final stage transistor of the decoder circuit between writing and reading,
A programmable monolithic integrated circuit having a simple circuit configuration and a mask design at the time of manufacturing and a high degree of integration can be obtained, and the effect of the present invention is great.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing an example of a conventional programmable monolithic integrated circuit. Q _{1 to} Q ₃ ... Transistor, D _{1 to} D ₅ ... Diode, R _{1 to} R ₆ ... Resistor, Q _{1 1 to} Q ₁ n to Qm _{1 to} Qmn
...... memory cell, Gate1~4 ...... inverter, WL ₁ ~WLm
...... Word line, DL _{1 to} DLn …… bit line

Claims (1)

[Claims] 1. A programmable electrically writable device
In a monolithic integrated circuit, a grounded-emitter first transistor having a collector connected to a word line, a second transistor having an emitter connected to the base of the first transistor, and an anode connected to the word line. Programmable monolithic integration characterized in that it has a diode whose cathode is connected to the collector of the second transistor and means for supplying a base current to the base of the second transistor when selecting the word line. circuit.