JPS6138558B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to monolithic integrated circuits.

Recently, various types of programmable read-only memory (hereinafter abbreviated as P-ROM) have been developed. Among these, the so-called juncture-type P-ROM, which uses a transistor as a memory element for 1 and 0 depending on whether or not there is a juncture burn-in (short circuit) between the base and emitter, does not require the nichrome or other forms of the usual fuse type, but instead is a normal bipolar type. It is attracting attention because the process can be applied. In particular, in the method of using open-base transistors as storage elements, the base-collector diode can be used as is as a decoupling diode for the storage element array, and the collector can be shared in the row direction, so insulation is required in the row direction. Not needed.

By the way, as P-ROMs, like general LSIs, continue to increase in capacity, the chip size will increase and the speed will only slow down if only conventional technology is applied, so it is necessary to reduce the unit area per element. It is essential to introduce new processes such as reduction of wire width and wiring width, and this introduction makes it possible to provide a large-capacity, high-speed P-ROM.

Now, in the above-mentioned juncture type P-ROM, the writing mechanism can be considered as follows. In other words, a certain large current (for example, 200 mA) is selectively applied to each element for a certain period of time by breakdown between the base and the emitter to generate a positive potential between the emitter and the collector, and the emitter rises due to the local temperature rise caused by the heat generated. This is done by shorting the emitter junction by forming a spike in the side contact metal (aluminum).

Therefore, if a new process with a small element area as described above is introduced for the memory element, the current required for writing can be reduced compared to the conventional one (for example, 100 mA). Furthermore, writing to such a small-area memory element with the same large current (eg 200 mA) as in the past tends to impair its breakdown voltage because the collector junction is located much closer to the emitter junction than in the past.
Further, if the write current is reduced, it is even more convenient because the element area of the row and column driver circuits that handle this current can be reduced. However, it is undesirable to change the specifications of the P-ROM writing device itself in order to change (reduce) the write current because compatibility with components with conventional characteristics will be lost.

SUMMARY OF THE INVENTION An object of the present invention is to provide an integrated circuit with write current compatibility.

The integrated circuit according to the present invention has a bypass circuit inside the monolithic integrated circuit for bypassing a part of the write current, so that the write current can be reduced by using a conventional writing device as is and supplying a desired small write current to the memory element. It is characterized by being made to flow.

The present invention will be described below with reference to the drawings. First, P-ROM has a write-only terminal.
An example of a write circuit is shown below.

Referring to FIG. 1, Z ₁ ,...Zm are column drive circuits for writing, and open-base transistors Qx ₁ y ₁ ...
Qx ₁ ym...Qxny ₁ ...Qxnym indicate (mxn) memory cells, _X1 ...Xn indicate row lines, and _Y1 ...Ym indicate column lines. Here, for example, the transistor
Assuming that Qx ₁ y ₁ is selected, when a large current according to the specifications of a conventional writing device is passed through the write-only terminal 1, the write drive circuit Z is made conductive, and a large current flows into the transistor Qx ₁ y ₁ , and writing is performed. However, as mentioned above, the collector juncture is destroyed or the withstand voltage is lowered.

Next, one embodiment of the present invention will be described with reference to FIG. The write circuits Z ₁ to Zm are the same as those shown in FIG. 1, and in the present invention, a bypass circuit 2, that is, a constant current source 2 is newly provided inside. When a large current flows into the write-only terminal 1, a portion of the large current initially flows into the constant current source 2, and the current obtained by subtracting the large current flowing into the constant current source from the large current, that is, the small current, is obtained using the example shown in Figure 1. , the write drive circuit Z ₁ is made conductive,
The current flows into the selected memory cell Qx ₁ y ₁ , and writing is performed using a small current. Therefore, by providing a constant current source internally as a bypass circuit, when writing to a memory cell whose unit area has become smaller due to the introduction of a new process, it is possible to write with a large current as specified by the P-ROM writing device. Since the collector junction is very close to each other, the problem of easily damaging its withstand voltage is eliminated, and in P-ROMs with write-only terminals, the small current required to write to the memory cell, which has become smaller per unit, can be applied to the memory cell. It can be poured.

Next, a specific example of the present invention will be shown in a P-ROM in which a write-only terminal is shared with an output terminal.

Referring to FIG. 3, the gain of the write column drive circuit or PNPN path consisting of transistors Q ₉ and Q ₁₀ is determined by the gain of transistors Q ₅ and Q ₆ and transistors
The gain is greater than the gain of the PNPN circuit composed of Q ₇ and Q ₈ , and the P-
When a large current is applied according to the specifications of the ROM writing device, transistors Q ₉ and Q ₁₀ of bypass circuit 2
The gain of the PNPN circuit consisting of the transistor
Since the gain is larger than the gain of the PNPN circuit composed of Q ₅ and Q ₆ and Q ₇ and Q ₈ , a part of the highest current conducts the PNPN path composed of transistors Q ₀ and Q ₁₀ ,
Flows into the power transistor Q ₁₁ . For example, if gates 4, 6, and 7 are set to high level and gates 5, 8, and 9 are set to bottom level, the memory cell
Considering the case where Q ₁ is selected, the current obtained by subtracting the current flowing into transistor Q ₁₁ of bypass circuit 2 from the large current, that is, the small current, flows through the transistor
The PNPN circuit composed of Q ₅ and Q ₆ is made conductive, and the flow flows into the selected memory cell Qx ₁ y ₁ , and then into the conductive transistor Q ₁₂ . Therefore, when writing to memory cells whose area per unit has become smaller due to the introduction of a new process, conventional P-
If you write with a large current according to the specifications of the ROM writing device, the collector junction is very close to each other, so there is no problem of easily damaging its withstand voltage.
In ROM, it is possible to flow the small current required to write into a memory cell whose area per unit has become smaller.

As explained above, the present invention provides a bypass circuit for bypassing a portion of the large current flowing from the write terminal in a P-ROM in which the area per transistor and wiring have been reduced due to the introduction of a new process. The write current of the memory cell can be performed with a small current, and the P-ROM
Large capacity without changing the specifications of the writing device.
We can provide high-speed P-ROM,
The effects of the present invention are enormous. In addition, fuse type P
- Similarly, by providing the bypass circuit of the present invention inside the ROM, a part of the write current can be bypassed, and writing to the memory cell can be performed with a small current. The present invention can be applied and the effects are enormous.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing a conventional P-ROM having a dedicated write terminal, Fig. 2 is a circuit diagram showing a P-ROM according to an embodiment of the present invention, and Fig. 3 is a circuit diagram showing the above-mentioned embodiment. FIG. 2 is a circuit diagram showing a specific example. _Z1 to Zm...Write circuit, 1, 11...Write terminal, 2...Bypass circuit, _Q5 to _Q12 ...Transistor, _Qx1y1 to _Qxnym ...Memory cell, _D1 to _D4 ...Diode.

Claims (1)

[Claims] 1. In an integrated circuit including an electrically writable fixed memory element and its programming circuit, only a part of the write current flowing into the fixed memory element is bypassed and flows to the fixed element. A programmable monolithic integrated circuit characterized by having a bypass circuit that reduces the amount of current. 2. The integrated circuit according to claim 1, wherein the fixed memory element is constituted by a bipolar transistor with an open base.