JPH0664964B2 - Switch input circuit - Google Patents
Switch input circuitInfo
- Publication number
- JPH0664964B2 JPH0664964B2 JP63167097A JP16709788A JPH0664964B2 JP H0664964 B2 JPH0664964 B2 JP H0664964B2 JP 63167097 A JP63167097 A JP 63167097A JP 16709788 A JP16709788 A JP 16709788A JP H0664964 B2 JPH0664964 B2 JP H0664964B2
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- circuit
- switch
- resistance value
- converter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
Landscapes
- Input From Keyboards Or The Like (AREA)
- Keying Circuit Devices (AREA)
- Analogue/Digital Conversion (AREA)
- Logic Circuits (AREA)
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明はスイッチ入力回路に関するものである。The present invention relates to a switch input circuit.
［従来の技術］ 従来は、例えばプリンタにおいては、モードスイッチや
種々の設定スイッチ等多数のスイッチを必要とし、各ス
イッチの状態を読み取るために、１つのスイッチに１つ
の入力ポートを割り当てている。[Prior Art] Conventionally, for example, a printer requires a large number of switches such as a mode switch and various setting switches, and one input port is assigned to one switch in order to read the state of each switch.
［解決しようとする課題］ 上記従来のものでは、スイッチの数だけ入力ポートが必
要となり、回路が大型化してしまうものであった。[Problems to be Solved] In the above-mentioned conventional device, as many input ports as the number of switches are required, and the circuit becomes large.
本発明は１本の入力端子で２つのスイッチの状態を読み
取れるスイッチ入力回路を提供することを目的としてい
る。An object of the present invention is to provide a switch input circuit capable of reading the states of two switches with one input terminal.
［課題を解決するための手段］ 本発明は抵抗値が所定の関係にある４つの抵抗と、２つ
のスイッチと、ADコンバータとにより構成した回路を用
い、上記２つのスイッチの開閉状態の組合わせによって
上記ADコンバータの入力電圧値を異ならせるようにして
上記課題を解決するものである。[Means for Solving the Problem] The present invention uses a circuit constituted by four resistors having a predetermined resistance value, two switches, and an AD converter, and combines the open / closed states of the two switches. The above problem is solved by making the input voltage value of the AD converter different by.
［実施例］ 以下、本発明の一実施例を図面に基づいて説明する。[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.
第１図において、１は入力端子の電圧Ｖを２ビットの出
力Q1、Q2に変換するADコンバータである。２は第１の抵
抗、３は第１のスイッチであり、これらが直列に接続さ
れて第１の回路４が構成される。５は第２のスイッチ、
６は第２の抵抗であり、これらが直列に接続されて第２
の回路７が構成される。第２の抵抗６は第１の抵抗２の
抵抗値のほぼ２分の１の抵抗値を有し、例えばそれぞれ
を2kΩ、1kΩに設定してある。。さらに第１の回路４と
第２の回路７とが直列に接続されて第４の回路８が構成
される。９は第１の抵抗２の抵抗値よりも十分に大きい
抵抗値、例えば1MΩの第３の抵抗、10は第３の抵抗９の
抵抗値のほぼ２倍の抵抗値、例えば2MΩの第４の抵抗で
あり、これらが直列に接続されて第３の回路11が構成さ
れる。また、本例においては電源VCCは5vである。In FIG. 1, reference numeral 1 is an AD converter for converting a voltage V at an input terminal into 2-bit outputs Q 1 and Q 2 . Reference numeral 2 is a first resistor, 3 is a first switch, and these are connected in series to form a first circuit 4. 5 is the second switch,
6 is a second resistor, which are connected in series
Circuit 7 is configured. The second resistor 6 has a resistance value that is approximately ½ of the resistance value of the first resistor 2, and is set to 2 kΩ and 1 kΩ, respectively, for example. . Further, the first circuit 4 and the second circuit 7 are connected in series to form a fourth circuit 8. 9 is a resistance value sufficiently larger than the resistance value of the first resistor 2, for example, a third resistance of 1 MΩ, 10 is a resistance value almost twice the resistance value of the third resistor 9, for example, a fourth resistance of 2 MΩ. A resistor, which is connected in series to form the third circuit 11. Further, in this example, the power supply V CC is 5v.
つぎに動作を説明する。第１のスイッチ３と第２のスイ
ッチ５の開閉状態と、その各組合せのときの電圧Ｖおよ
びADコンバータ１の出力Q1、Q2の状態を第２図に示す。Next, the operation will be described. FIG. 2 shows the open / closed states of the first switch 3 and the second switch 5, and the states of the voltage V and the outputs Q 1 and Q 2 of the AD converter 1 in each combination thereof.
第１のスイッチ３と第２のスイッチ５の両方が開いた状
態のときには、第３の抵抗９と第４の抵抗10の抵抗値の
比が約1:2なので電圧Ｖは約3.3vとなる。このときADコ
ンバータ１からはQ1に“1"、Q2に“0"が出力される。When both the first switch 3 and the second switch 5 are open, the ratio of the resistance values of the third resistor 9 and the fourth resistor 10 is about 1: 2, so the voltage V is about 3.3v. . "1" to Q 1 is from the AD converter 1 at this time, the Q 2 "0" is output.
第１のスイッチ３が閉じ第２のスイッチ５が開いた状態
のときは、第４の抵抗10の抵抗値は第１の抵抗２の抵抗
値よりも十分に大きいので、第１の抵抗２は無視するこ
とができ電圧Ｖは約5.0vとなる。このときADコンバータ
１からはQ1に“1"、Q2に“1"が出力される。When the first switch 3 is closed and the second switch 5 is open, the resistance value of the fourth resistor 10 is sufficiently larger than the resistance value of the first resistor 2, so that the first resistor 2 is It can be ignored and the voltage V is about 5.0v. At this time, the AD converter 1 outputs “1” to Q 1 and “1” to Q 2 .
第１のスイッチ３が開いて第２のスイッチ５が閉じた状
態のときには、第３の抵抗９の抵抗値は第２の抵抗６の
抵抗値よりも十分に大きいので第２の抵抗６は無視する
ことができ電圧Ｖは約0vとなる。このときADコンバータ
１からはQ1に“0"、Q2に“0"が出力される。When the first switch 3 is open and the second switch 5 is closed, the resistance value of the third resistor 9 is sufficiently larger than the resistance value of the second resistor 6, so that the second resistor 6 is ignored. The voltage V becomes approximately 0v. The Q 1 is from the AD converter 1 at this time "0", the Q 2 "0" is output.
第１のスイッチ３と第２のスイッチ５の両方が閉じた状
態のときには、第３の抵抗９および第４の抵抗10の抵抗
値は第１の抵抗２および第２の抵抗６の抵抗値より十分
大きいので、第３の抵抗９および第４の抵抗10は無視で
き、電圧Ｖは第１の抵抗２と第２の抵抗６の抵抗値の比
で決まる。第１の抵抗２と第２の抵抗６の抵抗値の比は
約2:1なので電圧Ｖは約1.7vとなる。このときADコンバ
ータ１からはQ1に“0"、Q2に“1"が出力される。When both the first switch 3 and the second switch 5 are closed, the resistance values of the third resistor 9 and the fourth resistor 10 are smaller than those of the first resistor 2 and the second resistor 6. Since it is sufficiently large, the third resistor 9 and the fourth resistor 10 can be ignored, and the voltage V is determined by the ratio of the resistance values of the first resistor 2 and the second resistor 6. Since the ratio of the resistance values of the first resistor 2 and the second resistor 6 is about 2: 1, the voltage V is about 1.7v. The Q 1 is from the AD converter 1 at this time "0", the Q 2 "1" is output.
以上の動作により、１つのADコンバータによって２つの
スイッチの状態を読み取ることができる。With the above operation, the state of two switches can be read by one AD converter.
［効果］ 本発明によれば、１つのADコンバータによって２つのス
イッチの状態を読み取れるものである。２つのスイッチ
の開閉状態の組合せは４通りであるが、この各組合せの
ときADコンバータの入力電圧値がそれぞれ異なるように
回路を構成してある。しかも、上記各組合せのときのAD
コンバータの入力電圧値は、電源の電圧値をａとする
と、ほぼ０、ａ／３、2a／３、ａというように、電源電
圧が均等に分割されるように各抵抗の抵抗値を定め、回
路を構成したので、抵抗値の誤差等の影響を受けにく
く、２つのスイッチの状態を１つのADコンバータで間違
いなく読み取ることができる。[Effect] According to the present invention, the states of two switches can be read by one AD converter. There are four combinations of open / closed states of the two switches, and the circuit is configured so that the input voltage value of the AD converter is different for each combination. Moreover, AD for each of the above combinations
As for the input voltage value of the converter, assuming that the voltage value of the power supply is a, the resistance value of each resistor is set to be approximately 0, a / 3, 2a / 3, a so that the power supply voltage is divided evenly. Since the circuit is configured, the states of the two switches can be reliably read by one AD converter without being easily affected by the resistance value error and the like.
また、ポート数の削減によってICの数またはICの端子数
を削減することができ、回路の小型化、コスト低減、信
頼性向上に大きく貢献するものである。Further, by reducing the number of ports, the number of ICs or the number of IC terminals can be reduced, which greatly contributes to circuit size reduction, cost reduction, and reliability improvement.
第１図は本発明の一実施例を示した電気回路図、第２図
は第１図の回路における各スイッチの状態とADコンバー
タの出力状態を示した説明図である。 １……ADコンバータ ２……第１の抵抗 ３……第１のスイッチ ４……第１の回路 ５……第２のスイッチ ６……第２の抵抗 ７……第２の回路 ８……第４の回路 ９……第３の抵抗 10……第４の抵抗 11……第３の回路FIG. 1 is an electric circuit diagram showing an embodiment of the present invention, and FIG. 2 is an explanatory diagram showing the state of each switch and the output state of the AD converter in the circuit of FIG. 1 ... AD converter 2 ... 1st resistance 3 ... 1st switch 4 ... 1st circuit 5 ... 2nd switch 6 ... 2nd resistance 7 ... 2nd circuit 8 ... Fourth circuit 9 ... Third resistor 10 ... Fourth resistor 11 ... Third circuit
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０３Ｍ 11/24 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H03M 11/24
Claims (1)
の抵抗と、 第１の抵抗の抵抗値よりも十分に大きい抵抗値をもつ第
３の抵抗と、 第３の抵抗の抵抗値のほぼ２倍の抵抗値をもつ第４の抵
抗と、 第１のスイッチと、 第２のスイッチとを有し、 第１の抵抗と第１のスイッチとを直列に接続して第１の
回路を構成し、 第２の抵抗と第２のスイッチとを直列に接続して第２の
回路を構成し、 第３の抵抗と第４の抵抗とを直列に接続して第３の回路
を構成し、 第１の回路と第２の回路とを直列に接続して第４の回路
を構成し、 第３の回路と第４の回路を電源間に並列に接続し、 第１の回路と第２の回路の接続点および第３の抵抗と第
４の抵抗の接続点を接続し、 この接続端子を上記ADコンバータの入力に接続したこと
を特徴とするスイッチ入力回路。1. An AD converter, a first resistor, and a second resistor having a resistance value that is approximately one half of the resistance value of the first resistor.
Of the first resistor, a third resistor having a resistance value sufficiently larger than the resistance value of the first resistor, a fourth resistance having a resistance value approximately twice the resistance value of the third resistor, And a second switch, the first resistor and the first switch are connected in series to form a first circuit, and the second resistor and the second switch are connected in series. Connect to form a second circuit, connect a third resistor and a fourth resistor in series to form a third circuit, and connect a first circuit and a second circuit in series. A fourth circuit, the third circuit and the fourth circuit are connected in parallel between the power supplies, and the connection point of the first circuit and the second circuit and the third resistor and the fourth resistor are connected. A switch input circuit in which a connection point is connected and the connection terminal is connected to the input of the AD converter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63167097A JPH0664964B2 (en) | 1988-07-05 | 1988-07-05 | Switch input circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63167097A JPH0664964B2 (en) | 1988-07-05 | 1988-07-05 | Switch input circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0218821A JPH0218821A (en) | 1990-01-23 |
| JPH0664964B2 true JPH0664964B2 (en) | 1994-08-22 |
Family
ID=15843369
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63167097A Expired - Fee Related JPH0664964B2 (en) | 1988-07-05 | 1988-07-05 | Switch input circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0664964B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2776105B2 (en) * | 1992-01-07 | 1998-07-16 | 三菱電機株式会社 | Electronic device and method for supplying power to electronic device |
| JP2006134608A (en) * | 2004-11-02 | 2006-05-25 | Omron Corp | Switch state detection circuit and automotive window opening and closing device |
-
1988
- 1988-07-05 JP JP63167097A patent/JPH0664964B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0218821A (en) | 1990-01-23 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |