JPH0666322B2 - Method for manufacturing heterojunction bipolar transistor - Google Patents

Description

The present invention relates to a method for manufacturing a heterojunction bipolar transistor.

[Conventional technology]

In recent years, active research and development have been advanced toward higher integration and higher speed of semiconductor devices. In particular, a bipolar transistor (hereinafter referred to as H
(BT) is attracting attention as a device having high gain and high speed performance because the emitter injection efficiency can be kept high even if the base is heavily doped.

However, in order to realize an HBT with high gain and high speed and high frequency characteristics, the device structure is usually formed by self-alignment and miniaturization technology, and parasitic parameters such as base-emitter capacitance, base-collector capacitance, and base resistance are set. Need to reduce.

FIG. 3 is a cross-sectional view showing the structure of a conventional heterojunction bipolar transistor, in which a p-GaAs base layer 3 and an n-AlGaAs emitter layer are formed on an n-GaAs collector layer 2 formed on a semi-insulating GaAs substrate 1. 4 are each provided in a self-aligned mesa shape. This transistor structure has an uppermost n layer formed on a substrate.
-The AuGe emitter electrode 45 is formed on the AlGaAs layer using a mask having a predetermined pattern, and the mesa-shaped emitter layer 4 is further formed by the wet etching method, and then the AuZn base electrode 33 is self-aligned with the emitter mesa. Of the p-Ga layer formed underneath
The As layer is also selectively etched to form a mesa-type base layer 3 and finally exposed n-GaAs collector layer 2
It is made by forming an AuGe collector electrode 22 on the top.

[Problems to be solved by the invention]

As described above, the conventional HBT is structurally weak because the emitter mesa is formed by wet etching. Especially, when the area of the emitter mesa is small, the emitter electrode is peeled off by the side etching effect of the emitter mesa. Occurs. Although such an HBT has a self-aligned structure, it is practically impossible to miniaturize the emitter / mesa, that is, to reduce the base / emitter capacitance. The current situation is that we cannot expect

In view of the above problems, it is an object of the present invention to provide a method for manufacturing a fine self-aligned heterojunction bipolar transistor having a mesa-shaped emitter layer that does not peel off in the emitter electrode.

[Means for solving problems]

A method of manufacturing a heterojunction bipolar transistor according to the present invention comprises a step of preparing a semi-insulating substrate, a first semiconductor material layer on which a collector layer, a base layer and an emitter layer are to be formed on the semi-insulating substrate, and a second semiconductor material layer. Semiconductor material layer and third
The step of sequentially stacking the semiconductor material layers, the step of depositing an emitter electrode metal layer on the entire surface of the third semiconductor material layer, and the step of forming the emitter electrode metal layer and the third semiconductor material layer into a second layer. Forming the emitter electrode and the mesa-shaped emitter layer selectively reaching the semiconductor material layer, and ion implantation is performed substantially perpendicularly to the side surface of the mesa-shaped emitter layer at an angle not shaded by other adjacent mesas. A step of increasing the resistance of the side surface of the mesa-shaped emitter layer, and a step of forming a metal film in a self-aligned manner on the second semiconductor material layer using the laminated film of the emitter electrode and the mesa-shaped emitter layer as a mask pattern, Forming a mesa-shaped base layer for selectively removing the second semiconductor material layer by etching to expose a predetermined region of the first semiconductor material layer; and the first semiconductor material layer. Selectively collector electrode metal material film on the exposed region comprising a collector electrode forming step of depositing.

〔Example〕

 Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor chip showing an embodiment of a heterojunction bipolar transistor manufactured by the manufacturing method of the present invention. According to the present embodiment, the heterojunction bipolar transistor of the present invention comprises a semi-insulating GaAs substrate 1
A collector layer 2 made of n-GaAs, a base layer 3 made of p-GaAs, a mesa-shaped emitter layer 4 made of n-AlGaAs, and a semiconductor layer formed on these semiconductor layers. The emitter and collector electrodes 45 and 22 made of AuGe and AuZ
It includes a base electrode 33 made of n, and a high resistance layer 8 on the side surface of the emitter formed by implanting ions into the side surface of the mesa-shaped emitter layer 4.

[Action]

Thus, the high resistance layer 8 on the side surface of the emitter formed by ion implantation into the emitter layer can reduce the effective area of the mesa-shaped emitter and the base-emitter capacitance without reducing the mechanical strength of the emitter electrode. Therefore, high-speed high-frequency characteristics excellent in HBT can be easily imparted.

2 (a) to (d) show the heterojunction bipolar device of the present invention.
FIG. 6 is a process sequence diagram showing an example of a method for manufacturing a transistor. According to this embodiment, a semi-insulating GaAs substrate 1 is first prepared, and then a collector layer 2 made of n-GaAs and p-GaAs are provided on the semi-insulating GaAs substrate 1.
A layer 36, an n-AlGaAs layer 46, and an emitter electrode metal layer 44 made of AuGe are sequentially formed.

[See FIG. 2 (a)]. Next, as shown in FIG. 2 (b), a mask 5 is provided, and the metal layer 44 for the emitter electrode and the n-AlGaAs are formed by argon ion milling and reactive ion etching (RIE) techniques.
Layer 46 is selectively removed until it reaches the underlying p-GaAs layer 36, forming emitter electrode 45 and mesa emitter layer 4, respectively. Here, as shown in FIG. 2 (c), the side surface of the formed mesa-shaped emitter layer 4 is substantially perpendicular to the side surface of the mesa at an angle not shaded by another mesa (not shown) adjacent thereto. The high resistance layer 8 is provided on this side surface by injecting hydrogen ions H ⁺ into. Then, as shown in FIG.
The base electrode 33 made of Zn is formed in self alignment with the mesa-shaped emitter layer 4.

Finally, the masks 5 and 9 are removed, and the p-GaAs layer 36 is further removed.
Is selectively etched to expose a predetermined portion of the n-GaAs collector layer 2, the p-GaAs base layer 3 is formed, and a collector electrode 22 made of AuGn is provided. A junction bipolar transistor is obtained.

〔The invention's effect〕

As described in detail above, according to the present invention, the mesa type emitter layer is formed by the dry etching method, and by implanting hydrogen ions into this side surface, the high resistance layer is formed on the side surface of the emitter mesa. Since the effective area of the emitter mesa is reduced by forming the structure, the base-emitter capacitance is significantly reduced compared to the conventional structure, and there is no problem of exfoliation of the emitter electrode. It is possible to obtain a transistor.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor chip showing an embodiment of a heterojunction bipolar transistor manufactured by the manufacturing method of the present invention, and FIGS. 2A to 2D are manufacturing methods of the heterojunction bipolar transistor of the present invention. 3 is a sectional view showing the structure of a conventional heterojunction bipolar transistor. 1 ... semi-insulating GaAs substrate, 2 ... n-GaAs collector layer, 3 ... p-GaAs mesa base layer, 4 ... n
-AlGaAs mesa type emitter layers, 5, 9 ... Mask,
8: high resistance layer, 22: AuGe collector electrode, 33
... AuZn base electrode, 36 ... p-GaAs layer, 4
4 ... AuGe emitter electrode metal layer, 45 ... AuGe
Emitter electrode, 46 ... n-AlGaAs layer.

Claims (1)

[Claims] 1. A step of preparing a semi-insulating substrate, and a first semiconductor material layer, a second semiconductor material layer and a third semiconductor material layer on which a collector layer, a base layer and an emitter layer are to be formed on the semi-insulating substrate. The step of sequentially stacking the semiconductor material layers, the step of depositing an emitter electrode metal layer on the entire surface of the third semiconductor material layer, and the step of forming the emitter electrode metal layer and the third semiconductor material layer into a second layer. Forming the emitter electrode and the mesa-shaped emitter layer selectively reaching the semiconductor material layer, and ion implantation is performed substantially perpendicularly to the side surface of the mesa-shaped emitter layer at an angle not shaded by other adjacent mesas. A step of increasing the resistance of the side surface of the mesa-shaped emitter layer, and a self-alignment forming of a metal film on the second semiconductor material layer using the laminated film of the emitter electrode and the mesa-shaped emitter layer as a mask pattern. Electrode forming step, a mesa-shaped base layer forming step of selectively etching away the second semiconductor material layer to expose a predetermined area of the first semiconductor material layer, and an exposed area of the first semiconductor material layer. And a collector electrode forming step of selectively depositing a metal material film for a collector electrode on the heterojunction bipolar transistor manufacturing method.