JPH0666352B2 - High frequency semiconductor device - Google Patents

Abstract

PURPOSE:To make possible the compatibility of a reduction in a parasitic capacity between wires and the parasitic inductances of the wires and a reduction in the size of the constitution of the title device by a method wherein external connecting electrodes on a ceramic substrate and the electrode pads of a high-frequency semiconductor device are folded back and are bonded together by first and second wire loops formed by being subjected to step bonding on the wires which respectively draw a different locus. CONSTITUTION:External connecting electrodes 12 on a ceramic substrate 11 end electrode pads 14 of a high-frequency semiconductor device 13 are folded back in parallel and are bonded together by first and second wire loops 16 and 19 formed by being subjected to step bonding on wires 15. Moreover, the two wires 15 respectively draw a different locus, the amount of a current per one of the wires, which are separated from each other so as to cross in their height direction, is reduced, s skin effect is reduced end with e parasitic capacity between the wires 15 and the parasitic inductances of the wires 15 reduced, an increase in the areas of the electrodes 12 is prevented by the separation of the wires in their height direction and a reduction in the size of the constitution of a device is contrived.

Description

The present invention relates to a high-frequency type semiconductor device such as GaAs FET, and more particularly to a semiconductor device in which the inductance of a connecting wire is reduced.

(B) Conventional Technology In general, the electrode lead-out line (including the thin metal wire and the lead) of the transistor has a weak inductance but a parasitic capacitance between the lead-out lines. As the frequency increases, these reactances cannot be ignored. Therefore, a transistor used at a high frequency (for example, 1 GHz or more) such as a satellite broadcast or a tuner circuit of a CATV receiver is required to have a small series inductance of lead lines and a small capacitance between the lines. For this reason, in the high-frequency transistor, both the mold type and the ceramic type are made smaller in size to reduce the series inductance due to internal wiring (Japanese Patent Laid-Open No. 62-281458).

Further, as a method of reducing the inductance of the connecting wire, as shown in FIG. 7, a plurality of lead wires (4) are arranged in parallel between the electrode pad (2) on the chip (1) and the external connecting electrode (3). It has been proposed by the inventor of the present application to reduce the current value per wire (4) to alleviate the skin effect and lower the equivalent inductance and the equivalent impedance by performing the bonding.

(C) Problems to be Solved by the Invention However, wire is provided on the electrode pad (2) on the chip (1).
(4) Securing two bonding areas has a drawback that the area of the electrode pad (2) cannot be reduced and thus the parasitic capacitance of the electrode pad (2) cannot be reduced.

Also, if two wires (4) are bonded in parallel, they have mutual inductance, so it is necessary to keep a certain distance between them, which inevitably increases the area of the external connection electrode (3). It was

(D) Means for Solving the Problems The present invention has been made in view of the above-mentioned conventional problems.
The (15) is stitch-bonded to form a folded bond, and the two wires (15) are separated so as to cross each other in the height direction, so that both parasitic capacitance and parasitic inductance are reduced and the device is downsized. And a high frequency type semiconductor device.

(E) Action According to the present invention, two loops (1
6) Since (19) is honed in parallel, the current value per wire (15) is reduced to alleviate the skin effect and
5) Mutual parasitic capacitance and parasitic inductance can be reduced.
Moreover, since the first and second loops (16) and (19) are formed so that the two wires (15) are separated from each other in the height direction, the inductance between the wires (15) is substantially increased. Can be prevented. Furthermore, the stitch bond can reduce the parasitic capacitance by reducing the area of the electrode pad (14), and the two wires (1
By making the shape so that 5) is separated in the height direction,
It is possible to prevent an increase in the area of the external connection electrode (12).

(F) Embodiment One embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 shows a side view of a semiconductor device by treating a wire bond according to the present invention. In the figure, (11) is a ceramic substrate, (12) is an electrode for external connection constituting a microstrip line on the surface of the substrate (11), and (13) is MES-FE on the surface.
T, a GaAs chip on which a microwave element such as a Schottky diode is formed, (14) is an electrode pad made of an aluminum material formed on the surface of the chip (13), and (15) is a diameter 2
It is a gold wire of about 5μ.

The wire (15) is first ball-bonded to the electrode (12) for external connection on the substrate (11) side, and then vertically shifted to a position higher than the surface of the chip (13) or away from the chip (13). And rises, and begins to descend diagonally in an arc from the higher position. The wire (15) which has started to descend descends in a substantially straight line toward the corresponding electrode pad (14) on the chip (13) and is second-bonded on the electrode pad (14). The loop so far describes the first wire loop (16).

The wire (15) connected to the electrode pad (14) is continuously folded as it is, and rises in an arc on the electrode pad (14). Therefore, the folded wire (15) is
(14) Pass the position higher than the first wire loop (16) in the upper vicinity. Wires raised to a height (15)
Starts to descend in a substantially straight line toward the electrode (12) for external connection. The wire (15) that started to descend is the first wire loop
(16) intersects with the first wire loop (16) in the middle (17) of the portion where it linearly descends from the higher position toward the electrode pad (14), and beyond that the electrode (12) for external connection is connected. ) Straight below the first wire loop (16). The wire (15) passing through the lower position again crosses again in the middle (18) of the portion where the first wire loop (16) rises vertically, is connected to the electrode (12) for external connection, and terminates. To do. This describes the second wire loop (19).

The first and second wire loops (16) and (19) take various forms by drawing different trajectories in the vertical direction (height direction). The first and second wire loops (16a) (19) on the right side of FIG.
a) is an example in which the second wire loop (19a) always passes higher than the first wire loop (16a), and the first and second wire loops (16b) (19b) on the left side are Wire loop (19
b) intersects the first wire loop (16b) at one point, and the connection to the electrode (12) for external connection is closer to the chip (13) side than that of the first wire loop (16b) It is an example performed in.

FIG. 3 is a plan view showing a state in which the Schottky diode element is fixed to the ceramic package. (11) is a ceramic base, (20) is an external connection lead derived from the ceramic base (11), and (12) is a base. An electrode for external connection formed on the surface of (11) and electrically connected to the external connection lead, and (13) is a chip having an element and an electrode pad (14) formed on the surface.
The chip (13) is die-bonded on the anode side external connection electrode (12a) pattern with a material such as solder, and then the corresponding electrode pad (14) and external connection electrode (12) are shown in FIG. Alternatively, a wire (15) is stitch-bonded to the shape shown in FIG. Then, the semiconductor chip (13) is sealed by fixing the lid on the base body (11).

Fig. 4 is a plan view showing a state in which a GaAs MESFET device is fixed to a ceramic package also called the µ-X type, and a chip is formed on the source external connection electrode (12S) pattern.
(13) is fixed, the gate electrode pad (14G) and the gate external connection electrode (12G) are connected to the drain electrode pad (14D).
And the drain external connection electrode (12D) are connected by wires (15) respectively, and the source electrode pad (14S) and the source external connection electrode (12S) are shaped as shown in FIG. 1 or 2. Stitch bonded with wire (15).

In the stitch bond, as shown in FIG. 5A, first, a wire (15) having a ball portion (21) at its tip is inserted and attached to a bonding tool (22) attached to a mounting member that can move back and forth in the X and Y directions. ) To lower the ball (21) to the external connection electrode.
(12) Bonding tool (22) under pressure contact with the surface
By applying ultrasonic vibration to the ball part of the wire (15)
(21) is thermocompression bonded with ultrasonic waves to the external connection electrode (12).

Next, as shown in FIG. 5B, the wire (15) is unfixed and the bonding tool (22) is vertically raised to extend the wire (15) to a height higher than the chip (13).

Next, as shown in FIG. 5C, the bonding tool (22) is moved to the chip (13) side and then lowered to wire-bond the wire (15) to the surface of the electrode pad (14) by thermocompression bonding with ultrasonic wave. ,
This completes the first wire loop (16).

Next, as shown in FIG. 5D, the bonding tool (22) is raised as it is without cutting the wire (15), and the wire is moved from the turning point on the electrode pad (14) as shown in FIG. 5E. Make sure that the bonding tool (2
2) is moved, and as shown in FIG. 5F, the bonding tool (22) is lowered on the external connection electrode (12), so that the wire (15) is ultrasonically used on the surface of the external connection electrode (12). The wire (15) is fixed by a clamper (not shown) in a state of being thermocompression bonded and the bonding tool (22) being in pressure contact with the wire, and then the wire (15) is cut. This completes the second wire loop (19). Next, with the wire (15) fixed, the bonding tool (22)
The bonding tool (2
The wire (15) is made to project to the tip of 2) with a certain length.

Then, as shown in FIG. 5G, the discharge electrode (23) and the wire (1
5) A ball portion larger than the diameter of the wire (15) insertion hole of the bonding tool (22) is attached to the tip of the wire (15) by instantaneous heat treatment to the tip of the wire (15) due to discharge or torch flame between
Form (21). Due to the momentary heat treatment at this time, the surface of the wire (15) protruding from the bonding tool (22), particularly close to the discharge electrode (23) and on the side opposite to the chip (13), is thermally affected and may be slightly affected. Quenching treatment is unavoidably performed.
Since the hardened wire (15) increases in hardness and becomes hard to bend, this portion forms a portion where the first wire loop (16) rises vertically on the external connection electrode (12), and It becomes a factor that the arc of the wire loop (16) can be enlarged. Since the second wire loop (19) does not undergo the heat treatment as described above, it is easier to draw an arc smaller than that of the first wire loop (16).

By the way, the increase in mutual inductance due to the close proximity of the two wires (15) is closely related to the distance between them. FIG. 6 is a characteristic diagram showing such a relationship.
= 12 GHz is shown as an example. As is clear from the figure, the mutual inductance rapidly decreases within the range of the distance between the wires 15 of 0 to 0.1 mm, and thereafter becomes almost saturated.
Therefore, in the wire (15) structure of the present application, a portion (17) where one point or two points intersect except for a turning point on the electrode pad (14)
At least 50μ including left and right, up and down, and diagonally including (18)
First and second wire loops (16) (1
It is clear that 9) should be formed.

According to the above invention of the present application, since a plurality of wire loops are formed by folding stitch bonding, the wire (1
5) The current value per wire can be reduced to alleviate the skin effect and the equivalent inductance and impedance of the semiconductor device can be reduced. In addition, by forming the first and second wire loops (16) and (19) into the shape shown in FIG. 1 or 2, the first and second wire loops (16) and (19) can be moved vertically or diagonally. The wires can be spaced apart in a direction, and thus substantially separating the two wires can reduce the mutual inductance of the wires. Moreover, 2
Since the wires (15) of the book are three-dimensionally separated, the pattern size of the electrode pad (14) and the external connection electrode (12) is reduced to reduce the device size and further reduce the equivalent inductance and parasitic capacitance. Can also be possible.

Although the present embodiment has described the ceramic type package in detail, the same applies to a mold type package made of epoxy resin or the like. The same applies when the loop is folded twice and three times to form three and four loops.

(G) Effect of the Invention As described above, the present invention has the plurality of wires (15), and thus has an advantage that the inductance of the wire (15) can be reduced. Also, the first and second wire loops (16) (1
Since the shape of 9) is three-dimensionally separated in the height direction, there is an advantage that the mutual inductance of the wires (15) can be reduced. Moreover, since it is a folded stitch bond, it has the advantage that the parasitic capacitance may be reduced by reducing the pattern size of the electrode pad (14), and since the distance is three-dimensionally maintained, the external connection electrode (12) There is an advantage that the pattern size can be reduced.

Therefore, the inductance of the wire (15) can be made lower than in the past, and a high-frequency and stable high-frequency semiconductor device can be provided.

[Brief description of drawings]

1 and 2 are side views for explaining the present invention, FIGS. 3 and 4 are plan views for explaining the present invention, and FIGS. 5A to 5G are for explaining the present invention. FIG. 6 is a side view for explaining the present invention, FIG. 6 is a characteristic view for explaining the present invention, and FIG. 7 is a perspective view for explaining a conventional example.

Claims (2)

[Claims] 1. A first wire loop extending between an electrode on a GaAs semiconductor chip and an electrode for external connection from the electrode for external connection to an electrode on the chip, and the first wire loop. From the electrode on the chip and connected to a second wire loop extending toward the electrode for external connection, wherein one of the first or second wire loop is A high-frequency characterized by drawing a locus crossing the side of the wire loop at one point or two points in the height direction, and the first and second wire loops have an interval of at least 50 μ or more excluding the folded-back portion. Semiconductor device. 2. A first wire loop extending from the electrode for external connection to the electrode on the chip between the electrode on the GaAs semiconductor chip and the electrode for external connection, and the first wire loop. From the electrode on the chip and connected to a second wire loop extending toward the electrode for external connection, wherein one of the first or second wire loop is A high-frequency semiconductor device characterized by drawing a locus that always passes through a position higher than the wire loop.