JPH0666767B2 - Clock selection switching method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention has a clock supply system of two lines in a clock supply system such as a digital transmission device, and one of the two systems is used by the side using the clock. The present invention relates to a clock selection switching system in the case where a plurality of clock supply systems having a 1 + 1 redundancy configuration, in which a system used as a system and a non-selected system are used as a standby system, are present in particular.

[Conventional technology]

An example of a conventional clock selection switching system will be described with reference to FIG.

In the figure, 21 is a 0-system clock input disconnection alarm, and 22 is 1
This is a system clock input disconnection alarm. Reference numeral 23 is a both-system alarm generation detection circuit which receives the 0-system clock input disconnection alarm 21 and the 1-system clock input disconnection alarm 22, and 24 is a switching control circuit.
Reference numeral 25 is a 0-system clock input disconnection alarm input terminal, 26 is a 1-system clock input disconnection alarm input terminal, 27 is a switching prohibition input terminal, 28 is a clock selection control output terminal, and these constitute a clock selection switching control unit 29. There is. Reference numeral 30 is a clock selection control output.

Reference numeral 31 is a clock break detection circuit, 32 is a clock switching circuit, and these constitute a clock selection switching unit 33.

And the conventional clock selection switching method is the third
As shown in the figure, 0 is set for each system that uses the clock.
The system has both system alarm generation detection circuits 23, which are clock detection circuits that generate input disconnection alarms for two system clock inputs, system 1 and system 2 respectively, and further provides system 0 system / 1 system clock input disconnection alarms. By performing a logical sum (OR) for each and switching the clock selection according to the result, that is, by switching to the standby system selection when the clock input disconnection of the active system occurs in one or more systems and the standby system is normal,
The reliability of the clock in the system was secured. Also,
It had a function of prohibiting clock selection switching so that unnecessary switching would not occur in the clock disconnection state of both systems.

[Problems to be Solved by the Invention]

The above-described conventional clock selection switching method has a function of prohibiting clock selection switching in both the 0-system and 1-system clock disconnection states, but the alarm generation timings of both systems must be exactly the same. If there is a slight "deviation" and the alarm that occurred earlier is the active system, it will temporarily be in the "active system clock disconnection, standby system normal" state, and clock selection switching will occur. That is, both the clock input disconnection alarm generated by turning on / off the clock supply to the system in part 1 or the instantaneous clock input disconnection state caused by turning on / off the power supply in part 1 system. When a clock input disconnection alarm is generated in the system, especially when the clock selection switching of multiple systems is performed simultaneously, the result of ORing the clock input disconnection alarms of multiple systems Therefore, there is a problem that a normal system is affected by unnecessary switching because the clock selection switching is performed.

[Means for Solving the Problem] The clock selection switching method of the present invention detects a break of the active clock in a clock supply system having a 1 + 1 redundancy configuration such as a digital transmission device, and inputs a first clock when a clock break occurs. A first clock loss detection circuit that outputs a loss alarm, a second clock loss detection circuit that detects a loss of the standby system clock, and outputs a second clock input loss alarm when a clock loss occurs; An alarm generation detection circuit connected to a second clock input disconnection detection circuit and outputting a first alarm signal when the first and second clock input disconnection alarms are simultaneously input; Connected to the clock input disconnection detection circuit of and outputs a second alarm signal when only one of the first clock input disconnection alarm and the second clock input disconnection alarm is input. Is connected to the exclusive OR circuit and outputs a switching prohibition signal for a preset time when the second alarm signal is input, and prohibits the switching after the time elapses. A protection timer circuit that suspends signal transmission, the first and second clock loss detection circuits, the alarm generation detection circuit, and the protection timer circuit are connected, and the first alarm signal is input. And a switching control circuit that sends a switching control signal when the switching prohibition signal is stopped.

[Action]

In the present invention, the clock supply to one system is turned on.
If the clock input disconnection alarm occurs due to / OFF or the clock input disconnection alarm occurs in both systems due to the instantaneous clock input disconnection status caused due to the ON / OFF power supply to part of the system, In particular, when the active system alarm is issued first, harmful clock selection switching due to a temporary "active system clock disconnection, standby system normal" state is suppressed.

〔Example〕

 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a clock selection switching system according to the present invention, and shows a clock selection switching control unit and a clock selection switching unit in the clock supply system of the apparatus.

In the figure, 1 is a 0-system clock input disconnection alarm, 2 is a 1-system clock input disconnection alarm, 3 is this 0-system clock input disconnection alarm 1
AND system 1 clock input disconnection alarm 2 as input for both systems alarm occurrence detection circuit, 4 is exclusive OR circuit with 0 system clock input disconnection alarm 1 and 1 system clock input disconnection alarm 2 as input, and 5 is switching control Circuit. The 0-system clock input disconnection alarm 1 and the 1-system clock input disconnection alarm 2 are both system alarm generation detection circuits 3, an exclusive OR circuit 4, and a switching control circuit 5.
Is multi-connected to. The output of the both-system alarm occurrence detection circuit 3 is connected to the switching prohibition input terminal 9 of the switching control circuit 5. On the other hand, the output of the exclusive OR circuit 4 is connected to the switching prohibition input terminal 10 of the switching control circuit 5 through the switching protection timer circuit 6. WOR is a wired OR.

The switching control circuit 5 constitutes means for switching to the standby system selection when the clock input of the active system is cut off and the standby system is normal, and the both system alarm generation detection circuit 3 and the switching control circuit 5 are In both the 0 system and the 1 system, a means for prohibiting the above switching when a clock input interruption occurs is formed, and the exclusive OR circuit 4, the switching control circuit 5, and the switching protection timer circuit 6 are the 0 system. / 1
Only one of the sides of the system is configured to prohibit switching within a certain time after a clock input interruption.

7 is a 0 system clock input disconnection alarm terminal, 8 is a 1 system clock input disconnection alarm input terminal, 11 is a clock selection control output terminal,
Reference numeral 12 is a clock selection switching control unit, and 13 is a clock selection control output.

Reference numeral 14 is a clock break detection circuit, 15 is a clock switching circuit, and these constitute a clock selection switching unit 16.

FIG. 2 is a time chart used to explain the operation of FIG.
6 is a diagram showing the operation timing of the embodiment of the present invention. Here, consider the case where the 0 system is selected as the initial state.

In Fig. 2, (a) shows the occurrence of both systems (when protection is applied), (b) shows the occurrence of both systems (when no protection is applied), (c) shows disconnection of both systems → recovery of both systems (When protection is applied), (d) shows the disconnection of both systems → the recovery of both systems (when protection is not applied).
Respectively correspond to 1, 2, 3, 4, 7 to 11 in FIG.

Next, the operation of the embodiment shown in FIG. 1 will be described with reference to FIG.

First, when a clock input disconnection alarm is generated in both systems due to power failure on the system side, etc., especially "clock disconnection in the active system, normal standby system" is temporarily caused due to a difference in the alarm generation timing of both systems. Consider the case of.

When the clock disconnection occurs only in the 0 system, the output of the exclusive OR circuit 4 changes from "0" to "1", and the switching protection timer 6 is activated. At this time, the output of the switching protection timer circuit 6 changes from "0" to "1", the switching operation of the switching control circuit 5 is prohibited, and returns to "0" after a fixed time.

If a 1-system (stand-by system) alarm is generated during this fixed time, the output of the both-system alarm generation detection circuit 3 becomes "1", and it is recognized as a 0-system / 1-system simultaneous alarm, and the switching protection timer circuit The switching operation of the switching control circuit 5 is continuously prohibited even after the return of 6 (see FIG. 2 (a)).

On the other hand, if the system 1 (standby system) alarm is not issued during the operation of the switching protection timer circuit 6, the system 0 (active system)
It is recognized that the alarm is generated independently, and the switching operation of the switching control circuit 5 occurs at the same time when the switching protection timer circuit 6 is restored (see FIG. 2 (b)).

Next, when the clock input disconnection alarm that occurred in both systems is recovered by turning on the power of the system side, etc. Consider the case where the system becomes "normal".

From the state where switching is prohibited because both systems occur simultaneously, 1
When the alarm of the system (standby system) recovers first and the clock interruption occurs only in the 0 system, the output of the exclusive OR circuit 4 changes from "0" to "1", and the switching protection timer circuit is the same as the above case. 6 starts. At this time, the output of the switching protection timer circuit 6 changes from "0" to "1", the switching operation of the switching control circuit 5 is prohibited, and returns to "0" after a fixed time.

If the alarm of system 1 (standby system) recovers within this fixed time, it is recognized as simultaneous recovery of system 0 / system 1 and the initial state is restored after the switching protection timer circuit 6 returns (see FIG. 2 (c)). .

On the other hand, if the alarm of system 1 (standby system) does not recover during operation of the switching protection timer circuit 6, system 0 (active system)
It is recognized that the above alarm is independently generated, and the switching operation of the switching control circuit 5 occurs at the same time as the switching protection timer circuit 6 is restored (see FIG. 2 (d)).

〔The invention's effect〕

INDUSTRIAL APPLICABILITY As described above, the present invention is applicable to a digital transmission device or the like.
In the clock selection method in the case where there are a plurality of systems using the clock among the clock supply systems of +1 redundant configuration, means for switching to the standby system selection when the clock input disconnection of the active system occurs and the standby system is normal, A means for prohibiting the above switching when a clock input interruption occurs in both the 0 system and 1 system and a means for inhibiting the switching within a certain time after the clock input interruption occurs in only one of the 0 system / 1 system By having a clock input disconnection alarm generated by turning on / off the clock supply to part of the system, or a momentary clock input disconnection state caused by turning on / off the power supply to part of the system. Then, if a clock input disconnection alarm occurs in both systems, especially when the active system alarm occurs first, the status of "active system clock disconnection, standby system normal" is temporarily entered. There is an effect that it is possible to suppress the adverse clock selection switching by the.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a clock selection switching system according to the present invention, FIG. 2 is a time chart used to explain the operation of FIG. 1, and FIG. 3 is a block showing an example of a conventional clock selection switching system. It is a figure. 1 ... 0 system clock input disconnection alarm, 2 ... 1 system clock input disconnection alarm, 3 ... both system alarm occurrence detection circuit, 4 ... exclusive OR circuit, 5 ... switch control circuit, 6 ... switch Protection timer circuit.

Claims (1)

[Claims] 1. A clock supply system having a 1 + 1 redundant configuration, such as a digital transmission device, detects a disconnection of an active system clock, and first detects when a clock disconnection occurs.
The first clock loss detection circuit that outputs the clock input loss alarm of the second, and the second clock detection circuit that detects the loss of the standby system clock
A second clock loss detection circuit for sending out the clock input loss alarm and the first and second clock input loss detection circuits, and when the first and second clock input loss alarms are simultaneously input. An alarm generation detection circuit that outputs a first alarm signal to the first and second clock input disconnection detection circuits, and the first clock input disconnection alarm and the second clock input disconnection alarm are connected to the first and second clock input disconnection detection circuits. An exclusive OR circuit that outputs a second alarm signal when only one of them is input, and an exclusive OR circuit that is connected to the exclusive OR circuit and is preset when the second alarm signal is input A protection timer circuit that sends a switching prohibition signal only for a period of time and stops the transmission of the switching prohibition signal after the lapse of the time, the first and second clock loss detection circuits, the alarm generation detection circuit, and the protection circuit. A switching control circuit connected to a protection timer circuit, which sends a switching control signal when the first alarm signal is not input and the switching prohibition signal is stopped. Clock selection switching method.