JPH0236001B2 - KUROTSUKUMUSHUNDANKIRIKAEKAIRO - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a dual clock system, and in particular to a clockless clock system that can switch to the other clock system without momentary interruption when one clock system is interrupted. This relates to a momentary interruption switching circuit.

Prior Art and Problems Clocks are essential for the operation of digitally operated logic circuits, etc. Therefore, clock systems that supply clocks to such devices are often of duplex configuration to ensure reliable operation. .

In this case, if a failure occurs in the circuit that is currently supplying the clock, and a switch is made to supply the clock from the backup circuit, if there is a momentary disconnection of the supplied clock, the logic Because there is a risk of malfunction in circuits, etc.,
A non-interruption switching circuit that performs switching without momentary interruption is required. FIG. 1 shows a conventional clock lossless switching circuit. In the figure, a indicates a circuit configuration, 1 and 2 are level-off detection circuits, 3 is an external control circuit, and 4 is a changeover switch. Further, b is a time chart showing the operation.

In Figure 1, the first input (CLK IN)
Assuming that the clock from
If a fault occurs in this clock and the clock goes to a high level as shown in FIG. to control the second input (CLK IN)
It operates to continue supplying the clock by switching the clock from the clock to the output.
However, in the circuit shown in FIG. 1, due to the clock break detection time in the level cut detection circuit 1 and the switching times in the external control circuit 3 and changeover switch 4, the clock from the second input is changed as shown in FIG. 1b. A time delay occurs before the signal is output, resulting in clock interruption. As described above, the circuit shown in FIG. 1 cannot perform complete clock switching without instantaneous interruption.

On the other hand, there is a circuit as shown in FIG. 2 that can perform more complete clock switching without instantaneous interruption. In Figure 2, IC1, IC2
is monomulti, C is capacitor, R is resistor, IC
3, IC4 and IC5 are NAND circuits. Also the third
The figure is a time chart showing signals of various parts in the circuit of FIG. 2.

In Figure 2, mono-multi IC1 and IC2 are
Each is triggered by the rising edge of the clock at input B, and generates a pulse with a constant time width determined by capacitor C and resistor R, and the pulse width is determined by the selection of these constants to correspond to one clock period τ. It is assumed that the selection is equal to . Therefore, when the clock is continuously input, the outputs Q _A and Q _B of the monomulti IC1 and IC2 are always at a high level.

Therefore, as shown in Figure 3, if the same clocks CLK A and CLK B are input to each circuit in a normal state, the NAND circuits IC3 and IC
4 outputs CLK A' and CLK B' are respectively clocks.
It becomes the inverted signal of CLK A and CLK B, and both inputs CLK A and CLK Y are output as the output CLK Y of the NAND circuit IC5.
A clock equal to CLK B is obtained.

Furthermore, when either clock input CLK A or CLK B is disconnected, for example, when clock CLK B is disconnected at high or low level as shown in FIG.
4's output clock CLK B' is always at a high level, and therefore, the output clock CLK B' of NAND circuit IC5 is equal to the output clock CLK A' of NAND circuit IC3.
CLK Y is obtained.

However, the circuit shown in Figure 2 works well when one input clock is disconnected at a low level;
If it is disconnected at a high level, there will be a momentary interruption in the output clock. In other words, in Fig. 3, when the input clock CLK B is disconnected at a low level, the output clock CLK Y becomes the input clock CLK.
If the clock CLK B is low level and the clock CLK B is disconnected, the mono multi-IC will not disconnect.
Due to the output delay of output Q of 2, NAND circuit IC
Since a rise delay occurs in the output clock CLK B' of 4 (Fig. 3A), the output clock CLK Y
is disconnected at a high level ((Figure 3B). Such an output clock disconnection occurs when one input clock
CLK B is normal and the other input clock CLK
The same thing happens when A is cut off at a high level.

As described above, the clock lossless switching circuit shown in FIG. 2 still has the problem of not being able to perform complete clock lossless switching.

Purpose of the Invention The present invention aims to solve the problems of the prior art, and its purpose is to provide a clock with two clock inputs, and when one of the input clocks is disconnected, the other clock input is interrupted. In a clock non-interruption switching circuit that switches the input clock without instantaneous interruption and outputs the clock, even if one of the input clocks is interrupted at a high level or an interruption at a low level, the output clock is instantaneously switched. It is an object of the present invention to provide a non-instantaneous clock interruption switching circuit that does not cause clock interruption.

Structure of the Invention The clock uninterrupted switching circuit of the present invention generates a pulse corresponding to one cycle of the input clock triggered by the first and second input clocks, which are equal, by the first and second monomultipliers. The first and second NAND circuits calculate the logical sum of the outputs of the first and second monomulti clocks and the first and second input clocks, respectively, and the third NAND circuit calculates the logical OR of the first and second monomulti clocks. In a clock no-interruption switching circuit that generates an output by calculating the logical sum of the outputs of the first and second NAND circuits, an exclusive OR circuit calculates the exclusive OR of the outputs of the first and second NAND circuits. The first AND circuit calculates the logical sum of the outputs of the first and second monomulti, and the fourth NAND circuit calculates the logic of the outputs of the exclusive OR circuit and the first AND circuit. The sum is calculated, and the second AND circuit calculates the logical sum of the outputs of the second NAND circuit and the fourth AND circuit to generate an output.

Embodiment of the Invention FIG. 4 shows the configuration of an embodiment of the clock non-interruption switching circuit of the present invention. In this figure, the same parts as in FIG. 2 are indicated by the same reference numerals; IC6 is an AND circuit, IC7 is an exclusive OR circuit, IC8 is an AND circuit, and IC9 is a NAND circuit. Further, FIG. 5 is a time chart showing various signals in the circuit of FIG. 4, and is for explaining the operation of the clock interruptionless switching circuit of the present invention.

In FIG. 4, the output clock CLK Y of the NAND circuit IC5 is the same as in the circuit of FIG. When both input clocks CLK A and CLK B are normal, a NAND circuit is activated as shown in Figure 5.
The output clocks CLK A' and CLK B' of IC3 and IC4 are always equal, so the output of exclusive OR circuit IC7 is always low level, and the output of AND circuit IC8 is always high level.
The output of the AND circuit IC6 is always at a high level, so the output of the AND circuit IC6 is equal to the output clock CLKY, and both input clocks are used as the output clock CLKZ.
A clock equal to CLK A and CLK B is obtained.

If one input clock, for example CLK B, is disconnected at a high level, the NAND circuit IC5
As in the case of the circuit shown in FIG. 2, the output clock CLKY of the circuit has a one-cycle high-level clock disconnection (FIG. 5A). However, during this period, the output clock CLK of NAND circuits IC3 and IC4
A' and CLK B' do not match, so the output of exclusive OR circuit IC7 is high level (fifth
Figure B) The output of the AND circuit IC8 is at a low level (Figure 5C), and the output of the NAND circuit IC9 is at a low level (Figure 5D), so the AND circuit IC
The output of CLK_Z is inverted and the high level clock disconnection at the output clock CLK_Z is eliminated.

Also, when one input clock, for example CLK B, is disconnected at high level, the NAND circuit IC5
As in the case of the circuit of FIG. 2, no clock disconnection occurs in the output clock CLKY of the circuit (FIG. 5E). In this case, the output clocks CLK A' and CLK B' of the NAND circuits IC3 and IC4 match, and therefore the output of the exclusive OR circuit IC7 is at a low level (the fifth
Figure F), the output of the AND circuit IC8 is at a high level (Figure 5G), and the output of the NAND circuit IC9 is at a high level (Figure 5H), so the AND circuit IC
The output of 6 is equal to the clock CLK_Y and there is no interruption to the output clock CLK_Z.

The above operation in the circuit of FIG. 4 is exactly the same even when one input clock CLK B is normal and the other input clock CLK A is disconnected.

Effects of the Invention As explained above, according to the clock interruptionless switching circuit of the present invention, the first and second input clocks generate a pulse corresponding to one cycle of the input clock when triggered by the first and second input clocks. a second monomulti, first and second NAND circuits that calculate the logical sum of the outputs of the first and second monomultis and the first and second input clocks, respectively; and a third NAND circuit that generates an output by calculating the logical sum of the outputs of the circuit.
an exclusive OR circuit that calculates the exclusive OR of the outputs of the NAND circuit; a first AND circuit that calculates the OR of the outputs of the first and second monomulti; an exclusive OR circuit and the first Since it includes a fourth NAND circuit that calculates the logical sum of the outputs of the AND circuit, and a second AND circuit that calculates the logical sum of the outputs of the second NAND circuit and the fourth NAND circuit and generates an output, Even when one of the input clocks is disconnected at a high level or disconnected at a low level, there is no momentary disconnection in the output clock.

[Brief explanation of drawings]

1 and 2 are diagrams showing conventional clock lossless switching circuits, FIG. 3 is a time chart showing various signals in the clock lossless switching circuit of FIG. 2, and FIG. 4 is a diagram showing the clock lossless switching circuit of the present invention. FIG. 5 is a time chart showing various signals in the clock non-interruption switching circuit of FIG. 4. 1, 2...Level cutoff detection circuit, 3...External control circuit, 4...Selector switch, IC1, IC
2... Monostable multivibrator (mono multi), C... Capacitor, R... Resistor, IC
3, IC4, IC5, IC9...Nand circuit, IC6,
IC8...AND circuit, IC7...Exclusive OR circuit.

Claims (1)

[Claims] 1 first and second monostable multivibrators (hereinafter abbreviated as monomulti) that are triggered by first and second input clocks and generate pulses corresponding to one cycle of the input clock; first and second NAND circuits for calculating the logical sum of the output of the second mono multi-channel clock and the first and second input clocks, respectively; and calculating the logical sum of the outputs of the first and second NAND circuits; a third NAND circuit that generates an output; an exclusive OR circuit that obtains an exclusive OR of the outputs of the first and second NAND circuits; and a first AND circuit that calculates the logical sum of the outputs of the second monomulti, a fourth NAND circuit that calculates the logical sum of the outputs of the exclusive OR circuit and the first AND circuit, and the second
1. A clock non-interruption switching circuit comprising: a NAND circuit of FIG.