JPH0668762B2 - Variable line buffer with bit configuration - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a line buffer that cuts out a local neighborhood image when executing a local neighborhood image processing such as a spatial product sum operation.

[Background of the Invention]

When performing image processing using a digital computer,
The image data is scanned by a scanning method called raster scanning, that is, a scanning method in which the main scanning direction is left to right and the sub scanning direction is top to bottom. Therefore, when executing a local neighborhood operation such as a spatial product sum operation, a local image is cut out using a circuit as shown in FIG.

In FIG. 6, the input image 1 is scanned by raster scanning. The scanned image data is input to the shift register 11 and the line buffer 2. The line buffer 2 delays the image data by the time for scanning one line of the input image 1. The output of line buffer 2 is the shift register
21 and the line buffer 3 are input. Line buffer 3
Similarly to the line buffer 2, outputs the image data to the shift register 31 after delaying the image data by the time for scanning one line of the input image 1. The image data in the shift registers 11, 21, 31 are sequentially transferred to the shift registers 12, 22, 32, and further to the shift registers 13, 23, 33, respectively. As a result,
Adjacent 3 × 3 pixel data is cut out from the 9 registers.

In the example of FIG. 6, two line buffers and nine shift registers cut out a local neighborhood image in the form of 3 × 3, but by adding a line buffer and a shift register, a larger local neighborhood image can be obtained. You can also take it out.

The line buffer that fulfills such a function was originally constructed by a shift register, but as the number of pixels included in the input image 1 increased, it was replaced with a large-capacity RAM and a row address control circuit that controls the row address of the RAM. (JP-A-58-159190, JP-A-58-169681, etc.). This realizes a function equivalent to that of a shift register by controlling the read / write row address instead of shifting the data itself. This makes it possible to increase the number of delay stages in the line buffer without significantly increasing the number of ICs to be used, and to cut out a local neighborhood image for a large image.

However, the bit width of the line buffer must be the same as the bit width of each pixel of the image to be handled.

Therefore, when processing an image with different pixel bit widths, such as a bivalent image consisting of only black and white, or a multi-valued image that handles intermediate densities, separate line buffers are prepared, or I had to prepare a line buffer with a wide bit width and use it as a dual buffer. This can be said to be a great waste particularly when the line buffer is integrated into an LSI. Further, as described in JP-A-59-45756, in order to effectively utilize the memory space of RAM, input data is combined with RA having a bit width wider than the input data (pixel data). And adjust the bit width to RAM,
It has been proposed to store the combined data in a RAM and decompose the stored data to generate and output data with a narrow bit width. With this configuration, the word length of the stored data can be made variable.

However, even if this method is adopted, the input / output timing of pixel data differs depending on the word length of the pixel, and the timing control becomes complicated. That is, the data can be stored in the RAM at once only after the data is combined according to the bit width of the pixel data and adjusted to the bit width of the RAM. Moreover, even after reading the data from the RAM, the data must be decomposed into data having a specified bit width. For this reason,
Timing control for synthesizing input data and timing control for decomposing data read from RAM are required. Moreover, since this timing changes every time the bit width of the data is different, the timing control becomes complicated. Furthermore, pixel data obtained by raster scanning is stored in RAM
In this case, the data of scanning lines are only sequentially output from this RAM, and this data can be used for straight line images, but it can be effectively used for clipping processing of local neighborhood images that compose a surface. Can not.

As described in JP-A-58-33765, a method of providing a path switching logic circuit for varying the bit width of accessible data according to an address signal when accessing a memory is adopted. However, since the minimum unit of access is only one word and the read data is fixed to a single bus, this data cannot be effectively used for image processing forming a surface.

[Object of the Invention]

An object of the present invention is to divide the memory space according to the bit width of the image data and write the image data into the memory space and read the image data from the memory space with the same timing control even for the image data having different bit widths. It is an object of the present invention to provide a variable line buffer having a bit configuration capable of simultaneously executing image processing and reading image data having different delay times from a plurality of delay stages when image data having a narrow bit width is stored in a memory space.

[Outline of Invention]

The present invention provides an information storage unit in which a plurality of storage elements are arranged in a grid and a row address and a column address are set in each storage element, and a plurality of types of image data having different bit widths are received. An image data selecting means for selecting one of the image data and transferring it to the information storing means, and an input image in response to a write command when the image data having a wider bit width is selected by the image data selecting means. First image data writing means for sequentially writing image data in the storage elements of all columns corresponding to the bit width of data according to the row address, and writing when image data having a wider bit width is selected by the image data selecting means In response to a read command that alternates with the command, image data is sequentially output from the storage elements in all columns corresponding to the bit width of the input image data according to the row address. A first image data read-out unit that protrudes and a storage element group in a column corresponding to the bit width of the input image data in response to a write command when the image data having a smaller bit width is selected by the image data selection unit. Column address control means for sequentially selecting all the column addresses, and when the image data selecting means selects the image data having the smaller bit width, the storage elements of all columns are responded to the write command in accordance with the row addresses for each column. Row address control means for sequentially selecting one by one from the above, and storage selected in duplicate by the column address control means and the row address control means when the image data of the narrower bit width is selected by the image data selection means. Second image data writing means for sequentially writing image data only to the element, and read when the image data having a narrower bit width is selected by the image data selecting means. 1 the image data stored in the storage element of each column corresponding to the bit width of the input image data in response to a command issued from each column according to a row address
The second image data that is sequentially read one by one is read by the reading means,
First image data output means for sequentially outputting the image data of each column read by the first image data reading means,
Receiving the image data of each column read by the second image data reading means, the image data of the newest column of the writing process among these image data is used as the latest read data, and the arrangement of the image data of each column is changed according to the writing order. It is characterized in that a variable line buffer having a bit configuration is provided, which is provided with a second image data output means for sequentially outputting. That is, in a RAM having m rows × n columns and a capacity of m × n bits capable of reading and writing n bits of information at the same time, not only the row address but also the column address is controlled, and the bit width that can be written simultaneously is made variable. . If the write bit width is reduced, the bit width n and the delay buffer number m are set to the bit width w, It can be used as a stage line butt.

Example of Invention

 Examples of the present invention will be described below.

FIG. 1 shows an embodiment of the present invention.

In the figure, a line buffer is configured to operate as 8 bits x 1024 stages when each pixel handles an 8-bit grayscale image, and as 1 bit x 8192 stages when each pixel handles a 1-bit binary image. Show. The line buffer in Figure 2 is
The function is determined by the control signal 101. That is, when the control signal is "High" level, it operates as a line buffer of 8 bits x 1024 stages (bit width n = 8 bits, delay stage number m = 1024 stages), and when it is "Low" level, 1 bit x
8192 stages (bit width w = 1 bit, number of delay stages m × n / w =
It operates as a line buffer of 1024 × 8/1 = 8192 stages).

In the line buffer of FIG. 1, 8-bit grayscale image data is supplied to the input signal line 106, and 1-bit binary image data is supplied to the input signal line 107. When the control signal line 101 is “High”, the input information selection circuit 4 outputs the 8-bit data on the input signal line 106 to the eight signal lines 108, respectively. On the other hand, when the control signal line 101 is "Low", the selection circuit 4 copies the 1-bit data on the input signal line 107 to all eight signal lines 108 and outputs it. The 8-bit data on the signal line 108 is supplied to the 8 × 1024-bit RAM5. RAM5
Reads and writes data in synchronization with the clock signal 102. When the clock signal 102 is "High", the row address signal given from the row address control circuit 7 to the RAM5
According to 104, eight data are simultaneously read onto the signal line 109. At this time, if the control signal 101 is set to “High”, the arrangement conversion circuit 6 outputs the data on the signal line 109 to the output signal line 110.
Output as above. On the other hand, the clock signal 102 is "Lo
When it becomes "w", 8-bit data on the signal line 108 is written in the RAM 5 in accordance with the row address signal 104 from the row address control circuit 7. That is, it is read out immediately before the clock signal 102 becomes "Low". The written data will be written in the same place where it was stored.
It consists of a 10-bit binary counter and counts up every time the "High" level of the clock signal 102 is input, so that the row address signal 104 makes one cycle in 1024 cycles. That is, the RAM 5 operates as a 1024-stage 8-bit line buffer. At this time, the column address control circuit 8 and the layout conversion circuit 6 do not perform any effective operation.

On the other hand, when the control signal 101 is "Low" and the clock signal 102 is "High", 8-bit data is read out on the signal line 107 in accordance with the row address signal 104. "The same as when. However, the clock signal is "L
When it becomes ow, only 1 bit of the 8 bit data on the signal line 108 is the line address signal from the line address control circuit 7.
104 and the column address signal 105 from the column address control circuit 8 are written. That is, only 1 bit of the 8 bit data read out immediately before is rewritten by the data on the input signal line 107. The column address control circuit 8 is a 3-bit binary counter and counts up when the signal 103 from the row address control circuit 7 is "High".
The row address control circuit 7 sets the signal line 103 to “High” when the row address signal 104 changes from 3FF to 000 in hexadecimal notation, and otherwise sets it to “Low”. When 1024 pulses are input to the signal 102, one count up is performed. That is, 8192 for the clock signal 102.
When the pulse is input twice, the column address signal 105 returns to the original state, so that the data in the RAM 5 is rewritten once in 8192 cycles. At this time, the line buffer shown in FIG. 1 operates as a circuit as shown in FIG.

Fig. 2 consists of 9,8 line buffers of 1 bit x 1024 stages. The data input from the input signal line 107 will be sequentially output eight times from the top on the output signal line 110 at different bit positions every 1024 cycles. On the signal line 109 in FIG. 1, as shown on the output signal line 110 in FIG. 2, the pixel data of interest is sequentially output from the top of 8 bits every 1024 machine cycles after being input to the RAM 5. Not necessarily. This is because it depends on the column address when it is written. Therefore, the column address signal 105
Accordingly, when 8 bits of the signal line 109 are shifted by the output information arrangement conversion circuit 6, the same data as the data output on the output signal line 110 of FIG. 2 is output on the output signal line 110 of FIG. The data will be output. This will be described in detail with reference to FIG.

In FIG. 3, it is assumed that the clock signal 102 is "High", the row address signal 104 is i, and the column address signal 105 is j. At this time, 8 bits of information at the i-th row address of the RAM 5 are read out on the signal line 109. In the output information arrangement conversion circuit 6, the read information is the i-th column data in the 1st column, the 8th column data in the {8- (i-1)} column, and the 1st column data. Is (1+
The data of the (i-1) th column is arranged and converted to the 8th column in the i) th column and is output onto the output signal line 110. That is, in order to make the data of the column read at the present time the latest read data, the image data of this column is set to the uppermost column, and the data of the column read before this column is set to the lowermost column. To change the arrangement of each column. If the arrangement of the columns is changed, it is not necessary to determine which column data is the latest data when displaying the image, and thus the image display control becomes easy. The control of the number of shift stages at this time is selectively determined by the column address signal 105.

After that, when the clock signal 102 becomes "Low", among the information of 8 bits on the signal line 108 (in this case, all 8 bits are "High" or all "Low"), the j-th column indicated by the column address signal 105. Only the data of the line address signal 104 in RAM5
Is written in the j-th column address of the i-th row address.

After that, when the clock signal becomes "High" again, the row address signal becomes (i + 1), and the read arrangement conversion similar to the above is performed. The same applies to writing when the clock is "Low". After the street address 104 rises to 1023,
When the clock signal becomes "High", the row address signal 104 is initialized to 0, and at the same time, the column address signal 105 becomes (j + 1). At this time, the output information arrangement conversion circuit 6 adds one shift stage number.

FIG. 4 shows the block configuration of the RAM 5 of FIG. In FIG. 4, the row address signal 104 is decoded by the decoder 42 and supplied as 1024 row selection signals 111 to the eight memory cells 41 at the corresponding row addresses. The column address signal 105 is decoded by the decoder 43 and becomes eight decoded signals 112. Each of the decoded signals 112 is ORed with the control signal 101 and the clock signal 102 at the gate 44, and the column selection signal 113 is obtained. Corresponding column address as 102
It is supplied to four memory cells 41.

When the clock signal is "High", regardless of the control signal 101 and the decode signal 112, the eight data selected by the row selection signal 111 are read out on the signal line 114 and are output to the eight buffers 45. Is entered. Buffer 45 is clock signal 102
The data on the signal line 114 is output to the signal line 109 only when is high. At this time, the signal line 108 is separated from the signal line 115 by the buffer 46.

On the other hand, when the clock signal 102 becomes “Low”, the signal line 108 is connected to the signal line 115 and the signal line 114 is disconnected from the signal line 109. At this time, if the control signal 101 is "High", the data of the input signal 108 is written to all of the eight memory cells 41 selected by the row selection signal 111, and if the control signal 101 is "Low", the decode signal is written. According to 112, the row selection signal 111
To one of the eight memory cells 41 selected by
The data of the input signal 108 is written.

FIG. 5 shows an example of the logic circuit of the memory cell 41 shown in FIG. In FIG. 5, the two gates 51 perform a negative logic and store one bit of information. Only when both the row selection signal 111 and the column selection signal 113 are "High", the gate 52 outputs "High" to the buffer 53 as a logical product.
As a result, the signal line 115 and the signal line 114 have two gates 51.
The information in the memory cell 41 is read out onto the signal line 114 by being connected to the closed loop formed by. Further, the data on the signal line 115 is written in the memory cell 41. However, as described with reference to FIG. 4, the column selection signal 113 may become “Low” after the information in the memory cell 41 is read, and data writing may not be executed in the memory cell 41. This depends on the control signal 101 and the column address signal 105.

According to the present embodiment, a line buffer bit width w that is variable in bit width and number of delay stages is used by using a RAM of m rows × n columns and having a capacity of m × n bits capable of simultaneously reading and writing n bits of information. (1 ≦ w ≦ n) Can be configured. As a result, the grayscale image and 2
When dealing with objects having different bit widths of data such as a value image, if the bit width is small, it can be used as a line buffer having a large number of delay stages. This means that a minimum amount of hardware can be used to handle many types of data, and especially when the line buffer is made into an LSI, the occupied area can be minimized.

Furthermore, each image data is written or read in response to the clock signal 102 without performing a timing process for adjusting the bit width of the image data input to the input information selection circuit 4 to the bit width of the RAM 4. Therefore, the writing control and the reading control of the image data can be executed with the same timing control, and the timing control becomes easy.

Further, when 1-bit binary image data is stored in the RAM 5, image data having different delay times are simultaneously read from each line buffer 9 having 1024 delay stages, as shown in FIG. The image data can be effectively used for cutting out a local neighborhood image forming a surface such as template matching. That is, when the local neighborhood image cutout process is executed using the image data obtained by the raster scan, even if a plurality of image data of the same scan line is collected, it can be used only for the straight line image process. When a plurality of different image data (when the 1024 stages of line buffers 9 are made to correspond to one scanning line, the output data of each line buffer 9 becomes image data obtained from different scanning lines) are sequentially stored, these are stored. The image data is effective for image processing for forming a surface. Further, the image data of each scanning line has a different delay time from line to line, but the image data of each read line is written in order to make the data of the line currently read out the latest read data. Since the images are rearranged in order, it is not necessary to determine which column of data is the latest data when displaying an image, and the image display control is facilitated.

〔The invention's effect〕

As described above, according to the present invention, the memory space is divided according to the bit width of the image data, and the writing of the image data into the memory space and the reading of the image data from the memory space are performed with the images having different bit widths. The same timing control is performed for data, and when image data with a narrow bit width is stored in the memory space, image data with different delay times are simultaneously read from the delay stages of multiple columns, and the read image data for each column is written. Since the data is rearranged according to the order, write control and read control of image data having different bit widths can be executed with simple timing control, and an image data group effective for image processing forming a surface is suitable for image display. Can be output as an array.

[Brief description of drawings]

FIG. 1 is a block diagram of a line buffer having a variable bit width showing an embodiment of the present invention, FIG. 2 is a block diagram showing one use form of the line buffer shown in FIG. 2, and FIG. 3 is shown in FIG. A conceptual diagram showing the operation of the RAM and the output information selection circuit, FIG. 4 is an internal configuration diagram of the RAM shown in FIG. 2, FIG. 5 is a logic diagram showing the operation of the memory cell shown in FIG. 4, and FIG. It is a figure which shows the usage example of the conventional line buffer. 4 ... Input information selection circuit, 5 ... RAM, 6 ... Output information conversion circuit, 7 ... Row address control circuit, 8 ... Column address control circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kotaro Hirasawa, 4026 Kuji Town, Hitachi City, Hitachi, Ibaraki Prefecture Hitachi Research Laboratory, Hitachi Ltd. (72) Inventor Takeshi Kato 5-2-1 Omika Town, Hitachi City, Ibaraki Prefecture Ceremony company Hitachi Ltd. Omika factory (72) Inventor Yoshiyuki Okuyama 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Hitachi Research Laboratory, Hitachi, Ltd. (56) Reference JP-A-58-33765 (JP, A)

Claims (1)

[Claims] 1. An information storage unit in which a plurality of storage elements are arranged in a grid pattern and a row address and a column address are set in each storage element, and a plurality of types of image data having different bit widths are received. Image data selecting means for selecting one of the image data and transferring it to the information storing means, and inputting in response to a write command when the image data having a wider bit width is selected by the image data selecting means. When first image data writing means for sequentially writing the image data in the storage elements of all columns corresponding to the bit width of the image data according to the row address, and when the image data having the wider bit width is selected by the image data selecting means In response to a read command that alternates with a write command, image data is sequentially acquired from the storage elements in all columns corresponding to the bit width of the input image data according to the row address. The first image data reading means for reading and all the storage element groups in the column corresponding to the bit width of the input image data in response to the write command when the image data of the narrower bit width is selected by the image data selecting means. Column address control means for sequentially selecting according to the column address, and when the image data of the narrower bit width is selected by the image data selecting means, in response to the write command, the storage elements of all the columns are changed from each column according to the row address. The row address control means for sequentially selecting one by one, and the storage element selected by the column address control means and the row address control means in duplicate when the image data of the narrower bit width is selected by the image data selection means When the second image data writing means for sequentially writing the image data only to the image data and the image data of the narrower bit width are selected by the image data selecting means The image data stored in the storage element of each column corresponding to the bit width of the input image data in response to a look out command from the column according to a row address 1
Second image data reading means for sequentially reading out one by one, first image data output means for sequentially outputting the image data of each column read by the first image data reading means, and second image data reading means for reading Second image data output for receiving the image data of each column and changing the arrangement of the image data of each column according to the writing order and sequentially outputting the image data of the newest column of the writing process among these image data as the latest read data A variable line buffer having a bit structure comprising :.