JPH0760457B2 - Semiconductor memory and memory device using a plurality of the same - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory and a memory device using a plurality of semiconductor memories, and particularly to a random access memory suitable for image signal processing and a memory using a plurality thereof. It relates to the device.

[Conventional technology]

The image processing includes various kinds of processing such as smoothing operation, noise removal operation, image sharpening operation, density conversion operation, and contour line extraction operation. For example, the simplest method of the smoothing operation is to find the average value of the densities of each point in a 3 × 3 square area centered on an arbitrary point (i, j), and obtain a new density f ( i,
j) and write this operation as follows.

The value of each element of the 3 × 3 matrix in the above equation indicates the coefficient given to the pixel area, which means that all points are added equally and then this is divided by 9 to obtain the average value. . Further, in the case of noise removal, a method of reducing the coefficient as the distance from the point of interest (i, j) increases is used. The following formula is an example of that case.

As described above, in the case of noise removal, high-frequency components are removed by averaging small areas, that is, integrating operation. On the other hand, when the image is sharpened (that is, in the case of edge enhancement), it is obtained by performing a differential operation on the image. For example, a method of taking a difference from four directions centering on an arbitrary point (i, j) is used, and the configuration shown by the following equation is obtained.

As is clear from the above operations, averaging of image signals,
When processing image signals such as differentiation and enhancement, the product-sum operation is often used. For example, as described in Nagao, et al., "Pattern Recognition and Graphic Processing," Iwanami Shoten, Chapter 4, or Chapter 4 of "The LSI Application" edited by the Institute of Electrical Communication, well known.

FIG. 2 is a diagram illustrating a signal flow in image signal processing. In FIG. 2, 201 is a frame buffer that stores a pixel matrix of one frame, 202 is an image display memory for displaying on a display such as a CRT, 203 is a product-sum calculator, and 204 is a register that stores a weighting factor. is there.

FIG. 2 (A) shows the overall flow when the signal X _ij processed by the product-sum calculator 203 is sent to the display memory 202 from the buffer memory 201 that stores a certain one-frame image signal. ing. 3 stored in the buffer memory 201
The signals of the × 3 image (center pixel x _ij ) are successively calculated by the product-sum calculator 2
It is input to 03, and the product sum operation is performed by the weighting coefficient a _ij of the register 204, and X _ij is created. Now, the load factor a
_{If ij} is selected as shown in (A-1), it becomes a differential operation of the digital image signal (sharpening of the image, edge enhancement),
If the selection is made as shown in (A-2), averaging calculation (noise removal) is performed.

Next, FIG. 2 (B) shows a procedure for extracting a signal from the RAM 201. That is, as x _ij , (i, j) =
(1,1), (1,2), (1,3), ..., (2,1),
If (2,2), (2,3), ... are selected sequentially, the required data blocks are VD ₁₁ , VD ₁₂ , VD ₁₃ ,
..VD ₂₁ , VD ₂₂ , VD ₂₃ , ..., Data of 3 × 3 pixels are shifted to the right one column at a time, and in the next line, 1
Shift to the bottom of the line and repeat the same shift to the right.

Therefore, focusing on one pixel data, for example, x ₁₃ , V
Used in each block of D ₁₂ , VD ₁₃ , VD ₁₄ , VD ₂₂ , VD ₂₃ , and VD ₂₄ . Here, this 3 × 3 image signal is calculated using all of them, and the signal X _ij is created after one processing (for example, display processing). Since the display signal X _ij itself is read at a high scan rate, the original signal of (3 × 3) pixels needs to be read at an extremely high speed.

In such image signal processing, since the information amount of the image signal is generally large and a huge amount of memory is required,
Usually, the frame buffer 201 has an inexpensive DRAM (Dynamic
Random Access Memory) is used. However, the conventional DRAM, including what is called a video memory, is not suitable for the above high-speed block reading, and many peripheral ICs (input Output device) must be used to create a complex circuit. Regarding this, for example, “Nikkei Electronics” 1985, 5-6 (NO.368) pp.227-25.
Shown in 8.

A nibble mode is a function that enables high-speed reading in a conventional DRAM.

FIG. 3 is a diagram showing an example of the configuration of a DRAM with a nibble mode function, and FIG. 4 (A) is a time chart of the read operation of the DRAM of FIG.

Pixel information stored in the memory mats 10 to 13 is designated by the row decoders 40 and 41 and the column decoders 42 and 43, read by the data line selection circuits 20 to 23, guided to the input / output line selection circuit 53, and decoded. After processing by 51 and shift register 52, it is taken out from output buffer 55. Memory mat 10
Similarly, when writing information to ~ 13, after inputting from the input buffer 54 to the input / output line selection circuit 53, the decoder
Processing is performed by the 51 and shift register 52, and the result is transferred to the memory mat.

As shown in FIG. 4, row address strobe
The row address i and the column address j are fetched at the falling edge of ▼ and the column address strobe ▲ ▼, respectively, and the row decoders 40 and 41 and the column decoders 42 and 43 operate. However, in this case, the address signals (here, the lower 2 bits a _c0 and a _c1 of the column address signal) used for selecting the four memory mats 10 to 13 are not input to the decoders 42 and 43. Therefore, 4
Data is simultaneously input / output from the individual memory mats 10 to 13.
It is output to 30-33. These are selected by the input / output line selection circuit 53 using the column address signals (lower 2 bits) a _c0 and a _c1 and output to the data output terminal d _out .

Next, if ▲ ▼ is repeatedly started up and down, ▲
The shift register 52 is shifted in synchronization with ▼, and the input / output line selected by the input / output line selection circuit 53 changes.
By applying ▲ ▼ four times, the data read from the four memory mats 10 to 13 are sequentially output to D _OUT .

The characteristic of the nibble mode is that data has already been output up to immediately before the input / output line selection circuit 53, and it is only necessary to select it, so that high speed operation is possible.

[Problems to be solved by the invention]

The conventional nibble mode is not always suitable for image signal processing. The reason will be described below. FIGS. 4B to 4E show changes in the column address of the memory cell selected in the nibble mode operation.
It is shown in correspondence with the waveform of ▲ ▼ in FIG.

FIG. 4B shows a case where the _fetched column address j = 0, that is, the column address signals a _c0 , a _c1 , ..., A _cn-1 are all "0". Initially, the input / output line 30 corresponding to (a _c1 , a _c0 ) = (0,0) is selected. In the same way
When (a _c1 , a _c0 ) = (0,1), (1,0), (1,1), the corresponding input / output lines 31, 32, 33 are selected (see FIG. 4 (C)). ) (D) (E)).

Next, as shown in FIG. 4 (A), by repeatedly raising and lowering ▲ ▼, as shown in FIG. 4 (B),
The selected input / output lines change to 31, 32, 33 in order. In other words, the column address is (a _c1 , a _c0 ) = (0,1), (1,
It is equivalent to the case where it changes to 0) and (1,1). Therefore, at this time, memory cells at addresses 0, 1, 2, and 3 are sequentially selected (note that memory mat 10 has address 0, 11 has address 1,
12 is number 2, 2 is number 3, 13 is number 10, 10 is number 4, and so on ...

FIG. 4C shows the case where the _fetched column address j = 1, that is, only the column address signal a _c0 is “1”, and the others are “0”. Initially, the input / output line corresponding to (a _c1 , a _c0 ) = (0,1) is selected (that is, the input / output line 31 is selected). Next, when the rising and falling of ▲ ▼ are repeated, the selected input / output lines change to 32, 33, 30 in order. In other words, the column address is (a _c1 , a _c0 ) =
It is equivalent to the case of changing to (1,0), (1,1), (0,0). Therefore, at this time, the memory cells at addresses 1, 2, 3, 0 are sequentially selected.

Similarly, in the case of j = 2 (in the case of FIG. 4 (D)), addresses 2, 3, 0, 1 are sequentially selected, and in the case of j = 3 (in the case of FIG. 4 (E)). ), The addresses 3,0,1,2 are selected in order. In the conventional nibble mode, there is a restriction that the head address j must be a multiple of 4 (a _c1 = a _c0 = 0) in order for the sequentially selected addresses to be continuous.

However, in the image signal processing, as shown in FIG. 2 (B), it is necessary to read continuous data with an arbitrary address at the head at high speed. In that case, when j = 1, 1,2,3,4, if j = 2, 2,3,4,5
If j = 3, then 3,4,5,6 must be selected respectively. Therefore, the function of the conventional nibble mode is insufficient for image signal processing.

An object of the present invention is to improve such a conventional problem and to provide a semiconductor memory capable of accessing continuous data at high speed without any restrictions even when an arbitrary address is used as a start address, and a plurality of such semiconductor memories. To provide the memory device that was used.

[Means for solving problems]

The present invention, in order to achieve the above objects, respectively,
A plurality of word lines (lines selected by the row decoder), a plurality of data lines (Dk, ...) Orthogonal to the word lines, and memory cells provided at intersections of the word lines and the data lines, A memory block address of one memory cell, which is composed of a plurality of memory blocks configured to selectively connect any data line of the plurality of data lines (Dk, ...) To one input / output line And an internal address in the memory block are specified, the information of the selected memory cell group of each of the memory blocks including the memory cell is sequentially or simultaneously read or written in the semiconductor memory. Select the data line associated with the memory cell specified by the internal address of the memory block, or specify the address obtained by performing a predetermined operation on the address. Determining means (74 to 79) for determining whether to select the data related to the memory cell, and means (60 to 63) for selectively connecting one of the data lines to the input / output line by the output of the determining means. It is characterized by having and respectively.

Further, the judgment means is configured to execute the memory block address (ac0, a
It is characterized in that it is determined based on c1) or based on the result of calculating the memory block address (ac0, ac1) and the externally applied control signal (c).

Further, in a memory device formed by connecting a plurality of the semiconductor memories, terminals for the memory block address signal and the memory block internal address signal of each semiconductor memory are commonly connected, and at least one of the semiconductor memories for the control signal is connected. The terminal is connected to a fixed potential, and the terminal for the control signal of the other at least one semiconductor memory is connected to the memory block address signal.

[Action]

According to the present invention, a memory cell at a specified address and an address obtained by performing an operation on the address, for example, a memory cell at an address obtained by adding 4 in the case of FIG. 4 can be selectively accessed. . That is, j
If = 1, the address is 1,2,3,0 without adding 4
By selecting any one of the addresses 5, 6, 7 and 4 to which 4 and 4, are added, it is possible to select the consecutive addresses 1, 2, 3, and 4.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 5 is a diagram showing a time chart of the nibble mode operation of the DRAM according to the present invention and the change state of the column address of the memory cell selected at that time.

The time chart of FIG. 5 (A) is the same as the conventional operation of FIG. 4 (A). What is different is from FIG.
The change in the column address in (E), which is apparent from comparison with FIG. 4, shows that the fetched column address j
Is the same when x is a multiple of 4 (a _c1 = a _c0 = 0),
In other cases, the selected address is different. That is, FIG. 5 (C) shows the case where j = 1. ▲ ▼
In the first to third cycles, the addresses 1, 2, and 3 are sequentially selected, as in the case of FIG. However, in the fourth cycle, address 0 is selected in the case of FIG. 4, whereas in the case of FIG. 5, the address to which 4 is added, that is, address 4 is selected.

FIG. 5 (D) shows the case where j = 2. In the first and second cycles of {circle around (2)}, addresses 2 and 3 are sequentially selected, as in FIG. However, in the 3rd and 4th cycles,
In the case of FIG. 4, addresses 0 and 1 are selected in order, whereas in the case of FIG. 5, addresses to which 4 is added, that is, addresses 4,5 are selected in order. Similarly, when j = 3 (FIG. 5 (E)), the third address is selected in the first cycle, but in the second to fourth cycles, 4,5,
Address 6 is selected in order. As described above, in the present invention, the selected addresses are always continuous regardless of whether the fetched column address j is a multiple of 4.

FIG. 1 is a block diagram of a DRAM showing an embodiment of the present invention. In FIG. 1, 10 to 13 are memory mats, 60 to 63 are data line selection circuits, 30 to 33 are input / output lines, 40 and 41 are row decoders, 42 and 43 are column decoders, 50 is an adder, and 51 is Decoder, 52 is shift register, 53 is input / output line selection circuit,
54 is an input buffer and 55 is an output buffer. The circuit of FIG. 1 differs from the conventional circuit of FIG. 3 in that the internal configuration of the data line selection circuits 60 to 63 and the cascade connection signal C are input from the outside.

The operation of the semiconductor memory shown in FIG. 1 will be described below. However, the description of the fetching of the address signal and the selection of the word line by the row decoder is omitted since it is the same as the conventional one, and the feature of FIG. The data line selection method will be described in detail.

The data lines are provided in each of the memory mats 10 to 13 by N / 4 = ^2n-2 lines, for a total of N = ²ⁿ lines. Column address signal
Out of a _{c0 to} a _cn-1 , the upper (n-2) bits a _{c2 to} a _cn-1
1 from each memory mat by the column decoders 42 and 43
It is used to select a total of four data lines one by one and connect them to the input / output lines 30 to 33, respectively. Lower 2 bits a
_c0 and a _c1 are used to select one of the four input / output lines 30 to 33. The column addresses are assigned by assigning the data lines D ₀ , D ₁ , D ₂ , ... of the memory mat 10 to addresses ₀ , 4, 8, ..., and D ₀ , D ₁ , ... of the memory mat 11, respectively.
D _2, ··· each 1,5,9, ... address, memory mat 1
2, D ₀ , D ₁ , D ₂ , ... are addresses 2,6,10, ..., and memory mat 13 D ₀ , D ₁ , D ₂ , ... are 3,7, respectively. 11,
··· The address.

When in nibble mode, shift register 52
The I / O line selected is changed in synchronization with ▼. That is, an address in which the lower 2 bits a _c0 and a _c1 of the column address are changed is selected.

Next, regarding the configuration and operation of the data line selection circuits 60 to 63,
Detailed description. Although the internal description of the selection circuits 61 to 63 is omitted, it has the same configuration as the selection circuit 60. These data line selection circuits 60 to 63 are circuits which receive the outputs of the column decoders 42 and 43 and connect one data line to the input / output lines 30 to 33. In the figure, φ _y is a data line selection signal, and 100 is a switching circuit. This switching circuit 100 receives the control signal 70 and outputs the data line selection signal φ _y to the line 80 side, or
This is a switching circuit for outputting to the 90 side.

Now, it is assumed that only the output Yk of the column decoder 42 is in the “selected” state. When the control signal 70 is “0”,
The data line selection signal φ _y is output to the line 80 side, and the data line Dk
Is selected. Further, when the control signal 70 is “1”, the data line selection signal φ _y is output to the line 90 side, and the data line Dk _{+ 1}
Is selected. That is, the control signal 70 determines whether the data line as the output of the column decoder 42 is selected or the adjacent data line, that is, the data line whose column address is increased by 4 is selected.

Next, in the nibble mode, the case where the cascade connection signal C = “0” is described first.

Now, it is assumed that the _fetched column address j = 0, that is, the column address signals a _c0 , a _c1 , ..., A _cn-1 are all "0". At this time, the output of the column decoder is Y ₀
Only the data line selection circuit 60 is in the state of "selection".
Since the control signals 70 to 73 of 63 to 63 are all “0”, the data line D ₀ is selected in each memory mat. When C = "0", the inputs a _c0 and a _c1 are output as they are to the output of the adder 50. Therefore, in the input / output selection circuit 53,
Every time 30 is selected and the shift register 52 is shifted, 31, 32, and 33 are sequentially selected.

FIG. 5 is a diagram showing an operation time chart of the DRAM in FIG. 1 and each selected address value when j = 0 to 3. As described above, when j = 0, the column address of the sequentially selected data line is 0, 1, 2, 3 as shown in FIG. 5 (B).

Next, the fetched column address j = 1, that is,
Consider a case where only a _c0 is “1” and a _{c1 to} a _cn-1 are “0”. At this time, the output of the column decoder is the same as above.
Although only Y ₀ is in the “select” state, the control signal 70 is “1” and 71 to 73 are “0”. Therefore, the data line D ₁ is selected in the memory mat 10 and 11 to 13 are selected. D ₀ is selected.
In the input / output line selection circuit 53, since the value of the cascade connection signal C is “0”, the values (01) of a _c1 and a _c0 are output as the output of the adder 50. Each time the shift register 52 is selected and shifted, the input / output lines 32, 33,
Selected in order of 30. Therefore, the column address of the data line selected at this time is 1,2,3,4 as shown in FIG. 5 (C).

Similarly, when j = 2, the control signals 70,71 are "1", 72,73 are "0", and the input / output line selection order is 32,3.
Since it is 3,30,31, as shown in FIG.
Addresses 4,5 are selected in order.

Next, when j = 3, the control signals 70 to 72 become 1 and 73 become 0, the input / output line selection order becomes 33, 30, 31, 32, and the fifth
As shown in FIG. 6E, addresses 3, 4, 5 and 6 are selected in order.

As described above, by providing the data line selection circuits 60 to 63 with the function of selecting the data line as specified by the column address and the data line of the address obtained by adding 4 to the column address, as shown in FIG. Such address selection can be performed. That is, in FIG. 5, regardless of whether the fetched column address j is a multiple of 4, the selected addresses are always continuous.

Next, regarding the case where the signal C for cascade connection is "1",
Detailed description. FIG. 6 is a diagram showing a time chart of the DRAM operation and a selected address value when the signal C for cascade connection is “1” in FIG.

Now, it is assumed that the fetched column address j = 0. At this time, the output of the column decoder is in the state that only Y ₀ is “selected”, and the input C of the OR gate 74 is “1”.
Therefore, the control signal 70 of the data line selection circuit 60 is “1”,
Or some of the inputs of AND gates 75,78,79 is a "0", the control signal 71 to 73 of the data line selection circuit 61 to 63 is "0", the memory mats 10 the data lines D ₁ Is selected,
The data line D ₀ is selected in the memory mats 11 to 13. Since C = “1”, the adder 50 adds 4 to a _c1 and a _c0 .
The result of adding 1 modulo is sent to the decoder 51.
That is, in this case, since (a _c1 , a _c0 ) = (0,0), (0,1) is sent. Therefore, the input / output line selection circuit 53
Now, the I / O line 31 is selected first and the shift register 52
The input / output lines 32, 33, 30 are selected in this order each time is shifted. The column address of the data line selected at this time is 1, 2, 3, 4 as shown in FIG. 6 (B).

_Similarly , when j = 1, a _c0 = "1", a _c1 = "
Control signals 70 and 7 which are the outputs of OR gates 74 and 76 because of "0"
1 is “1”, the control signals 72 and 73 output from the AND gates 78 and 79 are “0”, and the adder 50 adds 1 to a _c1 and a _c0 modulo 4, that is, (1 , 0) is output, the input / output line selection circuit 53, as shown in FIG.
Addresses 2, 3, 4, and 5 are selected in order.

Next, when j = 2, since a _c1 = “1”, a _c0 = “0”, the outputs of the OR gates 74, 76, 77 are “1”, and the output of the AND gate 78 is also “1”, The outputs of the AND gates 75 and 79 are "0", so that the control signals 70 to 72 are "1" and 73 is "0". In addition, the result of adding 1 to (1,0) modulo 4 by the adder 50 (1,
1) is output, the input / output line selection circuit 53 outputs 33,3
Input / output lines are selected in the order 0, 31, 32, and as shown in FIG. 6D, addresses 3, 4, 5 and 6 are selected in order.

Next, when j = 3, since a _c1 = “1” and a _c0 = “ ₁ ”, the outputs of the OR gates 74,76,77 are “1”, and the AND gates 75,7.
The outputs of 8 and 79 are also "1", so that the control signals 70 to 73 are all "1". Since the adder 50 outputs (0,0) as a result of adding 1 to (1,1) modulo 4, the input / output line selection circuit 53 selects the input / output lines in the order of 30, 31,32,33
Then, as shown in FIG. 6 (E), addresses 4, 5, 6, and 7 are selected in order.

As is clear from comparing FIG. 5 and FIG. 6, C =
In the case of "1", compared with the case of C = "0", the selected addresses are shifted by one address to the larger address.
That is, it becomes the same as when the column address becomes j + 1.

The cascade connection signal is particularly effective when a plurality of memories are cascade-connected and more than four continuous data are read and written at high speed.

FIG. 7 is a block diagram showing an example of a memory device using the DRAM of the present invention. Here, an example is shown in which two DRAMs according to the present invention are used so that eight continuous data can be read and written at high speed.

In FIG. 7, 110 and 111 are DRAMs according to the present invention, 11
2 and 113 are changeover switches. ▲ ▼ 、 ▲
The ▼ and the write enable signal ▲ ▼ are commonly connected to both memories 110 and 111. A _{0 to} A _n are external address signals, A ₀ is connected to the C terminal of the memory 110, the other A ₁ is connected to the a ₀ terminal, A ₂ is connected to the a ₁ terminal, and so on. Connect them by shifting them one by one. External data input terminal D
_in0 and D _in1 are stored in the memory 110 via the changeover switch 112.
And 111 to the data input terminal d _in . Similarly, the external data output terminals D _OUT0 and D _OUT1 are also connected to the data output terminals d _OUT of the memories 110 and 111 via the changeover switch 113. Continuous data in this memory device
When x ₀ , x ₁ , ... x _2N-1 are stored, x ₀ is stored in the memory 110 at address 0, x ₁ is stored in the memory 111 at address 0, x ₂ is stored in the memory 110 at address 1, x ₃ at address 1 of memory 111, ...
・ ・, And so on.

It will be described below that this connection yields any eight consecutive data. The description of the row address selection is omitted. For example, when 0 is designated as the column address, that is, when all of A _{0 to} A _n are “0”, addresses 0, 1, 2, and 3 are sequentially selected in the memories 110 and 111. When A ₀ = “0”, the changeover switch 113
Thus, the data output terminal d _OUT of the memory 110 is connected to D _OUT0 , and the data output terminal d _OUT1 of the memory 111 is connected to D _OUT1 . Therefore, data x ₀ , x ₂ , x ₄ , x ₆ from D _OUT0
Data x ₁ , x ₃ , x ₅ , x ₇ are sequentially output from _OUT1 . Next, when 1 is specified as the column address, that is, when only A ₀ is “1” and A _{1 to} A _n are “0”, the memory 111 addresses 0, 1, 2, 3 as above. Are sequentially selected, but the signal C for cascade connection of the memory 110 is “1”.
Therefore, the selected addresses are addresses 1, 2, 3, and 4. When A ₀ = “1”, the changeover switch 11
The output terminal d _OUT of the memory 110 becomes D _OUT1 and the memory 111
Output terminals d _OUT are connected to D _OUT0 , respectively. Therefore, x ₁ , x ₃ , x ₅ , x ₇ from D _OUT0 and x ₂ , x from D _OUT1
x ₄ , x ₆ , and x ₈ are sequentially output.

Thus, when the column address is even, the memory
The same address can be selected for both 110 and 111, and if it is an odd number, only the memory 110 can select one address with a larger number so that continuous data can always be obtained. As is clear from the above description, the change-over switch 113 is for always allowing the data with the smaller number to be output from D _OUT0 , and if the order of the data does not matter, select this switch. Can be omitted.

The advantage of providing the signal C for cascade connection is that the peripheral circuit required for performing the cascade connection becomes simple as shown in FIG. Although the cascade connection is possible without the cascade connection signal C, an adder for increasing the address is required, and the scale of the peripheral circuit increases. That is, as described above, setting C = “1” is equivalent to increasing the column address by 1.

In the embodiment of FIG. 1, the data line selection circuit 60
By adding a circuit to 63, not only the data line of the designated address but also the data line adjacent to the data line can be selected. However, the same thing can be done by placing an adder in front of the column decoder and modifying the address input to the column decoder. By doing so, the data line selection circuits 60 to 63 can be left in the same configuration as the conventional one. However, in this method, a separate column decoder is required for each memory mat, and for example, the column decoder 42 cannot be shared by the memory mats 10 and 11 in FIG.
In this respect, the method of FIG. 1 is superior.

Further, in the above description, the nibble address (address that automatically changes in the nibble mode) has been described as the lower 2 bits a _c0 and a _c1 of the column address. However, the nibble address is not necessarily limited to this bit, and may be another column address or row address. Even in this case, the present invention can be applied by simply exchanging the address signals.

Further, the present invention can be applied not only to the memory that sequentially reads and writes continuous data, such as the above-mentioned DRAM with nibble mode, but also to the memory that simultaneously reads and writes continuous data.

FIG. 8 is a block diagram of a RAM showing another embodiment of the present invention. FIG. 8 shows a case where the present invention is applied to a memory for reading / writing continuous data at the same time. In FIG. 8, reference numeral 56 is a changeover switch, which is composed of four input / output lines 30-
This is a circuit for switching the connection between 33 and the four input / output buffers 120 to 123. It is the same as in the case of FIG. 1 that continuous data is always obtained on the input / output lines 30 to 33 regardless of the address. The changeover switch 56 merely rearranges the data in numerical order. For example, C =
When "0", a _c1 = "0", a _c0 = "1", the I / O line 31 is in the buffer 120, the I / O line 32 is in the buffer 121, and the I / O line is
33 is connected to the buffer 122, and the input / output line 30 is connected to the buffer 123. Therefore, if the order of the data does not matter, the changeover switch 56, the decoder 51, and the adder 50
Can be omitted.

In the embodiment of FIG. 8, 4 bits of continuous data can be obtained at the same time, so that it is more suitable for high speed operation than the embodiment of FIG.

FIG. 9 is a flow chart of the memory read operation in the present invention. The operation sequence will be described with reference to FIG. First, the row address is read (301), and then the column address is read (302). Signal C for cascade connection
= "1" or C = "0" is checked (303), and if "0", some j / 4 remainders are obtained (304). If the remainder is 0, the memory mat 10 to 13 selects Dk (305). Then, the input / output lines are selected in the order of 30, 31, 32, 33 (306).
If the remainder is 1 (4n + 1), only memory mat 10 selects Dk _{+ 1} , and the other memory mats 1 to 13 select Dk (308). Then, the input / output lines are selected in the order of 31, 32, 33, 30 (309). If the remainder is 2, (4n +
2), the memory mats 10 and 11 are Dk ₊₁ and the memory mats 12 and 13 are
Select Dk respectively (310) and input / output lines 32,33,30,31
(311). If the remainder is 3, (4n
+3), memory mats 10 to 12 are Dk ₊₁ and memory mats 13
Only Dk is selected (312) and the input / output lines 33, 30, 31, 32 are selected in this order (313).

On the other hand, when C = “1”, the remainder of j / 4 is obtained (307). If the remainder is 0, the memory mat is the same as when the remainder is 1 when C = “0”. Select Dk ₊₁ only for 10 (308), and select I / O lines in the order of 31, 32, 33, 30 (30
9). If the remainder is 1, Dk _{+ 1} is selected only for the memory mats 10 and 11 (310), and the input / output lines are 32, 33, and 30 as in the case where the remainder is 2 when C = "0". Then, select in the order of 31 (311). If the remainder is 2, the memory mats 10 to 12 select Dk _{+ 1} (312) as in the case of the remainder 3 when C = "0" (312), and the input / output lines 33, 30, 31, Select in the order of 32 (313). If the remainder is 3, Dk _{+ 1} is selected for all the memory mats (314) and the input / output lines are selected in the order of 30, 31, 32, 33 (315).

Thus, in this embodiment, 4 bits of continuous data can be accessed at high speed. It is also possible to obtain continuous data at the same time, and in this case, even higher speed can be obtained.

〔The invention's effect〕

As described above, according to the present invention, continuous data having an arbitrary address at the head can be sequentially or simultaneously accessed at high speed, so that a semiconductor memory suitable for image signal processing can be created.

[Brief description of drawings]

FIG. 1 is a block diagram of a DRAM showing a first embodiment of the present invention, FIG. 2 is a diagram for explaining a signal flow in image signal processing,
FIG. 3 is a block diagram of a conventional DRAM, and FIG. 4 is a conventional DRAM of FIG.
The operation time chart of DRAM, FIG. 5 and FIG.
7 is an operation time chart of the DRAM in the figure, FIG. 7 is a block diagram of a memory device using the DRAM of the present invention, FIG. 8 is a block diagram of the RAM showing the second embodiment of the present invention, and FIG. DRA in figure
It is an operation | movement flowchart of M. 10 to 13: memory mat, 30 to 33: input / output lines, 40,41: row decoder, 42,43: column decoder, 50: adder, 51: decoder, 52: shift register, 53: input / output line selection circuit , 54: Input buffer, 55: Output buffer, 56: Changeover switch, 60
~ 63: Data line selection circuit, 120 ~ 123: I / O buffer.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Katsuhiro Shimoto 1-280 Higashi Koigakubo, Kokubunji, Tokyo Metropolitan Research Laboratory, Hitachi Ltd. (72) Ryoichi Hori 1-280 Higashi Koigakubo, Kokubunji, Tokyo Hitachi Central Research Laboratory (72) Inventor Goro Tachibagawa 1-280 Higashi Koigakubo, Kokubunji, Tokyo Hitachi Central Research Institute Co., Ltd. (72) Hiroi Ueda 1-280 Higashi Koigakubo, Kokubunji, Tokyo Hitachi Central Inside the research institute (72) Inventor Sei Matsushima 1-280, Higashi Koigakubo, Kokubunji, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (56) Reference JP-A-59-110086 (JP, A)

Claims (4)

[Claims] 1. Each of the memory cells has a plurality of word lines, a plurality of data lines orthogonal to the word lines, and a memory cell provided at an intersection of the word lines and the data lines. It is composed of a plurality of memory blocks configured to selectively connect any one of the data lines to one input / output line, and specifies a memory block address of one memory cell and an internal address in the memory block. By doing so, in the semiconductor memory in which the information of the selected memory cell group of each of the memory blocks including the memory cell is sequentially or simultaneously read or written, the memory block internal address is designated in each of the memory blocks. Selects a data line associated with a memory cell, or associates with a memory cell designated by an address obtained by performing a predetermined operation on the address. 2. A semiconductor memory comprising: a judgment means for judging whether to select a data line; and a means for selectively connecting one of the data lines to the input / output line according to the output of the judgment means. 2. The semiconductor memory according to claim 1, wherein the judging means makes a judgment based on at least the memory block address. 3. The semiconductor memory according to claim 2, wherein said judging means makes a judgment based on a result of calculating said memory block address and a control signal applied from the outside. 4. Each of the memory cells has a plurality of word lines, a plurality of data lines orthogonal to the word lines, and a memory cell provided at an intersection of the word lines and the data lines. It is composed of a plurality of memory blocks configured to selectively connect any one of the data lines to one input / output line, and designates a memory block address of one memory cell and an internal address in the memory block. By doing so, the information of the selected memory cell group of each of the memory blocks including the memory cell is sequentially or simultaneously read or written, and in each of the memory blocks,
Judging means for judging whether to select a data line associated with a memory cell designated by the internal address of the memory block or a data line associated with a memory cell designated by an address obtained by performing a predetermined operation on the address. And a plurality of semiconductor memories each having means for selectively connecting one of the data lines to the input / output line according to the output of the judging means, the memory block address signal of each semiconductor memory and the memory. The terminals for the block internal address signal are commonly connected, and the terminals for the control signal of at least one of the semiconductor memories are connected to a fixed potential,
A memory device, wherein the terminal for the control signal of at least another semiconductor memory is connected to the memory block address signal.