JPH0671082B2 - Thin film transistor - Google Patents
Thin film transistorInfo
- Publication number
- JPH0671082B2 JPH0671082B2 JP62081643A JP8164387A JPH0671082B2 JP H0671082 B2 JPH0671082 B2 JP H0671082B2 JP 62081643 A JP62081643 A JP 62081643A JP 8164387 A JP8164387 A JP 8164387A JP H0671082 B2 JPH0671082 B2 JP H0671082B2
- Authority
- JP
- Japan
- Prior art keywords
- resistant
- thin film
- film transistor
- tantalum
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
- H10D30/6739—Conductor-insulator-semiconductor electrodes
Landscapes
- Thin Film Transistor (AREA)
Description
【発明の詳細な説明】 ［産業上の利用分野］ この発明は薄膜トランジスタに関するもので、とりわけ
液晶表示パネルなどに使用さる薄膜トランジスタに関す
るものである。Description: TECHNICAL FIELD The present invention relates to a thin film transistor, and more particularly to a thin film transistor used for a liquid crystal display panel or the like.
［従来の技術］ 従来の薄膜トランジスタの構成について、液晶表示パネ
ルについて実施した例を製造工程を追って説明する。[Prior Art] With respect to the configuration of a conventional thin film transistor, an example in which a liquid crystal display panel is implemented will be described by following manufacturing steps.
ガラスまたは石英よりなる基板１の上にモリブデン、ニ
ッケルクロム合金、タンタル、クロムなどの耐熱性金属
よりなるゲート電極２をパターン形成する。さらにプラ
ズマCVD法により絶縁膜３としてシリコン窒化膜または
シリコン酸化膜を形成後、イントリンシックアモルファ
スシリコン膜４、リンＰをドープしたｎ型アモルファス
シリコン膜５を連続で成膜する（第３図Ａ）。その後イ
ントリンシックアモルファスシリコン膜４、ｎ型アモル
ファスシリコン膜５の必要部分を残してエッチングす
る。この上にソース電極６、ドレイン電極７をITOなど
の透明電極でパターン形成し、画素電極８はドレイン電
極７と同時に接続して形成する（第３図Ｂ）。画素電極
８はドレイン電極７とは別に形成してもよいことはもち
ろんである。ソース電極６、ドレイン電極７を形成後、
これら電極をマスクにしてｎ型アモルファスシリコン膜
５を部分的にエッチングして、イントリンシックアモル
ファスシリコン膜４を残してチャンネル９を形成する。
パシベーション膜10としてシリコン酸化膜またはシリコ
ン窒化膜をプラズマCVD法にて成膜する（第３図Ｃ）。
さらにアルミニウムやモリブデンなどにより光遮蔽膜11
を形成し、液晶配向膜12としてポリイミド型の樹脂やシ
リコン酸化膜を形成する（第３図Ｄ）。A gate electrode 2 made of a heat-resistant metal such as molybdenum, nickel chromium alloy, tantalum, or chromium is patterned on a substrate 1 made of glass or quartz. Further, after forming a silicon nitride film or a silicon oxide film as the insulating film 3 by the plasma CVD method, an intrinsic amorphous silicon film 4 and an n-type amorphous silicon film 5 doped with phosphorus P are continuously formed (FIG. 3A). . After that, the intrinsic amorphous silicon film 4 and the n-type amorphous silicon film 5 are etched leaving necessary portions. A source electrode 6 and a drain electrode 7 are patterned on the transparent electrode such as ITO, and a pixel electrode 8 is formed by connecting the drain electrode 7 and the pixel electrode 8 simultaneously (FIG. 3B). Of course, the pixel electrode 8 may be formed separately from the drain electrode 7. After forming the source electrode 6 and the drain electrode 7,
Using these electrodes as a mask, the n-type amorphous silicon film 5 is partially etched to form the channel 9 while leaving the intrinsic amorphous silicon film 4.
A silicon oxide film or a silicon nitride film is formed as the passivation film 10 by the plasma CVD method (FIG. 3C).
Furthermore, the light shielding film 11 is made of aluminum or molybdenum.
Then, a polyimide resin or a silicon oxide film is formed as the liquid crystal alignment film 12 (FIG. 3D).
［発明が解決しようとする問題点］ 上記従来例において、ゲート電極２をMo、NiCr、Cr、Ni
等の金属材料で形成した場合、これら金属は後工程のソ
ース電極６、ドレイン電極７、画素電極８を形成するた
めのITOのエッチング液、たとえば塩酸と塩化鉄系のエ
ッチング液に侵される。ゲート電極２を覆うゲート絶縁
膜のシリコン窒化膜やシリコン酸化膜にピンホールやク
ラックがなければ問題がないが、実際にはピンホールや
クラックが存在し、そこからITOのエッチング液がしみ
込み、ゲート電極を侵す。ゲート電極材料として、ITO
のエッチング液や強酸に強いTaを用いると、ゲートのラ
イン抵抗がMoで形成した場合より2.5〜10倍も高くな
り、寄生容量と併せてゲートパルスのなまりを生ずる。
したがって、アクティブマトリックス駆動表示パネル等
に応用した場合、表示品質の低下を生じる。[Problems to be Solved by the Invention] In the above-mentioned conventional example, the gate electrode 2 is formed of Mo, NiCr, Cr, Ni.
When formed of a metal material such as the above, these metals are attacked by an etching solution of ITO for forming the source electrode 6, the drain electrode 7, and the pixel electrode 8 in a later step, for example, an etching solution of hydrochloric acid and iron chloride. If there are no pinholes or cracks in the silicon nitride film or silicon oxide film of the gate insulating film that covers the gate electrode 2, there is no problem, but in reality there are pinholes or cracks, and the ITO etchant permeates from there. Attacks the gate electrode. ITO as a gate electrode material
When the etching solution or Ta which is strong against strong acid is used, the line resistance of the gate becomes 2.5 to 10 times higher than that when it is formed of Mo, and the gate pulse becomes rounded together with the parasitic capacitance.
Therefore, when applied to an active matrix drive display panel or the like, display quality is degraded.
こうした欠点を解決するために耐強酸性と抵抗値の両方
を満足させるために、Moなどの金属材の上にエッチング
液に強いTaを被覆することも考えられるが、これだとス
パッタに手間がかかり、パターニング工程が２度にな
る、などの欠点がある。In order to satisfy both the strong acid resistance and the resistance value in order to solve these drawbacks, it is conceivable to coat Ta, which is resistant to etching liquid, on a metal material such as Mo, but with this, it is troublesome for sputtering. However, there are drawbacks such as that the patterning process is performed twice.
本発明の目的は、ゲート電極が耐強酸性および低抵抗性
を有する薄膜トランジスタを提供することである。An object of the present invention is to provide a thin film transistor whose gate electrode has strong acid resistance and low resistance.
［問題点を解決するための手段］ 第１の発明に係わる薄膜トランジスタは、タンタルまた
はシリサイドからなる層とモリブデン、クロム、ニッケ
ルまたはニッケルクロムからなる層とを交互にかつそれ
ぞれの層数が２層以上となるように積層させてゲート電
極を構成したことを特徴とする。[Means for Solving the Problems] In the thin film transistor according to the first aspect of the present invention, the layers made of tantalum or silicide and the layers made of molybdenum, chromium, nickel or nickel chromium are alternately arranged and the number of layers is two or more. It is characterized in that the gate electrode is formed by stacking so that
第２の発明に係わる薄膜トランジスタは、クロム、ニッ
ケルまたはニッケルクロムとタンタルとの混合または合
金によりゲート電極を構成したことを特徴とする。The thin film transistor according to the second invention is characterized in that the gate electrode is made of chromium, nickel or a mixture or alloy of nickel chromium and tantalum.
［実施例］ この発明の実施例が上記従来例に対して特徴を有する点
はゲート電極の構成にある。[Embodiment] The feature of the embodiment of the present invention over the above-mentioned conventional example lies in the structure of the gate electrode.
第１図の第１の実施例では基板１の上のゲート電極２は
タンタルによりなる耐熱、耐強酸性金属2aと、タンタル
以外のモリブデンMo、ニッケルクロム合金NiCr、クロム
Cr、ニッケルNiなどの耐熱、低抵抗金属2bとが交互にス
パッタにより積層形成されている。この場合、耐強酸性
金属2aの各膜厚は10nm以下、好ましくは３〜5nm以下に
する。10nm以上にするとエッチング液の浸み込みでゲー
ト電極パターンが侵される。このスパッタにあたって
は、同一スパッタ用ターゲットに２種類の金属材料を配
置してもよいし、二つのターゲットを交互にスパッタし
てもよい。基板１に最初にスパッタされる膜はタンタル
の耐熱、耐強酸性金属2aが好ましいが他方の低抵抗金属
2bであってもよい。In the first embodiment of FIG. 1, the gate electrode 2 on the substrate 1 is made of tantalum, which is a heat-resistant and strong acid-resistant metal 2a, and molybdenum Mo other than tantalum, nickel-chromium alloy NiCr, chromium.
Heat-resistant and low-resistance metals 2b such as Cr and nickel Ni are alternately layered by sputtering. In this case, the film thickness of the strong acid resistant metal 2a is 10 nm or less, preferably 3 to 5 nm or less. When the thickness is 10 nm or more, the etching solution penetrates into the gate electrode pattern. In this sputtering, two kinds of metal materials may be arranged on the same sputtering target, or two targets may be alternately sputtered. The first sputtered film on the substrate 1 is preferably a tantalum heat-resistant and strong acid-resistant metal 2a, but the other low-resistance metal.
It may be 2b.
第２図の第２の実施例では基板１上のゲート電極２はタ
ンタルよりなる耐熱、耐強酸性金属２とモリブデンなど
の耐熱、低抵抗金属2bとがミックス状態で形成されてい
る。スパッタにあたってはタンタルとそれ以外のモリブ
デンなどの金属とを粉末状にしたものをミックスした焼
結型のものをターゲットにしておこなえばよい。タンタ
ルの含有割合は１〜99％で可能であるが、通常30〜70％
位が用いられる。なお二種類の金属は合金状態であって
もよい。In the second embodiment shown in FIG. 2, the gate electrode 2 on the substrate 1 is made of heat-resistant tantalum, a strong acid-resistant metal 2 and a heat-resistant low-resistance metal 2b such as molybdenum in a mixed state. The sputtering may be performed by using a target of a sintered type in which tantalum and a metal other than molybdenum such as molybdenum are mixed. The content of tantalum can be 1 to 99%, but it is usually 30 to 70%.
Rank is used. The two kinds of metals may be in an alloy state.
上記第１実施例でタンタルよりなる耐熱、耐強酸性金属
2aとモリブデンよりなる耐熱、低抵抗金属2bを、50wt％
ずつの比率で形成したもの、および第２の実施例でタン
タルとモリブデンを50wt％ずつの比で合金化したものの
抵抗値はモリブデンだけで形成した場合の1.5倍程度で
あり、抵抗値の著しい増加はなかった。またこれらを塩
酸と塩化鉄系のITOエッチング液に浸してITOのエッチン
グ時間だけ漬けたが、ゲート電極パターンのサイドエッ
チングや電極膜のハガレは生じなかった。また薄膜トラ
ンジスタ製造プロセスに入れたところ、ゲートラインの
断線が減少しITOエッチング工程の影響は認められなか
った。Heat resistant and strong acid resistant metal made of tantalum in the first embodiment
50wt% of heat resistant and low resistance metal 2b consisting of 2a and molybdenum
The resistance value of the alloy formed with each of them and the alloy of tantalum and molybdenum with the ratio of 50 wt% in the second embodiment is about 1.5 times that of the alloy formed with only molybdenum, and the resistance value significantly increases. There was no. Also, these were immersed in hydrochloric acid and iron chloride-based ITO etching solution and immersed for the etching time of ITO, but side etching of the gate electrode pattern and peeling of the electrode film did not occur. In addition, when it was put into the thin film transistor manufacturing process, the disconnection of the gate line was reduced and the effect of the ITO etching process was not recognized.
上記実施例では耐熱、耐強酸性金属2aとしてタンタルを
用いているが、その代りにタンタルとシリコンの合金Ta
Si2にしてもよく、またその中に微量のボロンや炭素、
窒素、酸素等が混入したものであってもよい。Although tantalum is used as the heat-resistant and strong acid-resistant metal 2a in the above embodiment, the alloy Ta of tantalum and silicon is used instead.
Si 2 may also be used, and a small amount of boron or carbon,
It may be a mixture of nitrogen and oxygen.
さらに耐熱、強酸性金属2aとしてはタンタルの代りにモ
リブデン、タングステン、チタンなどの耐熱、低抵抗金
属のシリサイドを用いてもよい。また耐熱、耐強酸性金
属2aおよび耐熱、低抵抗金属2bはそれぞれ一種類ずつの
材料より構成するものに限らず、二種類以上の材料を用
いて積層あるいは合金などにしてもよい。Further, as the heat-resistant and strongly acidic metal 2a, a silicide of a heat-resistant, low-resistance metal such as molybdenum, tungsten or titanium may be used instead of tantalum. Further, the heat resistant / strong acid resistant metal 2a and the heat resistant / low resistance metal 2b are not limited to be composed of one kind of material each, and may be laminated or alloyed using two or more kinds of materials.
ゲート電極２の形成方法としては、スパッタ法に限るも
のではなく、蒸着法やCVD法を用いてもよい。The method of forming the gate electrode 2 is not limited to the sputtering method, and an evaporation method or a CVD method may be used.
［発明の効果］ 本発明によれば、ゲート電極が耐強酸性および低抵抗性
を有する薄膜トランジスタを得ることができる。[Effects of the Invention] According to the present invention, a thin film transistor whose gate electrode has strong acid resistance and low resistance can be obtained.
第１図はこの発明の実施例の断面図、第２図は他の実施
例の断面図、第３図（Ａ）〜（Ｄ）は従来例における薄
膜トランジスタの製造工程を追って示す断面図である。 ２……ゲート電極 2a……耐熱、耐強酸性金属 2b……耐熱、低抵抗金属。FIG. 1 is a sectional view of an embodiment of the present invention, FIG. 2 is a sectional view of another embodiment, and FIGS. 3A to 3D are sectional views showing a manufacturing process of a thin film transistor in a conventional example. . 2 ... Gate electrode 2a ... Heat resistant, strong acid resistant metal 2b ... Heat resistant, low resistance metal.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 白井 勝夫 栃木県那須郡塩原町大字下田野531−１ 日本プレシジョン・サーキッツ株式会社内 (56)参考文献 特開 昭60−110165（ＪＰ，Ａ) 特開 昭61−42962（ＪＰ，Ａ) 特開 昭62−145870（ＪＰ，Ａ) 特開 昭62−205656（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Katsuo Shirai 531-1 Shimodano, Shiobara-cho, Nasu-gun, Tochigi Prefecture Within Japan Precision Circuits Co., Ltd. (56) Reference JP-A-60-110165 (JP, A) Kai 61-42962 (JP, A) JP 62-145870 (JP, A) JP 62-205656 (JP, A)
Claims (2)
リブデン、クロム、ニッケルまたはニッケルクロムから
なる層とを交互にかつそれぞれの層数が２層以上となる
ように積層させてゲート電極を構成したことを特徴とす
る薄膜トランジスタ。1. A gate electrode is formed by alternately stacking layers of tantalum or silicide and layers of molybdenum, chromium, nickel or nickel chromium so that the number of layers is two or more. Characteristic thin film transistor.
タンタルとの混合または合金によりゲート電極を構成し
たことを特徴とする薄膜トランジスタ。2. A thin film transistor comprising a gate electrode made of chromium, nickel, or a mixture or alloy of nickel chromium and tantalum.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62081643A JPH0671082B2 (en) | 1987-04-02 | 1987-04-02 | Thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62081643A JPH0671082B2 (en) | 1987-04-02 | 1987-04-02 | Thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63246873A JPS63246873A (en) | 1988-10-13 |
| JPH0671082B2 true JPH0671082B2 (en) | 1994-09-07 |
Family
ID=13752021
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62081643A Expired - Fee Related JPH0671082B2 (en) | 1987-04-02 | 1987-04-02 | Thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0671082B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USD562010S1 (en) | 2004-05-20 | 2008-02-19 | Newell Operating Company | Ergonomic paint brush sleeve |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5225364A (en) * | 1989-06-26 | 1993-07-06 | Oki Electric Industry Co., Ltd. | Method of fabricating a thin-film transistor matrix for an active matrix display panel |
| JP2558351B2 (en) * | 1989-06-29 | 1996-11-27 | 沖電気工業株式会社 | Active matrix display panel |
| JPH0820645B2 (en) * | 1989-09-19 | 1996-03-04 | シャープ株式会社 | Active matrix display |
| US5132745A (en) * | 1990-10-05 | 1992-07-21 | General Electric Company | Thin film transistor having an improved gate structure and gate coverage by the gate dielectric |
| DE4192351T (en) * | 1990-10-05 | 1992-10-08 |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0673379B2 (en) * | 1983-11-21 | 1994-09-14 | 松下電器産業株式会社 | Semiconductor device and manufacturing method thereof |
| JP2573558B2 (en) * | 1984-08-07 | 1997-01-22 | 松下電器産業株式会社 | Semiconductor device and manufacturing method thereof |
| JPS62145870A (en) * | 1985-12-20 | 1987-06-29 | Matsushita Electric Ind Co Ltd | Thin film transistor |
| JPS62205656A (en) * | 1986-03-06 | 1987-09-10 | Toshiba Corp | Semiconductor device |
-
1987
- 1987-04-02 JP JP62081643A patent/JPH0671082B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USD562010S1 (en) | 2004-05-20 | 2008-02-19 | Newell Operating Company | Ergonomic paint brush sleeve |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63246873A (en) | 1988-10-13 |
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| LAPS | Cancellation because of no payment of annual fees |