JPH0673379B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device that constitutes an image display device in combination with liquid crystal.

Configuration of conventional example and its problems FIG. 1 shows a switching MIS transistor 1 and a liquid crystal cell 2.
2 is an equivalent circuit of an image display device in which a unit picture element is connected by a scanning line 4 and a signal line 5 to form a two-dimensional matrix. Apply a scan pulse to scan line 4 and apply lateral MOS
The transistor 1 is turned on, and the video signal voltage is written in the liquid crystal cell 2 from the signal terminal group (y _j , y _{j + 1} ...). Next, an image display function is provided by sequentially scanning the scan pulses in the vertical direction (x _i , x _{i + 1} , ...). The charges written in the liquid crystal cell 2 corresponding to the video signal are discharged through the off resistance of the MIS transistor 1 and the resistance of the liquid crystal cell until the next writing, and the time constant of the discharge is the writing speed (1/60 (Seconds), it can display TV images. The auxiliary capacitor 3 having a capacity sufficiently larger than that of the liquid crystal cell 2 is often added to the ground line 6 as a load of the MIS transistor 1 for the reason described above. The common electrode 7 is fixed at 6 V, for example, and the video signal voltage is 0 to 6 V and 6 to 12 every time writing is performed.
The liquid crystal cell 2 is driven by alternating current by switching with V.

Now, FIG. 2 is a plan view of a unit picture element when an MIS transistor using amorphous silicon (hereinafter abbreviated as a-Si) as a semiconductor material is integrated as a switching element, and FIG. 3 is a plan view of FIG. A cross-sectional view of a main part on the line A ′ is shown. The manufacturing method is as described below.

A first transparent conductive layer 9 is formed on the entire main surface of the transparent insulating substrate such as the glass plate 8 or selectively, and then a transparent insulating layer such as silicon oxide 10 is deposited on the entire surface. The first metal layer 4 made of, for example, molybdenum, which constitutes the gate of the MIS transistor and also constitutes the scanning line, is formed.
And a pixel electrode 11 made of a transparent conductive layer and a silicon oxide layer 10
Selectively formed on top. Next, a gate insulating layer 12 made of, for example, Si ₃ N ₄ and an a-Si layer containing almost no impurities are deposited on the entire surface by glow discharge decomposition containing SiH ₄ system gas as a main component, and an island-shaped a-Si layer 13 is formed. To form Si on the pixel electrode 11.
_An opening 14 is formed in the ₃ N ₄ layer 12. Although not shown, at the same time, Si ₃ N ₄ on the scanning line 4 in a region far from the picture element part
An opening is also formed in the layer. After that, a pair of metal layers that partially overlap with the gate metal layer 4 are selectively formed of, for example, aluminum on the island-shaped a-Si layer 13. One of them constitutes the video signal line 5, and the other one is formed to include the opening 14, and constitutes a connection line 15 between the MIS transistor 1 and the pixel electrode 11. Although not shown, the extraction electrode to the scanning line 4 is also formed when the second metal layers 5 and 15 are formed as described above.

In order to obtain an image display device, for example, a polyimide thin film is applied to the surface of the above-mentioned semiconductor device, cured and then subjected to orientation treatment, and a glass plate 16 having a transparent conductive layer 7 deposited on one main surface and the semiconductor. The liquid crystal 17 may be filled between the apparatus and the polarizing plates 18 may be arranged above and below.

In order to improve the ohmic property between the a-Si layer 13 and the source / drain wirings 5 and 15, an a-Si layer containing, for example, phosphorus or boron serving as a donor or an acceptor is interposed between them. It is enough.

Although molybdenum is taken as the gate metal layer 4 in the semiconductor device described above, other examples using chromium, nichrome or the like are known. Since the gate metal layer 4 also serves as a scanning line, the lower the resistance value is, the better. When the film thickness is 1500Å, the resistance value of 1 to 10 Ω / □ can be obtained with the above-mentioned metals, which is not a practical problem. However, molybdenum is extremely soluble in an oxidizing acid such as nitric acid, and in the steps after the introduction of molybdenum, fuming nitric acid cannot be used in the resist removing and cleaning steps. Even in a process in which molybdenum is not exposed, molybdenum locally disappears through the pinholes in the gate insulating layer 12, and thus there is a drawback that causes a fatal line defect in an image display device.
Further, chromium and nichrome are chemically stable because a thin oxide film is easily formed on the surface and acts as a passive state. However, the existence of this stable oxide film causes a great obstacle when forming the extraction wiring to the outside.

As described above, the surface of the scan line 4 is exposed to fuming nitric acid or O ₂ plasma for removing the Si ₃ N ₄ etching liquid or etching gas and the resist in a region far away from the pixel portion. , A thin oxide film is formed as a passive state.
Therefore, the metal forming the extraction electrode comes into contact with the scanning line of chromium, nichrome or the like via the thin oxide film. Therefore, unless heat treatment at 400 to 500 ° C. or higher is performed, the contact resistance becomes unstable and high, the operation of the MIS transistor becomes uncertain, and the function as the image display device cannot be obtained. On the other hand, although a-Si formed by glow discharge deposition depends on the manufacturing conditions, heating at approximately 300 ° C. or higher causes hydrogen that compensates for dangling bonds to be released and the film quality as a semiconductor material to be significantly deteriorated.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to make contact resistance between a scanning line and a take-out wiring low and reliable without heat treatment. Further, the present invention is to lower the resistance of the scanning line.

Configuration of the Invention The main point of the present invention lies in the introduction of metal silicide as a gate electrode material that determines the characteristics of a semiconductor element and chromium as a scanning line material for low resistance. explain.

Description of Embodiments FIG. 4 is a sectional view of an essential part of an image display device according to an embodiment of the present invention. The difference from FIG. 3 which is a conventional example is that a gate electrode of a MIS transistor is formed and a scanning line is formed. The metal layer that also constitutes is 2 of chromium 19 and molybdenum silicide 20.
The other structure and manufacturing method are as described in FIG. 3. Acid- and fluorine-resistant metal suicides such as molybdenum, tantalum, or tungsten suicide are mainly formed by sputter deposition. Have. However, 10 on chrome 19 with a film thickness of 1000Å
When the molybdenum silicide 20 having a film thickness of 00 Å is deposited, the sheet resistance value is reduced to 3 to 4 Ω / □, which is nearly two digits, so that the resistance value of the scanning line is sufficiently low. Since chromium is likely to passivate, the metal silicide should be deposited immediately after the vapor deposition of chromium, preferably by continuous vapor deposition.

The gate electrode composed of chromium 19 and molybdenum silicide 20 is formed by depositing chromium and metal silicide and then selectively etching the metal silicide and chromium. Abnormal etching such as cutting does not occur.
Chromium has a high heat resistance, and the surface quality of the transparent gate insulating layer 12 made of Si ₃ N ₄ is not deteriorated by the heat treatment, and the film quality of the gate insulating layer 12 formed on the gate electrode is good. In the present invention, it is possible to obtain a highly reliable method for manufacturing an amorphous MIS transistor, in which a short circuit or the like of the wiring is unlikely to occur.

Further, an ohmic property may be improved by interposing an amorphous semiconductor layer containing silicon as a main component and an impurity serving as a donor or an acceptor between the a-Si layer 13 and the source / drain wirings 5, 15. Further, the auxiliary capacitor 3 can be formed via the transparent insulating layer 10 on which the transparent conductive layer 9 and the pixel electrode 11 are formed. In order to reduce the parasitic capacitance formed between the scanning line or the signal line 5, it is preferable that the transparent conductive layer 9 is selectively patterned instead of the entire surface. In this case, the transparent conductive layer 9 corresponds to the ground wire 6 in FIG.

EFFECTS OF THE INVENTION As is apparent from the above description, in the present invention, the resistance value of the scanning line is almost the same as that of the conventional single-layer metal, the metal silicide can withstand the hydrofluoric acid-based etching liquid, and the oxygen Thin in the resist removal process using plasma, fuming nitric acid, etc.
Even if the SiO ₂ film is formed, it can be easily removed with diluted hydrofluoric acid. Therefore, at the time of forming the extraction electrode on the scanning line, there is no possibility of forming a barrier between the scanning line, that is, the metal silicide and the extraction electrode material, and low contact resistance can be obtained. In addition, since the present invention uses chromium, it is possible to form a highly reliable gate electrode and achieve good insulation.
-It is a manufacturing method suitable for Si TET.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram of an image display device including a combination of a MIS transistor and a liquid crystal cell, FIG. 2 is a schematic plan view of a unit pixel of the device, and FIG. 3 is a unit pixel A- of FIG. FIG. 4 is a schematic sectional view of an image display device according to an embodiment of the present invention, and FIG. 1 ... MIS transistor, 2 ... Liquid crystal cell, 3 ... Auxiliary capacitance, 4 ... Scan line, 5 ... Signal line, 19 ... Chrome, 20
…… Metal silicide.

Claims (4)

[Claims] 1. A transparent conductive layer and a first metal layer consisting of two layers of chromium and metal silicide are selectively formed on an insulating transparent substrate, and a gate insulating layer and a gate insulating layer are formed on the first metal layer. An island-shaped non-single-crystal semiconductor layer containing silicon as a main component is formed via the first transparent insulating layer, and an opening is formed in the first transparent insulating layer formed on the transparent conductive layer. One of a pair of second metal layers selectively formed on the island-shaped non-single-crystal semiconductor layer so as to partially overlap with the first metal layer through the opening to the transparent conductive layer. A semiconductor device, which is in electrical contact with the semiconductor device. 2. The semiconductor device according to claim 1, wherein the metal forming the metal silicide contains at least one of tantalum, tungsten, and molybdenum. 3. A patent characterized in that a non-single-crystal semiconductor layer containing silicon as a main component and containing an impurity serving as a donor or an acceptor is interposed between the island-shaped non-single-crystal semiconductor layer and the second metal layer. The semiconductor device according to claim 1. 4. A step of selectively forming a transparent conductive layer on an insulating transparent substrate, a step of selectively forming a first metal layer composed of two layers of chromium and metal silicide, and a first metal. On a part of the layer, a transparent insulating layer to be a gate insulating layer is formed on the front surface, and then an island-shaped non-single-crystal semiconductor layer containing silicon as a main component is selectively formed on a part of the first metal layer. A step of forming an opening in the insulating layer on the transparent conductive layer, and overlapping one part of the first metal layer on the island-shaped non-single-crystal semiconductor layer, and one of the openings forms the opening. A semiconductor device comprising a step of selectively forming a second metal layer that is in contact with the transparent conductive layer via a metal silicide layer, and the metal silicide layer is deposited immediately after the chromium layer is deposited. Manufacturing method.