JPH067239B2 - Electro-optical device - Google Patents
Electro-optical deviceInfo
- Publication number
- JPH067239B2 JPH067239B2 JP62202716A JP20271687A JPH067239B2 JP H067239 B2 JPH067239 B2 JP H067239B2 JP 62202716 A JP62202716 A JP 62202716A JP 20271687 A JP20271687 A JP 20271687A JP H067239 B2 JPH067239 B2 JP H067239B2
- Authority
- JP
- Japan
- Prior art keywords
- electro
- optical device
- circuit
- shift register
- control line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/1306—Details
- G02F1/1309—Repairing; Testing
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136254—Checking; Testing
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Liquid Crystal (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Liquid Crystal Display Device Control (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は表示装置、プリンタ用シャッタ等の電気光学装
置、特にシフトレジスタ回路を同一基板上に内蔵した電
気光学装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electro-optical device such as a display device and a printer shutter, and more particularly to an electro-optical device having a shift register circuit built in on the same substrate.
シフトレジスタ回路を内蔵したマトリクス電気光学装置
において、線と制御線の少なくとも一方の終端に検査用
スイッチングトランジスタを設けたものであり、画素選
択トランジスタ駆動用回路の動作試験と同時に信号線、
制御線の断線チェック及び相互の短絡チェックを行える
ようにしたものである。In a matrix electro-optical device including a shift register circuit, an inspection switching transistor is provided at the end of at least one of a line and a control line, and at the same time as an operation test of a pixel selection transistor driving circuit, a signal line,
The control line is checked for disconnection and mutual short circuits.
〔従来の技術およびその問題点〕 半導体薄膜を用いた集積回路装置、特にマトリクス配置
型液晶表示装置において、現在シフトレジスタ回路に代
表される画素選択トランジスタ駆動用回路(以下駆回路
と称す)を画素部と同一基板上に同工程で作り込む試み
が多くなされており、実用化の方向にある。しかしなが
ら前記駆動回路を各信号線及び制御線に直結し同一基板
上に作り込んだだけでは、前記駆動回路の動作試験を行
うことが困難でかつ信号線、制御線の断線チェック及び
相互の短絡チェックを別の検査工程で行わなければなら
ず検査コストが増す原因となってしまう。[Prior Art and its Problems] In an integrated circuit device using a semiconductor thin film, particularly in a matrix-arranged liquid crystal display device, a pixel selection transistor driving circuit (hereinafter referred to as a driving circuit) currently represented by a shift register circuit is a pixel. Many attempts have been made to make it on the same substrate as the part in the same process, and it is in the direction of practical application. However, it is difficult to perform an operation test of the drive circuit by directly connecting the drive circuit to each signal line and control line and forming them on the same substrate, and check for disconnection of the signal line and control line and mutual short circuit check. Must be performed in another inspection process, which causes an increase in inspection cost.
第1図に示されるのは、駆動回路を画素部の信号線及び
制御線と直接つないで同一基板上に作り込んだだけの駆
動回路内蔵型液晶表示装置の回路図で画素選択トランジ
スタ1及び信号線2、制御線3を有する画素部と前記画
素選択トランジスタ1を駆動する駆動回路(画素信号用
シフトレジスタ回路4、制御信号用シフトレジスタ回路
5に大別される)部が同一基板上に作り込まれている。FIG. 1 is a circuit diagram of a liquid crystal display device with a built-in drive circuit, in which the drive circuit is directly connected to the signal lines and control lines of the pixel section and is formed on the same substrate. A pixel portion having lines 2 and control lines 3 and a driving circuit (driving circuit for pixel signal 4 and control signal shift register circuit 5) for driving the pixel selection transistor 1 are formed on the same substrate. It is embedded.
本発明は、これらの欠点を除去するため、同一基板上に
内蔵された駆動回路、特にシフトレジスタ回路の動作試
験と信号線、制御線の断線チェック及び相互の短絡チェ
ックをより短い検査工程でできる様な構造の電気光学装
置を提供することを目的とする。In order to eliminate these drawbacks, the present invention can perform an operation test of a drive circuit, especially a shift register circuit and a disconnection check of signal lines and control lines and a mutual short-circuit check in a shorter inspection process on the same substrate. It is an object to provide an electro-optical device having such a structure.
以下、図面を用いて本発明の実施例を詳細に説明する。
第2図は本発明の一実施例を示す回路図で、第1図に示
されるものと同様に画素部と駆動回路部が同一基板に作
り込まれ直結されているが画素信号用シフトレジスタ回
路4に接続されている信号線2及び制御信号用シフトレ
ジスタ回路5に接続されている制御線3のそれぞれの線
の終端にスイッチングトランジスタ6が設けられてお
り、前記各スイッチングトランジスタ6のゲート電極は
次段の信号線もしくは制御線に接続されている。また前
記各スイッチングトランジスタ6のソース電極は信号線
側及び制御線側それぞれに共通電極として取り出されて
いる。前記共通電極及び画素信号用シフトレジスタ回路
4へ入力されるクロック信号とデータ信号、また制御信
号用シフトレジスタ5へ入力されるクロック信号とデー
タ信号を使って逐次操作することによって、前記スイッ
チングトランジスタ6を信号線もしくは制御線ごとにス
イッチングすることができ、前記駆動回路の動作試験と
同検査工程において、信号線2、制御線3それぞれの断
線チェック及び相互の短絡チェックを行うことができ
る。Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 2 is a circuit diagram showing an embodiment of the present invention. As in the case shown in FIG. 1, the pixel portion and the driving circuit portion are formed on the same substrate and directly connected to each other. A switching transistor 6 is provided at the end of each of the signal line 2 connected to 4 and the control line 3 connected to the control signal shift register circuit 5, and the gate electrode of each switching transistor 6 is It is connected to the next signal line or control line. The source electrode of each switching transistor 6 is taken out as a common electrode on the signal line side and the control line side. The switching transistor 6 is sequentially operated by using the clock signal and the data signal input to the common electrode and pixel signal shift register circuit 4, and the clock signal and the data signal input to the control signal shift register 5. Can be switched for each signal line or control line, and disconnection check and mutual short-circuit check of each of the signal line 2 and control line 3 can be performed in the operation test and the inspection process of the drive circuit.
また実際液晶表示装置として使用する際には、前記共通
電極を接地電位に接続していれば動作に影響を与えるこ
とはない。Further, when actually used as a liquid crystal display device, if the common electrode is connected to the ground potential, it does not affect the operation.
また第3図は、本発明の他の実施例を示す回路図で前記
本発明の一実施例と構成的には同様であるが、信号線2
もしくは制御線3の終端に設けられたスイッチングトラ
ンジスタ6が画素部の上下及び左右に配され、それに従
ってシフトレジスタ回路4及び5を画素部の上下及び左
右に配置したことを特徴とする。これにより前記各シフ
トレジスタ回路4及び5の動作速度は1/2に軽減され、
かつ前記スイッチングトランジスタ6は分割配置のため
レイアウト上無理がない。またこの場合各スイッチング
トランジスタ6のソース電極をまとめた共通電極は画素
部の各辺ごとに集められ対応する各シフトレジスタ回路
の動作試験の際、信号読み取り端子として用いられる。Further, FIG. 3 is a circuit diagram showing another embodiment of the present invention, which is similar in configuration to the one embodiment of the present invention, but the signal line 2
Alternatively, the switching transistor 6 provided at the end of the control line 3 is arranged above and below and to the left and right of the pixel portion, and the shift register circuits 4 and 5 are arranged above and below and to the left and right of the pixel portion accordingly. This reduces the operating speed of each shift register circuit 4 and 5 to half,
In addition, since the switching transistor 6 is divided and arranged, there is no problem in layout. Further, in this case, the common electrode, which is a collection of the source electrodes of the switching transistors 6, is collected for each side of the pixel portion and used as a signal reading terminal in the operation test of the corresponding shift register circuit.
以上のごとく本発明によれば、シフトレジスタ回路に代
表される駆動回路の動作試験と信号線、制御線それぞれ
の断線チェック及び相互の短絡チェックを同検査工程で
行うことが可能である。As described above, according to the present invention, it is possible to perform the operation test of the drive circuit represented by the shift register circuit, the disconnection check of each of the signal line and the control line, and the mutual short circuit check in the same inspection process.
第1図は画素部と駆動回路部を同一基板上に作り込み直
結しただけの液晶表示装置の回路図で、第2図は本発明
の一実施例における電気光学装置の回路図で、第3図は
本発明の他の実施例における電気光学装置の回路図であ
る。 1・・・画素選択トランジスタ 2・・・信号線 3・・・制御線 4・・・画素信号用シフトレジスタ回路 5・・・制御信号用シフトレジスタ回路 6・・・スイッチングトランジスタFIG. 1 is a circuit diagram of a liquid crystal display device in which a pixel portion and a drive circuit portion are formed on the same substrate and directly connected, and FIG. 2 is a circuit diagram of an electro-optical device according to an embodiment of the present invention. The drawing is a circuit diagram of an electro-optical device according to another embodiment of the present invention. DESCRIPTION OF SYMBOLS 1 ... Pixel selection transistor 2 ... Signal line 3 ... Control line 4 ... Pixel signal shift register circuit 5 ... Control signal shift register circuit 6 ... Switching transistor
Claims (4)
電気光学装置において、信号線と制御線の少なくとも一
方の終端に検査用スイッチングトランジスタを設けたこ
とを特徴とする電気光学装置。1. A matrix electro-optical device having a built-in shift register circuit, wherein an inspection switching transistor is provided at the end of at least one of a signal line and a control line.
ートと次段の信号線もしくは制御線とをつないだ特許請
求の範囲第1項記載の電気光学装置。2. The electro-optical device according to claim 1, wherein the gate of the inspection switching transistor is connected to the signal line or control line of the next stage.
ースが共通電極として信号線、制御線について少なくと
もそれぞれ独立にとり出されていることを特徴とする特
許請求の範囲第1項記載の電気光学装置。3. The electro-optical device according to claim 1, wherein the source of the inspection switching transistor is taken out as a common electrode independently of at least a signal line and a control line.
し、前記検査用スイッチングトランジスタを信号線もし
くは制御線において少なくとも一本置きに互い違いに配
置したことを特徴とする特許請求の範囲第3項記載の電
気光学装置。4. The shift register is arranged above and below a pixel portion, and at least every other one of the switching transistors for inspection is arranged alternately in a signal line or a control line. The electro-optical device described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62202716A JPH067239B2 (en) | 1987-08-14 | 1987-08-14 | Electro-optical device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62202716A JPH067239B2 (en) | 1987-08-14 | 1987-08-14 | Electro-optical device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6352121A JPS6352121A (en) | 1988-03-05 |
| JPH067239B2 true JPH067239B2 (en) | 1994-01-26 |
Family
ID=16461972
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62202716A Expired - Lifetime JPH067239B2 (en) | 1987-08-14 | 1987-08-14 | Electro-optical device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH067239B2 (en) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0648551Y2 (en) * | 1986-10-27 | 1994-12-12 | カシオ計算機株式会社 | Active matrix display |
| JP2653099B2 (en) * | 1988-05-17 | 1997-09-10 | セイコーエプソン株式会社 | Active matrix panel, projection display and viewfinder |
| JP2618042B2 (en) * | 1989-06-15 | 1997-06-11 | 松下電子工業株式会社 | Inspection method for image display device |
| JP2633360B2 (en) * | 1989-06-16 | 1997-07-23 | 松下電子工業株式会社 | Image display device |
| JP2792634B2 (en) * | 1991-06-28 | 1998-09-03 | シャープ株式会社 | Active matrix substrate inspection method |
| EP0760508B1 (en) | 1995-02-01 | 2005-11-09 | Seiko Epson Corporation | Liquid crystal display device, and method of its driving |
| TW331599B (en) * | 1995-09-26 | 1998-05-11 | Toshiba Co Ltd | Array substrate for LCD and method of making same |
| JP4147594B2 (en) | 1997-01-29 | 2008-09-10 | セイコーエプソン株式会社 | Active matrix substrate, liquid crystal display device, and electronic device |
| WO1998048317A1 (en) | 1997-04-18 | 1998-10-29 | Seiko Epson Corporation | Circuit and method for driving electrooptic device, electrooptic device, and electronic equipment made by using the same |
| JP4498489B2 (en) * | 1999-03-19 | 2010-07-07 | シャープ株式会社 | Liquid crystal display device and manufacturing method thereof |
| JP2003029296A (en) * | 2001-07-13 | 2003-01-29 | Toshiba Corp | Array substrate, inspection method therefor, and liquid crystal display device |
| JP4790292B2 (en) * | 2004-10-25 | 2011-10-12 | 三星電子株式会社 | Array substrate and display device having the same |
| KR101093229B1 (en) * | 2005-01-06 | 2011-12-13 | 삼성전자주식회사 | Array substrate and display device having same |
| US9583063B2 (en) | 2013-09-12 | 2017-02-28 | Semiconductor Energy Laboratory Co., Ltd. | Display device |
| CN108831359B (en) * | 2018-06-22 | 2020-08-11 | 惠科股份有限公司 | Display panel and display device thereof |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5799688A (en) * | 1980-12-11 | 1982-06-21 | Sharp Kk | Display driving circuit |
| JPS57100467A (en) * | 1980-12-15 | 1982-06-22 | Suwa Seikosha Kk | Ic substrate for active matrix display body |
| JPS57104987A (en) * | 1980-12-22 | 1982-06-30 | Hokushin Electric Works | Matrix type driver |
| JPS584180A (en) * | 1981-06-30 | 1983-01-11 | セイコーエプソン株式会社 | Active matrix substrate |
| JPS5857188A (en) * | 1981-09-30 | 1983-04-05 | キヤノン株式会社 | Short-circuit detection circuit for liquid crystal display |
| JPS5895383A (en) * | 1981-11-30 | 1983-06-06 | 株式会社東芝 | Matrix type display |
| JPS5924892A (en) * | 1982-08-03 | 1984-02-08 | 日本電信電話株式会社 | Liquid crystal display |
| JPS602989A (en) * | 1983-06-20 | 1985-01-09 | セイコーエプソン株式会社 | Ic substrate for active matrix display body |
-
1987
- 1987-08-14 JP JP62202716A patent/JPH067239B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6352121A (en) | 1988-03-05 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term | ||
| S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
| R370 | Written measure of declining of transfer procedure |
Free format text: JAPANESE INTERMEDIATE CODE: R370 |