JPH0673365B2 - Semiconductor device - Google Patents

Description

Description: [Object of the Invention] (Field of Industrial Application) The present invention relates to a semiconductor device in which a plurality of semiconductor chips are arranged on a supporting substrate (such as a printed circuit board), and particularly to a memory module. Used for.

(Prior Art) FIG. 9 shows a conventional example of the above semiconductor device. Here, 11 is a support substrate, 12 is an LSI chip, 13 is an output terminal (pad), 14 is an input terminal, 15 is an output terminal lead wire, and 16 is an input terminal lead wire. However, in this structure, since the wirings cross on the supporting substrate 11, crossover wiring is required, and there are problems that the wiring area on the supporting substrate 11 increases.

FIG. 10, realizes a memory module using the principle of Fig. 9, 12 ₁ to 12 ₈ memory chips, the chip selection circuit 41, V _cc is the power supply, GND is grounded, A ₀ to A ₁₄ address signals, I / O1~I / O8 input and output signals, a, B, C are address signals for chip select, CS ₁ to CS ₈ is a chip select line. This first
Similar to the one in FIG. 9, the one in FIG. 10 has a problem of wiring crossover on the substrate 11, a problem of increasing the wiring area on the substrate 11, and a wiring relay point on the substrate 11 at the time of connection between the chip and the wiring. There are problems such as requiring a lot of.

(Problems to be Solved by the Invention) Japanese Patent Laid-Open No. 2-19890 discloses a solution to the above problems. FIG. 11 shows a part of the publication, in which 21 is an LSI chip, 22 is an output terminal pad, 23 is an input terminal pad, 24 is a common input terminal pad, and 25 is a conductor wiring. In this device, a common input terminal pad 24 is provided on the chip 21, and those common to these are wired by the conductor wiring 25 on the chip 21. In this way, the inter-pad wiring 25
Wiring crossover problem, board 11
Although the above area reduction problem is somewhat improved, it is still insufficient. For example, the wiring 25 is only a part and is only in the lateral direction, and the problem of relay wiring between the pads 22, 23, 24 and the support substrate 11 has not been sufficiently solved. Therefore, there are many problems, such as a limit on the area of the support substrate 11.

Therefore, an object of the present invention is to provide a semiconductor device that improves the above problems and obtains good results in electrical characteristics and the like.

[Structure of the Invention] (Means and Actions for Solving the Problems) The present invention provides (1) a plurality of semiconductor chips having the same kind of wiring arranged on a support substrate, and the plurality of chips are respectively arranged on the plurality of chips. It is characterized in that the terminal pads are omitted and long wires arranged so as to face from one side to the other side of the chip are provided, and common wires between the long wires of the adjacent chips are directly connected by conductors. It is a semiconductor device. The present invention also provides (2) the adjacent chips are partially overlapped with each other so that the common wirings between them are opposed to each other, and the common wirings of the adjacent chips are connected to each other via the protruding electrodes between them. The semiconductor device according to (1) above. (3) The connection between the wiring of the support substrate and the wiring of the chip is
The semiconductor device according to (1) or (2) above, which is performed by the one located at the end of the plurality of chips. Further, the present invention is (4) the semiconductor device according to (1), in which there is substantially no gap between adjacent chips. (5) Each of the plurality of chips is provided with a dedicated chip selection circuit, and the common wiring for these chip selection circuits selects a chip to be driven according to any one of (1) to (4) above. The semiconductor device described above. (6) The semiconductor device according to (5), wherein the plurality of chips are memory chips. Further, the present invention is (7) the semiconductor device according to (6), in which some of the chips for giving redundancy to the memory module are mixed in the plurality of chips.

That is, the present invention employs a plurality of chips whose wirings can be of the same type, such as a memory, as the chips mounted on the support substrate. In addition, for example, a multilayer wiring technique is used for the chips so that a plurality of chips can be arranged without any vertical and horizontal gaps. In addition, the chip selection circuit has each dedicated chip built in,
A desired chip can be selected with common wiring.

As an example, in the integrated circuit chip of the memory,
Most of the input and output terminals can be connected to a common bus line including the power supply, and the only ones that cannot be shared are chip select (CS) and / or output enable signals. However, these signals are output by a logic combination circuit or a decoder circuit outside the chip,
Wired to each chip for propagation.

At present, the degree of high integration in integrated circuits is progressing. For example, a chip has tens of thousands of elements, and adding the combinational circuit or the decoder circuit thereto does not affect the size of the chip. . Therefore, in the conventional memory chip, instead of the CS input terminal, a plurality of common input signal wiring terminals are provided,
This gives the function to send the input signal to the decoder circuit with redundancy and obtain the desired output and transmit it to the conventional CS input circuit by combining circuit or fuse cutting etc., all become common to each signal etc. By directly connecting such memory chips between chips, the area of the supporting substrate is significantly reduced. In addition, it is not necessary to perform so-called wiring crossover due to common wiring, and the wiring length is small, so that the one having good electrical characteristics can be obtained.

Embodiment An embodiment of the present invention will be described below with reference to the drawings. 1A is a side view of the embodiment, FIG. 1B is a plan view of the same embodiment, FIG. 2 is a chip selection circuit (combination circuit or decoder circuit) in each chip, and FIG. 3 is a memory chip. Top view, 4th
The figure is a modification of FIG. 1 (a). Here, as an example,
32K x 8-bit SRAM (static RAM) is used. In the figure
11 is a support substrate such as a printed circuit board, 12 _{1 to} 12 ₈ are memory chips, 13 is a bump for connection, 14 is a terminal on the substrate 11, 15 is a bonding wire, 16 is a TAB connection body, and 17 is a chip selection circuit. , This is built in each chip and selects the corresponding built-in chip. The memory chip 12 of FIG. 3 is shown as a representative of each of the above chips, and its common terminal 18 is in the form of a long wiring having no pad, that is, "pad + It has a "wiring" function. Here, V _cc is a power supply, A _{0 to} A ₁₄ are address signals, I / O1 to I / O8 are input / output signals, ▲ ▼ is a write enable signal, ▲ ▼ is an output enable signal, and A to C are shown in FIG. Is a chip selection signal of. Each common terminal 18 may have bumps on both ends, may be bumps as a whole, or may be soldered.

Then, as shown in FIG. 3, the required number of common terminals 18 are arranged in parallel on the chip 12, and if necessary, they are covered with a protective film to protect the terminals, and openings are formed in the protective films at both ends of the common terminal. A part may be provided, a bump may be provided, or the like. The memory chip 12 has as few as 28 common terminals 18, but even if the number of common terminals 18 is increased, the size of the chip 12 is not affected.

The chip selection circuit 17 built in each chip activates one of the eight output signals 21 _{1 to} 21 ₈ by a combination of three signals A, B and C as shown in FIG. When the built-in chip is selected or the fuse is blown, only the one output corresponding to the chip is connected to the conventional CS input circuit.

The chip mounting on the support substrate 11 and the chip-to-chip connection are performed by the signal
Any pin 21 ₁ to 21 ₈ becomes active by -C, the common terminals of the chip having an additional circuit connected to the CS input circuit, gold, copper, and forming bumps such as solder, Figure 1 Common connection between chips is performed by the bumps 13 as described above. The bonding between the support substrate 11 and the chip is performed by the bonding wire 15 or the TAB connection body 16.

In addition, in order to add redundancy to the memory module,
Furthermore it is possible to 1 bit add, in addition to nine chips chip 12 ₀ to impart its redundancy, it may be configured as shown in Figure 4.

FIG. 5 shows an example in which the chips 12 _{1 to} 12 ₈ are arranged on the supporting substrate 11 in one row without a gap. In this case also the chip selection circuit is incorporated in each of chip 12 ₁ to 12 _8, a combination of these signals is connected to the common wiring A through C, selects the built-in chip. The wiring connection between adjacent chips may be made by wire bonding, for example.

Further, by using the vertical and horizontal multilayer wiring technology for the memory chip 12 as shown in FIG. 8 and providing the common terminals 18 in two directions of the X direction and the Y direction, the chips are arranged on the substrate 11 as shown in FIG. Wires, and bonding wires between adjacent chips
A memory module is configured by connecting at 15. An opening 31 that exposes the end of the common terminal 18 is provided at the portion to which the wire 15 is connected. Here, a 3 × 3 common terminal is shown as an example. This chip-to-chip connection is the minimum connection, and if connection integrity is required, all connectable chips may be connected.

According to the above, (a) the size of the memory module is halved as compared with the conventional one. That is, in the conventional memory module, as shown in FIGS. 9 and 10, the signal wiring of the output terminal of the chip selection circuit 41 is provided on the supporting substrate 11 and is routed to each chip, so that the wiring area on the substrate 11 is large. Nari,
It is also necessary to provide crossover wiring. 32K x
In an 8-bit SRAM, the control terminal to each chip is CS, and when eight chips are mounted to make a 256 Kbyte memory module, 27 common terminals for power supply and CS are required for each chip. This makes a total of 35, which is eight. On the other hand, in the present invention, three chips A, B, and C for chip selection and two other common terminals are used.
There are 7 in total, 30 in total. Moreover, since the terminals other than the terminal 14 in FIG. 1 are formed only on the chip as common terminals, there is almost no wiring on the support substrate 11.

(B) Since the conductor on the support substrate 11 is conventionally used for the connection between the chips, noise causes the supply voltage of the power supply line to become unstable due to the self-inductance due to the wiring length. Since the chips can be directly connected to each other, the wiring length is minimum and it is effective against noise.

(C) The number of signal terminals for chip selection (A, B, C parts) is
Depending on the number of chips used in the module, the result is as shown in FIG. 6. If the number of chips is n in the conventional method, n are required, but in the present invention, log ₂ n is sufficient, so that the CPU will have a large number of bits in the future. The wiring area can be greatly reduced as the number of layers becomes smaller. The reason for this is that the chip selection circuit is provided in each chip and is commonly connected to the common terminal.

Even when compared with FIG. 11, it can be said that the same as the conventional example except that the wiring 25 is different.

[Effects of the Invention] As described above, according to the present invention, since chips can be arranged close to each other and wiring on a supporting substrate can be eliminated, high-speed and high-density integration is possible, and chip selection for each chip is possible. Since there is a circuit and common wiring is provided, there are advantages such as chip selection in a small area.

[Brief description of drawings]

1 to 4 are configuration diagrams of an embodiment of the present invention, and FIG.
FIG. 6 is a block diagram of a different embodiment of the present invention, FIG. 6 is a table showing the effects of the above-described embodiment, FIGS. 7 and 8 are block diagrams of a further different embodiment of the present invention, and FIGS. The figure is a block diagram of a conventional example. 11 …… Support substrate, 12,12 _{1 to} 12 ₈ …… Memory chip, 13…
… Bumps, 14 …… terminals, 15 …… bonding wires, 16
…… TAB connector, 17 …… chip selection circuit, 18 …… common terminal, 31 …… opening.

Claims (7)

[Claims] 1. A plurality of semiconductor chips having the same kind of wiring are arranged on a supporting substrate, and terminal pads are omitted on each of the plurality of chips so as to face from one side to the other side of the chip. A semiconductor device characterized in that long wires arranged are provided, and common wires of long wires of adjacent chips are directly connected by a conductor. 2. The adjacent chips are partially overlapped with each other so that the common wirings between them are opposed to each other, and the common wirings of the adjacent chips are connected to each other through the protruding electrodes between them. 1. The semiconductor device according to 1. 3. The semiconductor device according to claim 1, wherein the connection between the wiring of the support substrate and the wiring of the chip is made by one located at an end of a plurality of chips. 4. The semiconductor device according to claim 1, wherein there is substantially no gap between adjacent chips. 5. A plurality of chips are respectively provided with dedicated chip selection circuits, and a chip to be driven is selected by a common wiring for these chip selection circuits.
The semiconductor device according to claim 1. 6. The plurality of chips are memory chips.
The semiconductor device according to. 7. The semiconductor device according to claim 6, wherein some of the chips for mixing the memory module with redundancy are mixed in the plurality of chips.