JPH0673381B2 - Field effect semiconductor device - Google Patents
Field effect semiconductor deviceInfo
- Publication number
- JPH0673381B2 JPH0673381B2 JP61199745A JP19974586A JPH0673381B2 JP H0673381 B2 JPH0673381 B2 JP H0673381B2 JP 61199745 A JP61199745 A JP 61199745A JP 19974586 A JP19974586 A JP 19974586A JP H0673381 B2 JPH0673381 B2 JP H0673381B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor device
- field effect
- electrode
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔技術分野〕 この発明は電界効果半導体装置に関する。Description: TECHNICAL FIELD The present invention relates to a field effect semiconductor device.
電界効果半導体装置のひとつに絶縁ゲート型電界効果ト
ランジスタがある。絶縁ゲート型電界効果トランジスタ
は、縦型構造のものが開発されてからは電力制御用等い
わゆるパワー用としての用途が拓けてきた。第２図は、
縦型構造の絶縁ゲート型電界効果トランジスタの断面構
造をあらわしたものである。縦型構造の絶縁ゲート型電
界効果トランジスタ21は、半導体基板22の裏面にドレイ
ン電極26を備えていて、表面にソース電極27、27とゲー
ト電極28、28を備えている。ゲート電極28は絶縁層30の
上に形成されている。チャンネルはゲート電極28下のＰ
層25の表面部CHに形成される。An insulated gate field effect transistor is one of field effect semiconductor devices. Since the insulated gate field-effect transistor was developed to have a vertical structure, it has been opened up for so-called power use such as power control. Figure 2 shows
This figure shows a cross-sectional structure of a vertical structure insulated gate field effect transistor. The insulated gate field effect transistor 21 having a vertical structure has a drain electrode 26 on the back surface of the semiconductor substrate 22, and has source electrodes 27, 27 and gate electrodes 28, 28 on the front surface. The gate electrode 28 is formed on the insulating layer 30. The channel is P under the gate electrode 28
It is formed on the surface portion CH of the layer 25.
ただ、絶縁ゲート型電界効果トランジスタ21は、他の電
力制御素子と比べると、導通状態の素子における順方向
電圧降が大きい（つまりオン抵抗が大きい）傾向にあ
る。絶縁ゲート型電界効果トランジスタ21が導通状態に
あるとき、電流は、ドレイン電極27から入りＮ層23内を
２点矢印で示すように縦向きに流れ、表面付近で横向き
に流れを変えチャンネルを通ってドレイン電極26に達す
る。この場合、基板表面付近におけるＮ層（ドレイン領
域）23で電流の集中化が起こる。つまり、ドレイン領域
が有効に導体として作用しきれないのである。そのた
め、どうしても、オン抵抗が大きくなるのである。オン
抵抗が大きいと素子容量が小さくなるため、利用範囲が
制限されるなどの不都合がある。However, the insulated gate field effect transistor 21 tends to have a large forward voltage drop (that is, a large on-resistance) in a conductive element as compared with other power control elements. When the insulated gate field effect transistor 21 is in a conductive state, a current enters from the drain electrode 27 and flows vertically in the N layer 23 as shown by a double-pointed arrow, and changes in a horizontal direction near the surface to pass through the channel. Reach the drain electrode 26. In this case, current concentration occurs in the N layer (drain region) 23 near the substrate surface. That is, the drain region cannot effectively function as a conductor. Therefore, the on-resistance inevitably increases. If the on-resistance is large, the element capacitance becomes small, so there is a disadvantage that the range of use is limited.
上記の事情に鑑み、この発明は、ドレイン領域が有効に
作用しオン抵抗が小さく、大電流制御に適した電界効果
半導体装置を提供することを目的とする。In view of the above circumstances, it is an object of the present invention to provide a field effect semiconductor device that has a drain region that effectively acts and has a small on-resistance and is suitable for large current control.
前記目的を達成するため、この発明は、半導体基板の一
側にドレイン電極を備えているとともに他側にソース電
極と絶縁ゲート電極を備えていて、前記基板の他側表面
に形成された逆導電型領域表面にチャンネルが形成され
るようになっている電界効果半導体装置において、前記
逆導電型領域の外側における前記他側表面に別のソース
電極を備えていることを特徴とする電界効果半導体装置
を要旨とする。In order to achieve the above-mentioned object, the present invention comprises a drain electrode on one side of a semiconductor substrate, a source electrode and an insulated gate electrode on the other side, and a reverse conductive layer formed on the surface of the other side of the substrate. A field effect semiconductor device in which a channel is formed on the surface of a mold region, wherein another source electrode is provided on the other surface outside the opposite conductivity type region. Is the gist.
以下、この発明にかかる電界効果半導体装置を、その一
例である縦型の電界効果トランジスタ（以下、「FET」
という）をあらわした図面を参照しながら詳しく説明す
る。Hereinafter, a field-effect semiconductor device according to the present invention will be referred to as a vertical field-effect transistor (hereinafter referred to as "FET") as an example.
Will be described in detail with reference to the drawings.
第１図は、この発明にかかる電界効果半導体装置の一実
施例であるFETの断面構造をあらわしたものである。FIG. 1 shows a sectional structure of an FET which is an embodiment of a field effect semiconductor device according to the present invention.
FET1のドレイン領域となるN+層3aとN-層3bを有する半導
体基板２を備えている。半導体基板２表面に互いに離れ
てＰ層（逆導電型領域）５…５が形成されていて、各Ｐ
層５の表面に互いに離れるようにしてN+層４、４が形成
されている。Ｐ層５の外側におけるN-層3bの表面にN+層
3cが形成されている。N+層3aの上（半導体基板の他側表
面）にはドレイン電極６が形成されている。Ｐ層５表面
とN+層４、４表面の両方に渡るようにしてソース電極７
…７が形成されている。ゲート電極８…８は絶縁層10の
上に形成されている。N+層3cには別のソース電極９、９
が形成されている。The semiconductor substrate 2 having the N + layer 3a and the N − layer 3b which will be the drain region of the FET 1 is provided. P layers (reverse conductivity type regions) 5 ... 5 are formed apart from each other on the surface of the semiconductor substrate 2, and each P layer
N + layers 4 and 4 are formed on the surface of the layer 5 so as to be separated from each other. An N + layer is formed on the surface of the N − layer 3b outside the P layer 5.
3c is formed. A drain electrode 6 is formed on the N + layer 3a (the other surface of the semiconductor substrate). The source electrode 7 is formed so as to extend over both the P layer 5 surface and the N + layers 4, 4 surface
... 7 is formed. The gate electrodes 8 ... 8 are formed on the insulating layer 10. Separate source electrodes 9 and 9 are provided on the N + layer 3c.
Are formed.
FET1は、MOS（絶縁ゲート型）FETとＪ（接合型）FETの
ふたつの型の縦型トランジスタを有している。MOSFET
は、N+層（ソース領域）４、Ｐ層（ベース領域）５、ド
レイン領域となるN-層3a,N+層3b、電極６、７、８で構
成されていて、チャンネルはＰ層５の表面部CHに形成さ
れる。JFETは、N+層（ソース領域）3c、Ｐ層（ゲート領
域）５、ドレイン領域となるN-層3a,N+層3b、電極６、
９で構成されていて、チャンネルはドレイン領域に形成
される。つまり、従来と違って、FET1には、JFETも形成
されているのである。The FET 1 has two types of vertical transistors, a MOS (insulated gate type) FET and a J (junction type) FET. MOSFET
Is composed of an N + layer (source region) 4, a P layer (base region) 5, N − layers 3a and N + layers 3b to be drain regions, electrodes 6, 7 and 8, and the channel is the P layer 5 Is formed on the surface portion CH of. The JFET includes an N + layer (source region) 3c, a P layer (gate region) 5, N − layers 3a and N + layers 3b to be drain regions, an electrode 6,
The channel is formed in the drain region. In other words, unlike the conventional method, JFET is also formed in FET1.
FET1は、ゼロバイアス状態において空乏層が２点鎖線Ａ
より上のN-層3b内に横方向に連続して生ずるように、各
領域（特にN-層など）における不純物濃度およびディメ
ンジョン（特にＰ層５、５間の距離など）が選定されて
いる。そのため、FET1はエンハンストメント型の動作を
する。FET1 has a two-dot chain line A with a depletion layer in the zero bias state.
The impurity concentration and dimension (especially the distance between the P layers 5 and 5) in each region (especially the N − layer) are selected so as to be continuously generated in the lateral direction in the upper N − layer 3b. . Therefore, the FET1 operates in an enhancement type.
ゲート電圧（ゲート電極８に印加される電圧）がMOSFET
のしきい値電圧より低いときは、MOSFETは導通しない。
さらに空乏層の作用により、JFETも遮断状態にある。し
たがって、ドレイン電圧が一定の値以下のときには、FE
T1には全く電流が流れないことになる。ゲート電圧がし
きい値電圧を越えると、MOSFETが導通するようになる。
このとき、電極６、８間の電圧を支えて、JFETを遮断状
態に保たせていた空乏層が、実効的に電圧を支えきれな
くなる。そのため、JFETも導通することとなる。したが
っても、FET1が導通状態にあるときには、従来のドレイ
ン電極６とソース電極７の間に形成される電流通路の他
に、ドレイン電極６と別のソース電極９の間にあらたな
電流通路が形成されることとなる。つまり、N-層3bは表
面付近の個所も十分電流通路として使われることとなる
ので、FET1はオン抵抗が上昇を抑制され、かつ電流容量
が増加することとなるのである。もちろん、従来と同じ
電流容量であれば、オン抵抗が低くなることになる。The gate voltage (voltage applied to the gate electrode 8) is MOSFET
Below the threshold voltage of, the MOSFET does not conduct.
Furthermore, due to the action of the depletion layer, the JFET is also in the cutoff state. Therefore, when the drain voltage is below a certain value, FE
No current will flow through T1. When the gate voltage exceeds the threshold voltage, the MOSFET becomes conductive.
At this time, the depletion layer supporting the voltage between the electrodes 6 and 8 and keeping the JFET in the cutoff state cannot effectively support the voltage. Therefore, the JFET also becomes conductive. Therefore, when the FET 1 is conductive, a new current path is formed between the drain electrode 6 and another source electrode 9 in addition to the conventional current path formed between the drain electrode 6 and the source electrode 7. Will be done. In other words, the N − layer 3b is also used as a sufficient current path in the vicinity of the surface, so that in the FET 1, the on resistance is suppressed from increasing and the current capacity is increased. Of course, if the current capacity is the same as the conventional one, the on-resistance will be low.
この発明は、上記実施例に限定されない。例えば、各半
導体層の導電型が全く逆である構成であってもよい。Ｐ
層５の数も３個であったが、これに限られない。The present invention is not limited to the above embodiment. For example, the conductivity type of each semiconductor layer may be completely opposite. P
The number of layers 5 was also three, but is not limited to this.
以上に述べたように、この発明にかかる電界効果半導体
装置は、半導体基板の一側にドレイン電極を備えている
とともに他側にソース電極と絶縁ゲート電極を備えてい
て、前記基板の他側表面に形成された逆導電型領域表面
にチャンネルが形成されるようになっている構成におい
て、前記逆導電型領域の外側における前記他側表面に別
のソース電極を備えている。そのため、電界効果半導体
装置は、ドレイン領域が有効に作用しオン抵抗が小さ
く、大電流制御に適したものとなる。As described above, the field-effect semiconductor device according to the present invention has the drain electrode on one side of the semiconductor substrate and the source electrode and the insulated gate electrode on the other side, and the surface of the other side of the substrate is In the structure in which the channel is formed on the surface of the opposite conductivity type region formed in, the other source electrode is provided on the other side surface outside the opposite conductivity type region. Therefore, the field-effect semiconductor device is suitable for large current control because the drain region effectively acts and the on-resistance is small.
第１図は、この発明にかかる電界効果半導体装置の一実
施例であるFETの構造をあらわした断面図、第２図は、
従来のFETの構造をあらわした断面図である。 １……FET（電界効果半導体装置）、２……半導体基
板、５……Ｐ層（逆導電型領域）、６……ドレイン電
極、７……ソース電極、８……ゲート電極、９……別の
ソース電極FIG. 1 is a sectional view showing the structure of a FET which is an embodiment of the field effect semiconductor device according to the present invention, and FIG.
It is sectional drawing showing the structure of the conventional FET. 1 ... FET (field effect semiconductor device), 2 ... semiconductor substrate, 5 ... P layer (reverse conductivity type region), 6 ... drain electrode, 7 ... source electrode, 8 ... gate electrode, 9 ... Another source electrode
Claims (2)
いるとともに他側にソース電極と絶縁ゲート電極を備え
ていて、前記基板の他側表面に形成された逆導電型領域
表面にチャンネルが形成されるようになっている電界効
果半導体装置において、前記逆導電型領域の外側におけ
る前記他側表面に別のソース電極を備えていることを特
徴とする電界効果半導体装置。1. A semiconductor substrate having a drain electrode on one side and a source electrode and an insulated gate electrode on the other side, wherein a channel is formed on the surface of the opposite conductivity type region formed on the surface of the other side of the substrate. A field effect semiconductor device to be formed, wherein another source electrode is provided on the other side surface outside the opposite conductivity type region.
複数個形成されていて、別のソース電極が前記逆導電型
領域の間に位置している特許請求の範囲第１項記載の電
界効果半導体装置。2. The electric field according to claim 1, wherein a plurality of opposite conductivity type regions are formed so as to be separated from each other, and another source electrode is located between the opposite conductivity type regions. Effect semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61199745A JPH0673381B2 (en) | 1986-08-26 | 1986-08-26 | Field effect semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61199745A JPH0673381B2 (en) | 1986-08-26 | 1986-08-26 | Field effect semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6355976A JPS6355976A (en) | 1988-03-10 |
| JPH0673381B2 true JPH0673381B2 (en) | 1994-09-14 |
Family
ID=16412924
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61199745A Expired - Lifetime JPH0673381B2 (en) | 1986-08-26 | 1986-08-26 | Field effect semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0673381B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07142731A (en) * | 1993-05-26 | 1995-06-02 | Texas Instr Inc <Ti> | Power device and method for forming the same |
| US5396085A (en) * | 1993-12-28 | 1995-03-07 | North Carolina State University | Silicon carbide switching device with rectifying-gate |
| US5488236A (en) * | 1994-05-26 | 1996-01-30 | North Carolina State University | Latch-up resistant bipolar transistor with trench IGFET and buried collector |
-
1986
- 1986-08-26 JP JP61199745A patent/JPH0673381B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6355976A (en) | 1988-03-10 |
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