JPH067550B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH067550B2 JPH067550B2 JP59156893A JP15689384A JPH067550B2 JP H067550 B2 JPH067550 B2 JP H067550B2 JP 59156893 A JP59156893 A JP 59156893A JP 15689384 A JP15689384 A JP 15689384A JP H067550 B2 JPH067550 B2 JP H067550B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- aluminum wiring
- protective film
- semiconductor device
- polysilicon film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
- Local Oxidation Of Silicon (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は、アルミニウム配線処理が完了した半導体チッ
プの表面を保護するために形成される保護膜の部分につ
いて改良を施した半導体装置に関する。Description: TECHNICAL FIELD The present invention relates to a semiconductor device having an improved protective film portion formed to protect the surface of a semiconductor chip on which an aluminum wiring process has been completed.
（従来技術） 従来から、半導体チップの表面は、そこに形成されたト
ランジスタや抵抗等の素子を、物理的・化学的・機械的
に外部から保護するために、酸化シリコン（ＳｉＯ２）
膜や窒化シリコン（Ｓｉ３Ｎ４）膜等で成る保護膜で覆
われている。(Prior Art) Conventionally, the surface of a semiconductor chip is formed of silicon oxide (SiO 2 ) in order to physically, chemically, and mechanically protect elements formed therein, such as transistors and resistors, from the outside.
It is covered with a protective film such as a film or a silicon nitride (Si 3 N 4 ) film.
ところが、この保護膜は、アルミニウム配線の完了後に
低温で形成されるために、そのアルミニウム配線の下地
の酸化膜（ＳｉＯ２）と反応せず、Van der Waalsの力
のみによって弱く結合しているので、接着強度が弱く、
水分等の侵入に対してこれを十分阻止することができ
ず、また半導体チップを樹脂封止する場合には、その樹
脂の収縮によって保護膜を剥離する力が働くため、はが
れ易いという問題があった。However, since this protective film is formed at a low temperature after completion of the aluminum wiring, it does not react with the underlying oxide film (SiO 2 ) of the aluminum wiring and is weakly bonded only by the Van der Waals force. , The adhesive strength is weak,
There is a problem that it is not possible to sufficiently prevent the invasion of moisture and the like, and when the semiconductor chip is sealed with a resin, the shrinkage of the resin acts to peel off the protective film, so that it easily peels off. It was
（発明の目的） 本発明は斯かる点に鑑みて成されたもので、その目的
は、保護膜部分を強力に接着させて水分等の浸透を防止
し、また剥離等も生じないようにした半導体装置を提供
することである。(Object of the Invention) The present invention has been made in view of the above problems, and an object thereof is to strongly adhere the protective film portion to prevent the permeation of water and the like and prevent peeling or the like. It is to provide a semiconductor device.
（発明の構成） このために本発明の半導体装置では、半導体基板の上面
に直接或いは酸化膜を介在してアルミニウム配線を形成
し、該アルミニウム配線を含む上面に保護膜を形成した
半導体装置において、上記アルミニウム配線を含む上面
と上記保護膜との間にポリシリコン膜を介在させ、上記
ポリシリコン膜と上記アルミニウム配線との間に両者の
焼結反応層を設け、上記ポリシリコン膜と上記保護膜と
の間に両者の組成が連続して変化する層を設けて構成し
た。Therefore, in the semiconductor device of the present invention, aluminum wiring is formed directly on the upper surface of the semiconductor substrate or with an oxide film interposed, and a protective film is formed on the upper surface including the aluminum wiring. A polysilicon film is interposed between the upper surface including the aluminum wiring and the protective film, and a sintering reaction layer of both is provided between the polysilicon film and the aluminum wiring, and the polysilicon film and the protective film. And a layer in which the composition of both of them continuously changes.
（実施例） 以下、本発明の実施例について説明する。第１図はその
一実施例の半導体装置の断面を示すものである。この例
は、ｐ型基板の上にｎ型エピタキシャル成長層を形成し
て、その成長層内に拡散或いはイオン打込等によってｎ
ｐｎトランジスタと抵抗が分離して形成された半導体基
板１についてのものである。(Example) Hereinafter, the Example of this invention is described. FIG. 1 shows a cross section of a semiconductor device of the embodiment. In this example, an n-type epitaxial growth layer is formed on a p-type substrate, and n or n is formed in the growth layer by diffusion or ion implantation.
This is for the semiconductor substrate 1 in which the pn transistor and the resistor are formed separately.
２はこの半導体基板１の上面に形成された酸化膜（Ｓｉ
Ｏ２）、３１〜３６はアルミニウム配線である。このア
ルミニウム配線の内、３２はトランジスタのベース電
極、３３はエミッタ電極、３４はコレクタ電極、３５、
３６は抵抗の引出し電極である。３１は半導体基板１の
上面周囲を囲むように形成された枠状電極である。この
電極３１は第１図に示すように必ずしも半導体基板１の
アイソレーションの上に形成する必要はない。この電極
３１の概要を第２図に示す。2 is an oxide film (Si formed on the upper surface of the semiconductor substrate 1
O 2 ), 31 to 36 are aluminum wirings. Of the aluminum wiring, 32 is a base electrode of the transistor, 33 is an emitter electrode, 34 is a collector electrode, 35,
Reference numeral 36 is a resistance extraction electrode. Reference numeral 31 is a frame-shaped electrode formed so as to surround the upper surface of the semiconductor substrate 1. The electrode 31 does not necessarily have to be formed on the isolation of the semiconductor substrate 1 as shown in FIG. The outline of the electrode 31 is shown in FIG.
４はポリシリコン膜であり、高抵抗のものが100〜3000
Åの厚さで形成されて、アルミニウム配線３１〜３６及
び酸化膜２の上面の全面を覆っている。4 is a polysilicon film, and a high resistance film is 100 to 3000
It is formed with a thickness of Å and covers the entire upper surfaces of the aluminum wirings 31 to 36 and the oxide film 2.
そして、そのポリシリコン膜４の上面に、保護膜（Ｓｉ
Ｏ２、Ｓｉ３Ｎ４等）５が全面に亘って形成されてい
る。Then, on the upper surface of the polysilicon film 4, a protective film (Si
O 2 , Si 3 N 4, etc.) 5 are formed over the entire surface.
上記ポリシリコン膜４の形成は、アルミニウム配線が完
了した後に例えば気相法によって形成する。The polysilicon film 4 is formed by, for example, a vapor phase method after the aluminum wiring is completed.
即ち、上記半導体基板１を反応管内にセットし、キャリ
アガスに原料ガスとしてモノシラン（ＳｉＨ４）を供給
して、ＳｉＨ４→Ｓｉ＋２Ｈ２の反応により、酸化膜２
及びアルミニウム配線上にポリシリコン膜４を形成す
る。また続けて、ＳｉＨ４とＯ２或いはＮＨ３とを反応
させることにより、連続して、即ち組成が連続して界面
がない状態で保護膜５としてのＳｉＯ３膜やＳｉ３Ｎ４
膜を形成する。この結果、ポリシリコン膜４と保護膜５
とは、両者の組成が連続して変化する層を介在して一体
となる。That is, the semiconductor substrate 1 is set in the reaction tube, monosilane (SiH 4 ) is supplied as a source gas to the carrier gas, and the reaction of SiH 4 → Si + 2H 2 causes the oxide film 2
A polysilicon film 4 is formed on the aluminum wiring. In addition, subsequently, by reacting SiH 4 with O 2 or NH 3 , the SiO 3 film or Si 3 N 4 serving as the protective film 5 continuously, that is, in a state where the composition is continuous and there is no interface.
Form a film. As a result, the polysilicon film 4 and the protective film 5
And is integrated with a layer in which the composition of both changes continuously.
そして、上記のようにして形成された半導体装置をアル
ミニウム配線が溶融しない温度、例えば560 ℃或いはそ
れ以下の温度（ほぼ50℃程度までの温度）で熱処理する
と、ポリシリコン膜４がアルミニウム配線と焼結反応を
起して、その界面が反応接着するようになる。Then, when the semiconductor device formed as described above is heat-treated at a temperature at which the aluminum wiring does not melt, for example, at a temperature of 560 ° C. or lower (a temperature up to about 50 ° C.), the polysilicon film 4 is burned with the aluminum wiring. A binding reaction occurs and the interface reacts and adheres.
この結果、保護膜５と一体化したポリシリコン膜４がア
ルミニウム配線と強力に接着し、半導体装置の周囲の応
力の強くかかる部分からの保護膜５のはがれを防ぐこと
ができる。As a result, the polysilicon film 4 integrated with the protective film 5 is strongly adhered to the aluminum wiring, and the protective film 5 can be prevented from peeling off from the portion around the semiconductor device to which a strong stress is applied.
なお、上記熱処理は、ポリシリコン層４や保護膜５の形
成中に行うこともでき、また、上記保護膜５としては、
酸化物、窒化物の以外にシリコンカーバイド等の炭化物
を使用することもできる。The heat treatment may be performed during the formation of the polysilicon layer 4 and the protective film 5, and as the protective film 5,
In addition to oxides and nitrides, carbides such as silicon carbide can also be used.
（発明の効果） 以上から本発明によれば、表面の保護膜部分が強固に接
着されるので、水分の侵入の阻止を確実に行うことがで
きることはもとより、樹脂封止の際のその樹脂の収縮に
よる剥離も効果的に防止することができるという特徴が
ある。(Effects of the Invention) As described above, according to the present invention, since the protective film portion on the surface is firmly adhered, it is possible to surely prevent the intrusion of water, and it is also possible to prevent It is characterized in that peeling due to shrinkage can be effectively prevented.
第１図は本発明の一実施例の半導体装置の断面図、第２
図は枠状電極の説明図である。 １…半導体基板、２…酸化膜、３１〜３６…アルミニウ
ム配線、４…ポリシリコン膜、５…保護膜。FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.
The figure is an illustration of a frame-shaped electrode. 1 ... Semiconductor substrate, 2 ... Oxide film, 31-36 ... Aluminum wiring, 4 ... Polysilicon film, 5 ... Protective film.
Claims (1)
在してアルミニウム配線を形成し、該アルミニウム配線
を含む上面に保護膜を形成した半導体装置において、 上記アルミニウム配線を含む上面と上記保護膜との間に
ポリシリコン膜を介在させ、 上記ポリシリコン膜と上記アルミニウム配線との間に両
者の焼結反応層を設け、 上記ポリシリコン膜と上記保護膜との間に両者の組成が
連続して変化する層を設けた、 ことを特徴とする半導体装置。1. A semiconductor device in which aluminum wiring is formed directly on the upper surface of a semiconductor substrate or with an oxide film interposed, and a protective film is formed on the upper surface including the aluminum wiring, wherein the upper surface including the aluminum wiring and the protective film. A polysilicon film is interposed between the polysilicon film and the aluminum wiring, and a sintering reaction layer of both is provided between the polysilicon film and the aluminum wiring, and the composition of both is continuous between the polysilicon film and the protective film. A semiconductor device having a layer that changes according to the above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59156893A JPH067550B2 (en) | 1984-07-27 | 1984-07-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59156893A JPH067550B2 (en) | 1984-07-27 | 1984-07-27 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6135523A JPS6135523A (en) | 1986-02-20 |
| JPH067550B2 true JPH067550B2 (en) | 1994-01-26 |
Family
ID=15637696
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59156893A Expired - Lifetime JPH067550B2 (en) | 1984-07-27 | 1984-07-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH067550B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6387833U (en) * | 1986-11-27 | 1988-06-08 | ||
| JPH0245932A (en) * | 1988-08-06 | 1990-02-15 | Fujitsu Ltd | Passivation structure in semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3021175A1 (en) * | 1980-06-04 | 1981-12-10 | Siemens AG, 1000 Berlin und 8000 München | METHOD FOR PASSIVATING SILICON COMPONENTS |
| JPS5788734A (en) * | 1980-11-21 | 1982-06-02 | Toshiba Corp | Semiconductor device |
-
1984
- 1984-07-27 JP JP59156893A patent/JPH067550B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6135523A (en) | 1986-02-20 |
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