JPH067555B2 - Multi-cell type transistor - Google Patents

Description

TECHNICAL FIELD The present invention relates to a structure of a multi-cell type transistor.

[Conventional technology]

Fine unit transistor area (cell) to increase the transistor current, high-speed switching, and high frequency
A transistor having a large number of so-called multi-cell transistors has already been commercialized. 9 to 11
The figure shows a multi-emitter silicon transistor, which is one type of multi-cell type transistor. This FIG. 9 to 1
In FIG. 1, 1 is an n ⁺ type collector low resistance region, 2 is an n type collector high resistance region, 3 is a p type base region, 4 is an n ⁺ type unit emitter region, 5 is an insulating film made of a SiO ₂ film, 6 Is a base connection opening formed in the insulating film 5, 7 is an emitter connection opening formed in the insulating film 5, 8 is an Al base electrode showing a connection portion to the base region 3 and a wiring portion, and 9 is The Al emitter electrode 10 showing the connecting portion to the emitter region 4 and the wiring portion is
It is a collector electrode composed of two layers of Ti and Ni.

The collector low resistance region 1, the collector high resistance region 2, and the base region 3 are sequentially arranged in a three-layer structure adjacent to each other, and a large number of emitter regions 4 are arranged in the base region 3 in an island shape. Therefore, this transistor is an aggregate of a large number of unit transistor regions (cells) corresponding to a large number of emitter regions 4. In this conventional multi-emitter transistor, the unit emitter region 4 is formed in an annular shape, the base region 3 is arranged on the outer periphery thereof, and the base region 3 is also arranged in the central portion. The surfaces of the base region 3 and the emitter region 4 are provided with connection openings 6 and 7, respectively.
It is covered with the insulating film 5 except for. The base connection opening 6 is arranged in the vicinity of the four corners of the unit emission region 4 having a substantially square outer periphery, that is, in the approximate center of the four unit emission regions 4 adjacent to each other.

Base electrodes 8 shown by hatching are provided in a stripe shape so as to pass over the base regions 3 between the emitter regions 4, and are connected to the base regions 3 through the connection openings 6. The emitter electrode 9 shown by hatching is arranged in parallel to the base electrode 8 and passes over each emitter region 4. Two emitter openings 7 are provided for each unit emitter area 4 along the direction in which the emitter electrode 9 extends, and the unit emitter area 4 is connected to the emitter electrode 9 through these two openings 7. In this example, a region surrounded by four straight lines connecting the centers of the four base connecting holes 6 close to the four corners of the unit emitter region 4 is a unit transistor region.

[Problems to be Solved by the Invention]

In the conventional transistors shown in FIGS. 9 to 11, the unit transistor region in the vicinity of the emitter bonding pad portion (not shown) is likely to cause reverse bias secondary breakdown. This phenomenon occurs due to the wiring resistance of the emitter electrode 9 and the base electrode 8. That is, in the unit transistor region near the emitter bonding pad portion, since the wiring resistance of the emitter electrode 9 is small, the forward bias voltage between the emitter and the base in the ON state is effectively large and the emitter current density is high. Moreover, in the unit transistor area near the emitter bonding pad, the wiring resistance of the base electrode 8 is large, so that it is difficult to draw the base reverse bias current when the reverse bias voltage is applied between the emitter and the base to turn it off. Emitter current concentrates after a delay. Due to these synergistic effects, in the multi-cell type transistor, the unit transistor region in the vicinity of the emitter bonding pad portion is often burned to cause secondary breakdown.

As a measure against this, a structure in which an emitter stabilizing resistance is provided in series to the emitter region 4 of each unit transistor region is widely adopted. The emitter stabilization resistor generally has a structure in which a polycrystalline silicon layer is provided on the insulating film 5 above the emitter region 4. The problem that the unit transistor region in the vicinity of the emitter bonding pad portion is likely to be burned is remarkably improved by selecting the emitter stabilizing resistance to a value at which the wiring resistance of the emitter electrode 9 can be ignored. However, the provision of the emitter stabilizing resistor increases the number of manufacturing steps and complicates the structure, resulting in cost increase.

In order to prevent the destruction in the vicinity of the emitter bonding pad portion, it is possible to reduce the size of the opening provided in the insulating film for connecting the emitter electrode to the emitter region near the emitter bonding pad portion.
It is known from Japanese Patent No. 4751. However, a multi-cell type transistor that can effectively use the area of a semiconductor substrate (chip) to achieve miniaturization and prevent destruction has not been proposed yet.

Therefore, it is an object of the present invention to provide a multi-cell transistor that can achieve miniaturization and is resistant to breakage.

[Means for Solving the Problems] The present invention for achieving the above object will be described with reference to the reference numerals of the drawings showing an embodiment. A large number of unit transistor regions including a collector region, a base region and an emitter region will be described. The semiconductor substrate 20 is provided individually, the insulating film 5 is provided on the surface 12 of the semiconductor substrate 20 having a quadrangular planar shape, and the plurality of units are provided through the openings 7 provided in the insulating film 5. The emitter electrodes 9 connected to the emitter regions of the transistors, the base electrodes 8 connected to the base regions of the plurality of unit transistors through the openings 6 formed in the insulating film 5, and the semiconductor substrate. In the multi-cell type transistor including the collector electrode 10 provided on the back surface of the semiconductor substrate 20, the plurality of unit transistors are rectangular surfaces of the semiconductor substrate 20. A plurality of unit transistors are arranged in the same number on a plurality of virtual straight lines that extend in parallel to the opposing first and second sides 21 and 22 of the surface 12, and a plurality of unit transistors are arranged on the plurality of virtual straight lines. Each of the emitter electrodes 9 is disposed at a third side 23 perpendicular to the first and second sides 21 and 22.
Wide emitter bonding pad portion 9 extending along
a, an emitter common connecting portion 9d extending along the third side 23, connected to the emitter bonding pad portion 9a, and having a width narrower than the emitter bonding pad portion 9a, and the emitter bonding pad A plurality of first emitter wiring portions 9c1 connected to the portion 9a and provided along the virtual straight line, and a plurality of second emitter wiring portions 9c1 connected to the emitter common connection portion 9d and provided along the virtual straight line. And the emitter regions of the plurality of unit transistors, the emitter regions of the plurality of unit transistors being formed through the openings 7.
c1 and 9c2, and the base electrode 8 is connected to the third
A base bonding pad portion 8a extending along a fourth side 24 facing the side 23 and facing the common emitter connecting portion 9d; and a fourth side 24 connected to the base bonding pad portion 8a. A base common connection portion 8d extending along the first emitter wiring pad portion 9a and a plurality of base common connection portions 8d connected to the base common connection portion 8d and extending in parallel to the first emitter wiring portion 9c1. 1 base wiring portion 8c1 and the base bonding pad portion 8a
Of the second base wiring portion 8c2 extending in parallel with the emitter wiring portion 9c2 of the second base, and the area of the emitter connection opening 7 in the first and second emitter wiring portions 9c1 and 9c2 is equal to the area of the emitter bonding portion. Pad part 9a
The plurality of emitter connections provided in the insulating film 5 below the one closest to the first side 21 in the plurality of first emitter wiring portions 9c1. The area of the application hole 7 changes in at least two steps, and the plurality of the plurality of the second emitter wiring portions 9c2 provided on the insulating film 5 under the one closest to the second side 22 are provided. The area of the emitter connecting opening 7 is changed in at least three steps and the first emitter wiring portion 9c closest to the first side 21 is formed.
The present invention relates to a multi-cell type transistor characterized in that it has a difference with the area of the emitter connection opening under 1.

[Operation and Effect] The present invention has the following operation and effect.

(A) Since the wide emitter bonding pad portion 9a is arranged to face the narrow base common connecting portion 8d, and the wide base bonding pad portion 8a is arranged to face the narrow emitter common connecting portion 9d, a plurality of virtual straight lines are formed. It is possible to arrange the same number of unit transistors, and a large number of unit transistors can be arranged regularly. That is, it is possible to arrange the unit transistors in a state where there is little waste and to reduce the size.

(B) By making a difference in the state of the opening 7 between the first emitter wiring portion 9c1 closest to the first side 21 and the second emitter wiring portion 9c2 closest to the second side 22,
It is possible to compensate for the resistance of the narrow emitter common connection portion 9d, ensure the uniformity of operation of a large number of unit transistors, and provide a multi-cell type transistor that is not easily destroyed.

First Embodiment Next, a multi-emitter transistor according to the first embodiment of the present invention shown in FIGS. 1 to 4 will be described. However,
In FIGS. 1 to 4, reference numerals 1 to 10 indicate
Since they are substantially the same as those denoted by the same reference numerals in FIGS. 9 to 11, the description thereof will be omitted. In this embodiment, the base region 3 is not exposed in the central portion of the emitter region 4 having a substantially square planar shape. Therefore, the emitter region 4 is non-annular. Below the center of the emitter region 4, that is, between the center of the emitter region 4 and the base region 3, a p ⁺ type low resistance region 11 having a higher impurity concentration than the base region 3 is provided.
Can be referred to as quasi-base region or low resistance base region
The p ⁺ type low resistance region 11 improves the high-speed switching characteristics, increases the reverse bias secondary breakdown resistance, increases the design freedom of the emitter connection opening 7, and further improves the characteristics in the high current region. Let

The p ⁺ type low resistance region 11 is provided by forming the base region 3 by impurity diffusion from the surface 12 of the silicon substrate on the insulating film 5 side and then performing impurity diffusion from the surface 12 to a higher concentration than the base diffusion. And does not reach the n-type high resistance collector region 2. The emitter region 4 is formed by diffusing an impurity concentration higher than that of the p ⁺ type low resistance region 11. After the diffusion step for forming the p ⁺ -type low-resistance region 11, when the diffusion to form the emitter region 4, emitter regions 4, strictly, p ⁺ -type low-resistance region 11
It is formed to be slightly shallower than the surrounding area in the area adjacent to, but is shown at the same depth.

The opening 7 for connecting the emitter is formed in the unit transistor area, that is, the unit emitter area 4, as is apparent from FIGS.
Of the p ⁺ -type low resistance region 11 and is arranged concentrically with the p ⁺ -type low resistance region 11. The planar size of the emitter connecting opening 7 is smaller than that of the p ⁺ type low resistance region 11.

FIG. 1 shows the entire chip. In the figure, 24 unit emission regions 4 are shown in order to avoid complication, but in reality, 100 or more unit emission regions 4 are often formed. The base electrodes 8 and the emitter electrodes 9 are alternately juxtaposed to each other, and the base bonding pad portions 8a are respectively arranged.
And the emission padding pad portion 9a.
The emitter electrode 9 has an emitter bonding pad portion 9a.
And the emission region connecting portion 9b, which is a portion formed approximately in the emission connecting hole 7, and the emission region connecting portion 9b are commonly connected to each other and the emission bonding pad portion 9a.
And the wiring portion 9c leading to the. The patterns of the base electrode 8 and the emitter electrode 9 shown in FIG. 1 will be described in more detail. Along the virtual straight lines L1 to L6 parallel to the first and second sides 21 and 22 of the semiconductor substrate 20 having a quadrangular surface. Unit transistors are arranged. The base electrode 8 includes a wide base bonding pad portion 8a extending along the fourth side 24 and a narrow base common connecting portion 8d.
The first and second base wiring portions 8c1 and 8c2 extend parallel to the first and second sides 21 and 22. The emitter electrode 9 includes a wide emitter bonding pad portion 9a extending along the third side 23 and a narrow emitter common connecting portion 9d, and first and second extending in parallel with the first and second sides.
Of emitter wiring portions 9c1 and 9c2. The emitter bonding pad portion 9a faces the common base connecting portion 8d, and the pad connecting portion 8a faces the common emitter connecting portion 9d. The size of the opening 7 for connecting the emitter is not the same in all the unit emitter regions 4, and in the individual wiring of the emitter electrode 9, the emitter bonding pad 9
It is designed to have a tendency to increase with distance from a. Here, the area of the opening 7 for connecting the emitter is set to three stages of large, medium and small, and the area of the four emitter electrodes 9 on the left side of FIG. 4 is changed to two stages of small and medium along each wiring, The area of the two emitter electrodes 9 on the right side is changed in three steps of large, medium and small along each wiring. In addition, in a part of many emitter electrodes 9, the area of the emitter connection opening 7 may be constant along the wiring without changing.

When the areas of the emitter connecting holes 7 are formed nonuniformly in this way, it is possible to compensate for nonuniform operation of the unit emitter regions 4 due to the wiring resistance of the emitter electrode 9 and the base electrode 8. That is, the conventional defect that the unit emission region 4 near the emission bonding pad portion 9a is easily destroyed is greatly reduced, and the reverse bias secondary breakdown withstand capability is improved. Further, since it is only necessary to change the mask pattern in the photolithography process, there is no need to increase the manufacturing process or complicate the structure. Since it is not a method of adding a relatively large emitter stabilization resistor with polycrystalline silicon or the like, power loss is not generated in the emitter stabilization resistor, which is also advantageous in terms of power loss. The structure of the present invention is also effective as a measure for improving the forward bias secondary breakdown resistance. In order to adjust the area of the opening 7 for the emitter connection, the surface area of the emitter area 4 is increased without exposing the base area 3 in the center of the emitter area 4, and the opening 7 for the emitter connection is arranged in the center. , Easily achieved.

[Second Embodiment] Next, a base island type transistor (mesh-emitter type transistor) which is another type of the multi-cell type transistor according to the second embodiment of the present invention shown in FIGS. 5 to 8 will be described. To do. However, since the parts indicated by reference numerals 1 to 12 are substantially the same as those shown by the same reference numerals in FIGS. 9 to 11 and FIGS. 1 to 4, the description thereof will be omitted. The base island type transistor has the base region 3 on the surface 12 as is apparent from FIGS.
A plurality of islands are exposed in the area, and an emission region 4 runs between them in a mesh shape. Unit transistor area is 1
It is a region surrounded by four base connecting holes 6 adjacent to one emitter connecting hole 7. Therefore, the central part of the unit transistor region is the central part of the intersection of the emitter regions 4 running vertically and horizontally on the surface 12. p ⁺ type low resistance region 1
1 and the emitter connection opening 7 are arranged in the central portion of the unit transistor, that is, the unit emitter region 4 for the same reason as in the first embodiment. In this example, as is clear from FIG. 8, the area of the opening 7 for connecting the emitter is continuously changed along each wiring of the emitter electrode 9. Also in this example, the secondary breakage resistance is improved by forming the opener 7 for connecting the emitter so that the area is not uniform. Substantially no increase in manufacturing process, structural complexity, or increase in power loss occurs.

The present invention is not limited to the above-mentioned two embodiments, and various modifications and applications are possible within the scope of the gist of the present invention.

[Brief description of drawings]

FIG. 1 is a plan view showing the whole multi-emitter transistor according to the first embodiment of the present invention, FIG. 2 is a plan view showing a part of the transistor of the first embodiment, and FIG. 3 is FIG. 3 is a sectional view showing a portion taken along the line III-III of FIG. 4, FIG. 4 is a sectional view showing a portion taken along the line IV-IV of FIG. 2, and FIG. 5 is a base island type transistor according to the second embodiment of the present invention. FIG. 6 is a cross-sectional view showing a part taken along line VI-VI in FIG. 5, FIG. 7 is a cross-sectional view showing a part taken along line VII-VII in FIG. 5, and FIG. FIG. 9 is a plan view showing all of the transistors of the second embodiment, FIG. 9 is a plan view showing a part of a conventional multi-emitter transistor, and FIG. 10 is a sectional view showing a portion taken along line XX of FIG. FIG. 11 is a sectional view showing a portion taken along line XI-XI of FIG. 1, 2 ... Collector region, 3 ... Base region, 4 ... Emitter region, 5 ... Insulating film, 7 ... Emitter connecting hole, 8 ... Base electrode, 8a ... Base bonding pad portion, 9 ... Emitter electrode, 9a ... Emitter bonding pad section (external connection section), 9b ... Emitter area connection section, 9c ... Wiring section,
11 ... P ⁺ type base low resistance region.

Claims (1)

[Claims] 1. A semiconductor substrate (20) provided with a plurality of unit transistor regions each including a collector region, a base region, and an emitter region, and a semiconductor substrate (20) having a quadrangular planar surface (12). An insulating film (5) provided, an emission electrode (9) respectively connected to the emitter regions of the plurality of unit transistors via openings (7) provided in the insulating film (5), Base electrodes (8) respectively connected to the base regions of the plurality of unit transistors through holes (6) provided in the insulating film (5), and collector electrodes (8) provided on the back surface of the semiconductor substrate. 10) in the multi-cell type transistor, wherein the plurality of unit transistors are the semiconductor substrate (2
0) of the quadrangular surface (12) are arranged in the same number on a plurality of virtual straight lines extending in parallel to the opposing first and second sides (21) and (22), respectively. A plurality of unit transistors are respectively arranged on a straight line, and the emitter electrode (9) has the first and second sides (2).
1) A wide emitter bonding pad portion (9a) extending along a third side (23) perpendicular to (22)
And an emitter common connection portion (9d) extending along the third side (23) and connected to the emitter bonding pad portion (9a) and having a width narrower than the emitter bonding pad portion (9a). ), A plurality of first emitter wiring portions (9c1) connected to the emitter bonding pad portion (9a) and provided along the virtual straight line, and the emitter common connection portion (9d), and A plurality of second emitter wiring portions (9c2) provided along a virtual straight line, and the emitter regions of the plurality of unit transistors are provided with the first and second emitters through the openings (7). The base electrode (8) is connected to the wiring parts (9c1) and (9c2), extends along the fourth side (24) facing the third side (23), and has the same emitter. Base bonding pad portion facing the connecting portion (9d) and (8a), the base bonding pad portion (8
a) and a base common connecting portion (8d) extending along the fourth side (24) and facing the emitter bonding pad portion (9a), and a base common connecting portion (8d). A plurality of first base wiring portions (8c1) connected to each other and extending parallel to the first emitter wiring portion (9c1), and the second emitter wiring connected to the base bonding pad portion (8a) Division (9
The second base wiring portion (8c) extending parallel to c2).
2) and the first and second emitter wiring parts (9c1), (9c
The area of the emitter connecting hole (7) in 2) is set so as to increase as the distance from the emitter bonding pad portion (9a) increases, and among the plurality of first emitter wiring portions (9c1). The area of the plurality of emitter connecting holes (7) provided in the insulating film (5) below the one closest to the first side (21) changes in at least two stages, and the plurality of second Of the emitter wiring portion (9c2) closest to the second side (22), the area of the plurality of emitter connection holes (7) provided in the insulating film (5) is at least 3 It has a difference with the area of the emitter connection opening below the first emitter wiring part (9c1) closest to the first side (21) while changing in stages. Multi-cell type Njisuta.