JPH0680449B2 - Active matrix substrate - Google Patents

Description

Detailed Description of the Invention

[Field of Industrial Application] The present invention relates to an active matrix substrate having a thin film transistor array for forming an active matrix display device in combination with liquid crystal or the like. [Prior Art and Its Problems] In an active matrix display device, the occurrence of pixel defects and line defects is a serious defect in quality. In order to prevent these defects, it is necessary to eliminate the disconnection of the gate bus line and the source bus line in the active matrix substrate, the line leakage, or the malfunction of the thin film transistor (hereinafter referred to as TFT). The cause of these defects is dust, foreign matter, or film peeling in the photolithography process or the thin film forming process. The conventional TFT active matrix substrate will be described below. FIG. 24 shows a TFT active matrix substrate in which picture elements (A _mn ) including TFTs are arranged in a matrix. Conventional structure TFT and bus line,
The pixel electrodes are shown in FIGS. 22 and 23. FIG. 23 is a view showing a cross section taken along the line BB 'in FIG. The gate bus lines a and b are formed of tantalum (Ta) on the glass substrate S, and the gate oxide film is a tantalum oxide (Ta ₂ O ₅ ) layer c and silicon nitride (S).
iNx) layer d has a double structure, semiconductor layers e and f are intrinsic amorphous silicon (a-Si (i)), source bus lines g and h are titanium (Ti), drain electrodes i and j. Is a titanium pixel electrode k, l is an IOT film (indium oxide transparent conductive film),
A silicon nitride layer r, m as an etching stopper layer and an n ⁺ type amorphous silicon (a-Si (n ⁺ )) layer p, q are formed between the semiconductor layer and the source / drain electrode. Further, in order to prevent a leak between the source and the gate, an a-Si (i) / a-Si (n ⁺ ) layer x and an etching stopper layer n are formed at the cross portion of the source bus line g and the gate bus line a. Has been done. Here, if the tantalum of the gate bus lines a and b or the titanium of the source bus lines g and h breaks for some reason, a linear defect occurs in the active matrix substrate having the conventional structure. Also TF
If T is damaged for some reason, pixel defects occur in the active matrix substrate having the conventional structure. Therefore, conventionally, a process measure has been taken to prevent these defects, but it is difficult to completely prevent them. In view of the above drawbacks, the present invention provides a structure of an active matrix substrate for preventing a linear defect due to a disconnection of a source bus line in an active matrix substrate and improving the image quality of an active matrix display device. To aim. [Means for Solving the Problems] According to the present invention, a gate bus line and a source bus line, which are orthogonally arranged in a grid pattern on an insulating substrate, a gate bus line and a through hole formed by being stacked on the source bus line are formed. An insulating layer provided, a bypass line formed on the insulating layer and connected to the gate bus line and the source bus line through the through hole, and formed at each intersection of the gate bus line and the source bus line. In the active matrix substrate having a thin film transistor and a pixel electrode made of an ITO film formed in each region surrounded by the gate bus line and the source bus line, the ITO film is provided on the bypass line including the through hole. Is laminated. [Operation] With the structure of the present invention, highly reliable electrical connection between the source bus line and the gate bus line and the bypass line in the active matrix substrate can be obtained. [Embodiment] FIG. 1 shows an amorphous silicon (a-Si) semiconductor TFT active matrix substrate having various kinds of redundancy, which is an embodiment of the present invention. Reference numbers 1 and 5 are a gate bus line and a source bus line, respectively. The TFT 11 is connected to the electrode 13 drawn out from the gate bus line and the electrode 15 drawn out from the source bus line. Reference numeral 14 is a drain electrode, which is a transparent conductive film ITO.
It is connected to the membrane 12. The above substrate structure is the same as the conventional example. The gate bus lines, the source bus lines, and the picture elements will be described below with respect to the portions having various types of redundancy according to the present invention. Gate bus line A bypass line 2 is provided in parallel with the normal gate bus line 1. By providing the bypass in this way, the line width of the bus line is effectively increased. Even if the bus line material is peeled off, the probability that both bus lines 1 and 2 will peel at the same time is lower than the probability of peeling when there is only one bus line. Even if peeling occurs on the TFT, it is
As a whole, it has good operability without defects. Further, as shown in FIG. 21, the gate bus line is made of two layers of conductor thin films, titanium and tantalum, and an insulator thin film is provided between the respective layers of the conductor thin film. Through holes 3 are provided for electrically connecting the respective layers of the conductor thin film. Through hole 3
By connecting the respective conductive films through, it is possible to effectively reduce the resistance of the gate bus line. The cross section 4 with the source bus line is not provided with a bypass section in order to reduce the number of crosses. This is because if the number of cross portions is increased, vertical leakage between the source and the gate is likely to occur and the stray capacitance also increases. Source bus line In addition to the normal source bus line 5, a bypass line 6 is provided at the cross portion with the gate bus line. By providing the bypass line 6, the line width of the source line is effectively increased. Further, as in the case of the gate bus line, the probability of occurrence of peeling of the entire source bus line can be reduced. Also, as shown in detail in FIGS. 16 to 20, the source bus line is also formed of two or more conductor thin films,
Since the insulating thin film is provided between the respective layers of the conductor thin film, the through hole 9 for electrically connecting the respective layers of the conductor thin film is provided. By connecting the conductor thin films through the through holes 9, it is possible to prevent disconnection of the source bus line and at the same time reduce the resistance of the source bus line. Reference numerals 7 and 8 are an a-Si (n ⁺ ) / a-Si (i) layer and an etching stopper SiNx layer, which are semiconductor films for preventing leakage between the source bus line and the gate bus line, respectively. Each of 7 and 8 is formed separately in an island shape at each cross. This is a-Si (n ⁺ ) / a-Si (i) layer, etching stopper Si
The probability of disconnection of the source bus line at the cross portion caused by the peeling of the Nx layer 8 is reduced by the redundancy of the island-shaped separation. Two TFTs for driving each picture element are provided for one picture element like TFT11,11. Here, two TFTs are connected in parallel to the picture element via a TFT connection read gate line 13 extending from the gate bus line in parallel with the source bus line. That is, the TFTs 11 and 11 are connected to the same gate bus line and the same source bus line. Two TFTs
At the same time, the interval is made as large as possible in order to suppress the probability of source or gate disconnection. Also,
As will be described later, the drain electrode 14 has a two-layer structure using titanium and a pixel electrode material ITO (FIGS. 19 and 2).
(See Figure 0). The above reference numerals 1, 5, 13 and the like are used to represent the source bus line, the gate bus line, the lead line from the gate bus line, and the like, but hereinafter, the thin film layers constituting them are also represented. .

[Description of manufacturing process]

Next, a manufacturing process of the TFT active matrix substrate of FIG. 1 will be described with reference to FIGS. In addition, the hatched portion shown in the following figures indicates the portion to be formed or processed in the process at that time. << Process 1 >> As shown in FIG. 2, tantalum having a film thickness of 500 Å to 5000 Å is vapor-deposited on a transparent insulating glass substrate 50, and patterning is performed by a photolithography process like a hatched portion.
In FIG. 2, a gate bypass line 2 is provided in parallel with the normal gate bus line 1. Further, no bypass line is formed at the intersection with the source bus line. This is because, as described above, if the cross section of the source / gate is increased, vertical leakage between the source / gate is likely to occur and the stray capacitance also increases. << Process 2 >> Next, as shown by the shaded area in FIG. 3, except for the source bus line 5 in FIG. 2, that is, the gate bus line is oxidized by anodizing the tantalum surface to a film thickness of 500 Å.
Form ˜5000Å Ta ₂ O ₅ . << Process 3 >> Then, the PCVD method is used to form the gate insulating film SiNx layer, a-Si
(I) After the semiconductor layer and the etching stopper SiNx layer are formed to have film thicknesses of 500Å to 6000Å, 50Å to 4000Å, 300Å to 5000Å respectively, patterning is performed by a photolithography process, and only the etching stopper layer is formed in the shaded area 8 in FIG. (See Fig. 13). << Process 4 >> Then, a-Si with a film thickness of 200Å to 2000Å is formed by PCVD.
After forming the (n ⁺ ) layer, the a-Si (n ⁺ ) / a-Si (i) layer is separated into islands as shown by the shaded areas 7 and 7 in FIG. Is patterned (see FIG. 15). << Process 5 >> Next, as shown in FIG. 6, a through hole 9 is formed in the SiNx layer which is the gate insulating film on the source bus line. Further, the through hole 3 is also formed in the SiNx / Ta ₂ O ₅ layer which is the insulator layer on the gate bus line. Two through holes can be opened. This is to provide redundancy and reduce defects in the through holes in the case where one of the through holes is closed due to a defective photolithography process (see FIGS. 16 and 21). << Process 6 >> Subsequently, titanium to be the bypass line and the drain electrode is sputter-deposited so as to have a film thickness of 500Å to 5000Å, and titanium and a-Si (n ⁺ ) are formed as shown by the hatched pattern in FIG.
To etch. By the way, the above-mentioned through holes 9,3
Through, the tantalum having the pattern formed in << Process 1 >> and the titanium vapor-deposited in this process are electrically connected by the titanium itself entering into the through hole. Therefore, both the gate bus line and the source bus line have a double structure of titanium and tantalum (see FIGS. 17 and 18). << Process 7 >> Next, ITO, which is a pixel electrode material, is sputter-deposited to a film thickness of 300 Å to 3000 Å, and then an eighth photolithography process is performed.
The ITO film is patterned as shown by the shaded area in the figure. Note that I
The TO is patterned not only on the pixel electrode and the drain electrode 14 of the TFT, but also on the source bus line and a part of the gate bus line, and it is possible to suppress the occurrence of titanium disconnection due to << Process 6 >>. .

[Explanation of manufacturing process by cross section]

Next, the manufacturing process of the active matrix substrate according to the present invention will be described with respect to the AA ′ cross section in FIG. FIG. 9 shows the vapor deposition of tantalum having a film thickness of 500Å to 5000Å on the glass substrate 50. Next, the tantalum shown in FIG. 9 is patterned in the cross section as shown in FIG. 10 by the pattern shown in FIG. Then, only the gate bus lines are oxidized as shown by the hatched portions in FIG. 3 to form an oxide film as shown in FIG. Then, the gate oxide film SiN is formed by the PCVD method.
x, the semiconductor layer a-Si (i), and the etching stopper layer have film thicknesses of 500Å to 6000Å, 50Å to 4000Å, 300Å to 50, respectively.
Form to 00Å (Fig. 12). Then, the etching stopper layer in FIG.
It is formed on the island-shaped etching stopper layer 8 shown in FIG. 13 (FIG. 13). Next, a semiconductor layer a-Si (n ⁺ ) having a film thickness of 200Å to 2000Å is formed by the PCVD method (Fig. 14). Then, in the photolithography process, the semiconductor layers a-Si (n ⁺ ) and a-Si (i) formed in FIGS. 12 and 14 are simultaneously formed in the island-shaped pattern 7 of FIG. 5 (see FIG. (Fig. 15).
Next, a through hole 9 is opened in the gate oxide film SiNx (first
(Fig. 16). After that, titanium was sputter-deposited to a film thickness of 500Å to 5000Å (Fig. 17), and then titanium and a-Si (n ⁺ ) were formed on the source bus line pattern by a photolithography process as shown in Fig. 7. (Fig. 18), ITO to be a pixel electrode was sputter-deposited to a film thickness of 300Å to 3000Å (Fig. 19).
After that, patterning is performed as shown by the hatched portion in FIG.
Figure). The above is the manufacturing process for the AA ′ section in FIG. 1. Finally, for reference, the cross-sectional view taken along the line CC ′ of FIG.
It is shown in the figure. [Effect] It is possible to reduce the probability of occurrence of linear defects in an active matrix liquid crystal display device using the active matrix substrate according to the present invention. That is, even if the bypass line that has entered the through hole is removed due to over-etching or the like during etching when forming the pattern of the bypass line, and a disconnection occurs between the bypass line and the bus line, the disconnection portion of the bypass line and the insulation ITO with high adhesiveness that penetrates into the through holes of the film
The film enables electrical connection between the bypass line and the bus line, and even when the bypass line is broken at the step of the through hole when the bypass line is formed, the ITO film also connects the bypass line and the bus line. You can get a connection. Also, since the ITO film is formed at the same time as the pixel electrode manufacturing process, there is no need to form an extra pattern, and the reliability of the electrical connection between the bypass line and the bus line is improved without increasing the manufacturing process or materials. To do.
Therefore, the manufacturing yield of the active matrix liquid crystal display device can be improved.

[Brief description of drawings]

FIG. 1 is a structural diagram of a thin film transistor of an active matrix substrate according to the present invention. 2 to 8 are views showing the thin film transistor array manufacturing process in FIG. 1, respectively. 9 to 20 are sectional views showing the manufacturing process of the thin film transistor array in FIG. 1 taken along the line AA '. FIG. 21 shows C of the thin film transistor array in FIG.
It is a sectional view of the -C 'line direction. FIG. 22 is a diagram showing a thin film transistor having a conventional structure. FIG. 23 shows BB ′ of the thin film transistor in FIG.
It is sectional drawing of a line direction. FIG. 24 is a diagram showing an active matrix substrate in which picture elements (A _mn ) including thin film transistors are arranged in a matrix. 1 ... Gate bus line, 4 ... Cross section of source bus line and gate bus line, 5 ... Source bus line,
6 ... Source bus line bypass line, 50 ... Glass substrate.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasunori Shimada 22-22 Nagaike-cho, Abeno-ku, Osaka-shi, Osaka Within Sharp Corporation (72) Inventor Hiroshi Morimoto 22-22 Nagaike-cho, Abeno-ku, Osaka-shi, Osaka (56) References JP-A-61-249078 (JP, A) Actually developed 61-181 (JP, U)

Claims (1)

[Claims] 1. A gate bus line and a source bus line orthogonally arranged in a grid pattern on an insulating substrate, an insulating layer having a through hole laminated on the gate bus line and the source bus line, and the insulating layer. A bypass line, which is formed in a stacked manner and is electrically connected to the gate bus line and the source bus line through the through hole, a thin film transistor formed at each intersection of the gate bus line and the source bus line, and the gate bus line and the In an active matrix substrate provided with a pixel electrode made of an ITO film and formed in each region surrounded by a source bus line, the IT is provided in the bypass line including on the through hole.
An active matrix substrate having a stack of O films.