JPH0690373B2 - Active matrix substrate - Google Patents

Description

Detailed Description of the Invention

[Field of Industrial Application] The present invention relates to an active matrix substrate having a thin film transistor array for forming an active matrix display device in combination with liquid crystal or the like. [Prior Art and Its Problems] In an active matrix display device, the occurrence of pixel defects and line defects is a serious defect in quality. Further, in the pixel electrode, there is a voltage drop caused by the resistance component of the transparent conductive film as it goes away from the thin film transistor, and the display quality of the active matrix liquid crystal display device is degraded. In order to prevent these defects, it is necessary to eliminate disconnection of gate bus lines and source bus lines in the active matrix substrate, line leakage, or malfunction of thin film transistors (hereinafter referred to as TFTs). The causes of these defects are dust in the photolithography process or thin film formation process,
Foreign matter or film peeling. The conventional TFT active matrix substrate will be described below. Figure 24 shows picture elements (A _mn ) including TFTs.
Is a TFT active matrix substrate in which are arranged in a matrix. 22 and 23 show a conventional structure of TFT, bus line, and pixel electrode. FIG. 23 shows B- in FIG.
It is a figure showing a B'section. The gate bus lines a and b are formed of tantalum (Ta) on the glass substrate S, and the gate oxide film has a double structure of a tantalum oxide (Ta ₂ O ₅ ) layer c and a silicon nitride (SiNx) layer d. , The semiconductor layers e and f are intrinsic amorphous silicon (a-Si (i)), the source bus lines g and h are titanium (Ti), the drain electrodes i and j are titanium, and the pixel electrodes k and l are ITO films. (Indium oxide transparent conductive film), between the semiconductor layer and the source / drain electrodes, a silicon nitride layer r, m as an etching stopper layer and an n ⁺ type amorphous silicon (a-Si (n ⁺ )) layer p, q. Are formed. Further, in order to prevent a leak between the source and the gate, an a-Si (i) / a-Si (n ⁺ ) layer x and an etching stopper layer n are formed at the cross portion of the source bus line g and the gate bus line a. Has been done. Here, if the tantalum of the gate bus lines a and b or the titanium of the source bus lines g and h breaks for some reason, a linear defect occurs in the active matrix substrate having the conventional structure. Also TFT
Also, if it is damaged for some reason, a pixel defect occurs in the active matrix substrate having the conventional structure. Therefore, conventionally, a process measure has been taken to prevent these defects, but it is difficult to completely prevent them. In view of the above-mentioned drawbacks, the present invention aims to provide a structure of an active matrix substrate for preventing pixel defects due to defective operation of a TFT in the active matrix substrate and improving the image quality of the active matrix display device. And [Means for Solving the Problems] A gate electrode connected to the gate bus line formed corresponding to each intersection of a gate bus line and a source bus line arranged in directions orthogonal to each other, and the source bus In an active matrix substrate in which a thin film transistor including a source electrode connected to a line and a drain electrode connected to a pixel electrode for matrix display is provided as a switching element for display driving, the drain electrode of the thin film transistor is the pixel electrode. It is characterized in that they are arranged so as to be spaced apart from each other in the direction of both ends of the side to be connected and connected. [Operation] According to the structure of the present invention, the voltage drop of each pixel electrode in the active matrix substrate is suppressed. [Embodiment] FIG. 1 shows an amorphous silicon (a-Si) semiconductor TFT active matrix substrate having various kinds of redundancy, which is an embodiment of the present invention. Reference numbers 1 and 5 are a gate bus line and a source bus line, respectively. The TFT 11 is connected to the electrode 13 drawn out from the gate bus line and the electrode 15 drawn out from the source bus line. Reference numeral 14 is a drain electrode, which is a transparent conductive film ITO.
It is connected to the membrane 12. The above substrate structure is the same as the conventional example. The gate bus lines, the source bus lines, and the picture elements will be described below with respect to the portions having various types of redundancy according to the present invention. Gate bus line A bypass line 2 is provided in parallel with the normal gate bus line 1. By providing the bypass in this way, the line width of the bus line is effectively increased. Even if the bus line material is peeled off, the probability that both bus lines 1 and 2 will peel at the same time is lower than the probability of peeling when there is only one bus line. Even if peeling occurs on the TFT, it is
As a whole, it has good operability without defects. Further, as shown in FIG. 21, the gate bus line is made of two layers of conductor thin films, titanium and tantalum, and an insulator thin film is provided between the respective layers of the conductor thin film. Through holes 3 are provided for electrically connecting the respective layers of the conductor thin film. Through hole 3
By connecting the respective conductive films through, it is possible to effectively reduce the resistance of the gate bus line. The cross section 4 with the source bus line is not provided with a bypass section in order to reduce the number of crosses. This is because if the number of cross portions is increased, vertical leakage between the source and the gate is likely to occur and the stray capacitance also increases. Source bus line In addition to the normal source bus line 5, a bypass line 6 is provided at the cross portion with the gate bus line. By providing the bypass line 6, the line width of the source line is effectively increased. Further, as in the case of the gate bus line, the probability of occurrence of peeling of the entire source bus line can be reduced. Also, as shown in detail in FIGS. 16 to 20, the source bus line is also formed of two or more conductor thin films,
Since the insulator thin film is provided between the respective layers of the conductor thin film, the through hole 9 for electrically connecting the respective layers of the conductor thin film is provided. By connecting the conductor thin films through the through holes 9, it is possible to prevent disconnection of the source bus line and at the same time reduce the resistance of the source bus line. Reference numerals 7 and 8 are an a-Si (n ⁺ ) / a-Si (i) layer and an etching stopper SiNx layer, which are semiconductor films for preventing leakage between the source bus line and the gate bus line, respectively. Each of 7 and 8 is formed separately in an island shape at each cross. This is a-Si (n ⁺ ) / a-Si (i) layer 7, etching stopper
The probability of disconnection of the source bus line at the cross portion caused by the peeling of the SiNx layer 8 is reduced by the redundancy of separating into islands. Two TFTs for driving each picture element are provided for one picture element like TFT11,11. Here, two TFTs are connected in parallel to the picture element via a TFT connection read gate line 13 extending from the gate bus line in parallel with the source bus line. That is, the TFTs 11 and 11 are connected to the same gate bus line and the same source bus line. Two TFs
Since the pixel electrode has a relatively large resistance component in T, the voltage drop that occurs with the distance from one TFT is compensated by the other TFT, so that the edge of the pixel electrode side to be electrically connected is And are spaced apart at the other end position. Further, the drain electrode 14 has a two-layer structure using titanium and a pixel electrode material ITO, as described later (see FIGS. 19 and 20). Although the reference numerals 1, 5, 13 and the like described above are used to represent the source bus line, the gate bus line, the gate bus line and the lead line, and the like, hereinafter, the thin film layers constituting them are also represented.

[Description of manufacturing process]

Next, a manufacturing process of the TFT active matrix substrate of FIG. 1 will be described with reference to FIGS. In addition, the hatched portion shown in the following figures indicates the portion to be formed or processed in the process at that time. << Process 1 >> As shown in FIG. 2, tantalum vapor deposition with a film thickness of 500 Å to 5000 Å is deposited on a transparent insulating glass substrate 50, and patterning is performed by a photolithography process like a shaded portion. In FIG. 2, a gate bypass line 2 is provided in parallel with the normal gate bus line 1. Further, no bypass line is formed at the cross section 4 with the source bus line. This is because, as described above, if the cross section of the source / gate is increased, vertical leakage between the source / gate is likely to occur and the stray capacitance also increases. << Process 2 >> Next, as shown by the shaded area in FIG. 3, except for the source bus line 5 in FIG. 2, that is, the gate bus line is oxidized by anodizing the tantalum surface to a film thickness of 500 Å.
Form ˜5000Å Ta ₂ O ₅ . << Process 3 >> Then, the PCVD method is used to form the gate insulating film SiNx layer, a-Si
(I) After forming the semiconductor layer and the etching stopper SiNx layer to a film thickness of 500 Å to 6000 Å, 50 Å to 4000 Å, 300 Å to 5000 Å respectively, patterning is performed by a photolithography process and only the etching stopper layer is shaded in FIG. (See Fig. 13). << Process 4 >> Then, a-Si with a film thickness of 200Å to 2000Å is formed by PCVD.
After forming the (n ⁺ ) layer, the a-Si (n ⁺ ) / a-Si (i) layer is separated into islands as shown by the shaded areas 7 and 7 in FIG. Is patterned (see FIG. 15). << Process 5 >> Next, as shown in FIG. 6, a through hole 9 is formed in the SiNx layer which is the gate insulating film on the source bus line. Further, the through hole 3 is also formed in the SiNx / Ta ₂ O ₅ layer which is the insulator layer on the gate bus line. Two through holes can be opened. This is to provide redundancy and reduce defects in the through holes in the case where one of the through holes is closed due to a defective photolithography process (see FIGS. 16 and 21). << Process 6 >> Subsequently, titanium is sputter-deposited to a film thickness of 500Å to 5000Å, and titanium and a-Si (n ⁺ ) are etched as shown by the hatched pattern in FIG. By the way, the tantalum having the pattern formed in << Process 1 >> and the titanium vapor-deposited in this process are electrically connected through the through holes 9 and 3 by the titanium itself entering into the through holes. Therefore, both the gate bus line and the source bus line have a double structure of titanium and tantalum (see FIGS. 17 and 18). << Process 7 >> Next, ITO, which is a pixel electrode material, is sputter-deposited to a film thickness of 300 Å to 3000 Å, and then an eighth photolithography process is performed.
The ITO film is patterned as shown by the shaded area in the figure. The ITO is patterned not only on the pixel electrode and the drain electrode 14 of the TFT but also on the source bus line and a part of the gate bus line to suppress the occurrence of titanium disconnection due to << Process 6 >>. You can

[Explanation of manufacturing process by cross section]

Next, the manufacturing process of the active matrix substrate according to the present invention will be described with respect to the AA ′ cross section in FIG. FIG. 9 shows the vapor deposition of tantalum having a film thickness of 500Å to 5000Å on the glass substrate 50. Next, the tantalum shown in FIG. 9 is patterned in the cross section as shown in FIG. 10 by the pattern shown in FIG. Then, only the gate bus lines are oxidized as shown by the hatched portions in FIG. 3 to form an oxide film as shown in FIG. Then, the gate oxide film SiN is formed by the PCVD method.
x, semiconductor layer a-Si (i), and etching stopper layer are 500Å ~ 6000Å, 50Å ~ 4000Å, 300Å ~ 5000Å, respectively.
To form (Fig. 12). Then, the etching stopper layer shown in FIG. 12 is formed on the island-shaped etching stopper layer 8 shown in FIG. 4 by the photolithography process (see FIG. 13).
Figure). Next, a semiconductor layer a-Si (n ⁺ ) having a film thickness of 200Å to 2000Å is formed by the PCVD method (Fig. 14). Then, in the photolithography process, the semiconductor layers a-Si (n ⁺ ) and a-Si (i) formed in FIGS.
It is formed in the island pattern 7 in the figure (FIG. 15). Next, through holes 9 are provided in the gate oxide film SiNx (FIG. 16).
After that, titanium was sputter-deposited to a film thickness of 500Å to 5000Å (Fig. 17), and then titanium and a-Si (n ⁺ ) were formed on the source bus line pattern by a photolithography process as shown in Fig. 7. (Fig. 18), ITO as a pixel electrode is sputter-deposited to a film thickness of 300Å to 3000Å (Fig. 19),
Patterning is performed as shown by the shaded area in FIG. 8 (FIG. 20). The above is the manufacturing process for the AA ′ section in FIG. 1. Finally, for reference, the cross-sectional view taken along the line CC ′ of FIG.
It is shown in the figure. [Effect] According to the present invention, the voltage drop of each pixel electrode in the matrix liquid crystal display device using the active matrix substrate can be suppressed. Therefore, the display quality of the active matrix liquid crystal display device becomes good.

[Brief description of drawings]

FIG. 1 is a structural diagram of a thin film transistor of an active matrix substrate according to the present invention. 2 to 8 are views showing the thin film transistor array manufacturing process in FIG. 1, respectively. 9 to 20 are sectional views showing the manufacturing process of the thin film transistor array in FIG. 1 taken along the line AA '. FIG. 21 shows C of the thin film transistor array in FIG.
It is a sectional view of the -C 'line direction. FIG. 22 is a diagram showing a thin film transistor having a conventional structure. FIG. 23 shows BB ′ of the thin film transistor in FIG.
It is sectional drawing of a line direction. FIG. 24 is a diagram showing an active matrix substrate in which picture elements (A _mn ) including thin film transistors are arranged in a matrix. 1 ... Gate bus line, 11 ... Thin film transistor, 13 ... Lead line from gate bus line, 50 ... Glass substrate.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasunori Shimada 22-22 Nagaike-cho, Abeno-ku, Osaka-shi, Osaka Within Sharp Corporation (72) Inventor Hiroshi Morimoto 22-22 Nagaike-cho, Abeno-ku, Osaka-shi, Osaka (56) References JP-A-61-249078 (JP, A)

Claims (1)

[Claims] 1. A gate electrode connected to the gate bus line formed corresponding to each intersection of a gate bus line and a source bus line arranged in directions orthogonal to each other, and connected to the source bus line. In an active matrix substrate in which a plurality of thin film transistors each including a source electrode and a drain electrode connected to a pixel electrode for matrix display are provided as a switching element for display driving per pixel electrode, the drain electrode of the thin film transistor is the pixel An active matrix substrate, wherein the active matrix substrate is arranged so as to be separated from each other in both end directions of a side connected to an electrode.