JPH0680646B2 - Dry etching method - Google Patents
Dry etching methodInfo
- Publication number
- JPH0680646B2 JPH0680646B2 JP3694488A JP3694488A JPH0680646B2 JP H0680646 B2 JPH0680646 B2 JP H0680646B2 JP 3694488 A JP3694488 A JP 3694488A JP 3694488 A JP3694488 A JP 3694488A JP H0680646 B2 JPH0680646 B2 JP H0680646B2
- Authority
- JP
- Japan
- Prior art keywords
- etching
- etching method
- dry etching
- film
- rie
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims description 11
- 238000001312 dry etching Methods 0.000 title claims description 4
- 238000005530 etching Methods 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 6
- 238000001020 plasma etching Methods 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はドライエッチング方法に関し、特に有機膜の異
方性エッチング方法に関する。The present invention relates to a dry etching method, and more particularly to an anisotropic etching method for an organic film.
従来のこの種のエッチング方法を第３図を用いて説明す
る。第３図（ａ）のように半導体基板１の上に形成した
下層レジスト２の上に酸化ケイ素膜３を形成し、その上
に上層レジスト４のパターンを形成する。次に第３図
（ｂ）に示したように中間層にある酸化ケイ素膜３をCF
4+H2を用いたRIE（反応性イオンエッチング）でエッチ
ングする。次にO2のRIEで下層レジスト２を異方性エッ
チングする（第３図（ｃ））。この時、この下層レジス
トのエッチングが途中で止ってしまう場合が多い。A conventional etching method of this type will be described with reference to FIG. As shown in FIG. 3A, the silicon oxide film 3 is formed on the lower layer resist 2 formed on the semiconductor substrate 1, and the pattern of the upper layer resist 4 is formed thereon. Next, as shown in FIG. 3 (b), the silicon oxide film 3 in the intermediate layer is removed by CF.
Etch by RIE (Reactive Ion Etching) using 4 + H 2 . Next, the lower layer resist 2 is anisotropically etched by RIE of O 2 (FIG. 3 (c)). At this time, the etching of the lower layer resist often stops halfway.
上述した従来の有機膜の異方性エッチング方法では、下
地有機膜をエッチングされにくい無機膜をマスクにして
エッチングを行うと、エッチング中に開孔部から水分な
どの蒸発がおこり、エッチング用ガスの進入が妨害され
るため第３図（ｃ）に示すようにエッチングが途中で止
まってしまうという欠点がある。In the above-described conventional anisotropic etching method for an organic film, when the underlying organic film is etched by using an inorganic film that is difficult to be etched as a mask, evaporation of water or the like occurs from the opening during etching, which causes the etching gas Since the entry is blocked, there is a drawback that the etching stops midway as shown in FIG. 3 (c).
本発明のドライエッチング方法は、半導体基板上に形成
された有機膜層を無機膜をマスクとして異方性エッチン
グする方法において、前記エッチング直前に真空中で10
0℃以上のベークを行うことである。The dry etching method of the present invention is a method of anisotropically etching an organic film layer formed on a semiconductor substrate using an inorganic film as a mask, in a vacuum just before the etching.
It is to bake above 0 ° C.
次に、本発明について図面を参照して説明する。第１図
は、本発明の一実施例の縦断面図である。半導体基板１
の上に形成した下層レジスト２の上に中間層としてスパ
ッタリング法により酸化ケイ素膜３を1000Å厚を形成
し、その上にパターン化した上層レジスト４を形成する
（第１図（ａ））。次に中間層である酸化ケイ素膜３の
エッチングをCF4+H2を用いたRIEで行う（第１図
（ｂ））。次に130℃で真空ベークを30分行いレジスト
中のH2O,N2を追い出す（第１図（ｃ））。その直後にO2
を用いたRIEで下層レジスト２をエッチングする（第１
図（ｄ））。上記のベーク処理を行なうことにより、開
口部中の水分や窒素等を追い出すことができ、O2による
RIEがうまく行き、良好なエッチングが実現できた。Next, the present invention will be described with reference to the drawings. FIG. 1 is a vertical sectional view of an embodiment of the present invention. Semiconductor substrate 1
A silicon oxide film 3 having a thickness of 1000 Å is formed as an intermediate layer on the lower layer resist 2 formed on the substrate by a sputtering method, and a patterned upper layer resist 4 is formed thereon (FIG. 1 (a)). Next, the silicon oxide film 3 as the intermediate layer is etched by RIE using CF 4 + H 2 (FIG. 1 (b)). Next, vacuum baking is performed at 130 ° C. for 30 minutes to drive out H 2 O and N 2 in the resist (FIG. 1 (c)). Shortly thereafter O 2
Etch the lower resist 2 by RIE (first
Figure (d)). By performing the above baking treatment, water, nitrogen, etc. in the opening can be expelled, and O 2
The RIE went well and good etching was achieved.
第２図は、本発明の他の実施例の縦断面図である。半導
体基板１上に形成したPSG（Phosphorous Silicate Glas
s）膜８の上に１層目のAl配線を形成し、その上にポリ
イミドを１μｍの厚さで塗布後400℃でベークした後、T
i膜７を1000Å厚スパッタでつける。その上に上層レジ
スト12を形成しパターニングする（第２図（ａ））。上
層レジスト12をマスクにTi膜をSF6+CCl4を用いたRIEで
エッチングする（第２図（ｂ））。FIG. 2 is a vertical sectional view of another embodiment of the present invention. PSG (Phosphorous Silicate Glas) formed on the semiconductor substrate 1
s) Form the first layer of Al wiring on the film 8, apply polyimide on it to a thickness of 1 μm, and bake at 400 ° C.
The i film 7 is applied by sputtering with a thickness of 1000Å. An upper layer resist 12 is formed thereon and patterned (FIG. 2 (a)). The Ti film is etched by RIE using SF 6 + CCl 4 using the upper resist 12 as a mask (FIG. 2B).
次に真空中で130℃、30分ベークを行なうと第２図
（ｃ）に示したように開口部の水分が蒸発する。次にO2
+SF6のRIEを行う（第２図（ｄ））。第２図（ｃ）の工
程を入れることにより第２図（ｄ）のような良好なエッ
チングが行える。Next, when baking is performed in vacuum at 130 ° C. for 30 minutes, the water in the openings evaporates as shown in FIG. 2 (c). Then O 2
Perform RIE of + SF 6 (Fig. 2 (d)). By including the step of FIG. 2C, good etching as shown in FIG. 2D can be performed.
以上説明したように、本発明は、無機膜をマスクに有機
膜をエッチングする直前に100℃以上の真空ベークを行
うことにより開口部から水分を蒸発させ、エッチング中
に有機膜からの水分等の影響を受けにくくすることがで
き、良好な異方性エッチングを行うことができる。As described above, the present invention evaporates water from the opening by performing a vacuum bake at 100 ° C. or more immediately before etching the organic film using the inorganic film as a mask, and removes water or the like from the organic film during etching. It is possible to make it difficult to be affected and to perform good anisotropic etching.
第１図は本発明の一実施例をプロセス順に示した縦断面
図、第２図は本発明の他の実施例をプロセス順に示した
縦断面図、第３図は従来の方法を示す縦断面図である。 １……半導体基板、２……下層レジスト、３……酸化ケ
イ素膜、４……上層レジスト、５……PSG、６……ポリ
イミド、７……Ti、８……Al。FIG. 1 is a vertical sectional view showing an embodiment of the present invention in process order, FIG. 2 is a vertical sectional view showing another embodiment of the present invention in process order, and FIG. 3 is a vertical sectional view showing a conventional method. It is a figure. 1 ... Semiconductor substrate, 2 ... Lower layer resist, 3 ... Silicon oxide film, 4 ... Upper layer resist, 5 ... PSG, 6 ... Polyimide, 7 ... Ti, 8 ... Al.
Claims (1)
膜をマスクとして異方性エッチングする方法において、
前記エッチング直前に真空中でベークを行うことを特徴
とするドライエッチング方法。1. A method of anisotropically etching an organic film layer formed on a semiconductor substrate using an inorganic film as a mask,
A dry etching method characterized in that baking is performed in a vacuum immediately before the etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3694488A JPH0680646B2 (en) | 1988-02-18 | 1988-02-18 | Dry etching method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3694488A JPH0680646B2 (en) | 1988-02-18 | 1988-02-18 | Dry etching method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01211923A JPH01211923A (en) | 1989-08-25 |
| JPH0680646B2 true JPH0680646B2 (en) | 1994-10-12 |
Family
ID=12483864
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3694488A Expired - Fee Related JPH0680646B2 (en) | 1988-02-18 | 1988-02-18 | Dry etching method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0680646B2 (en) |
-
1988
- 1988-02-18 JP JP3694488A patent/JPH0680646B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01211923A (en) | 1989-08-25 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |