JPH0681132B2 - Clock asynchronous data detection method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a clock asynchronous data detection system, and in particular, in receiving a burst data signal, a clock oscillator output asynchronous with the clock signal of the received data signal. The present invention relates to an asynchronous data detection method for discriminating a data signal by using.

(Prior Art) Conventionally, in transmitting a burst data signal, it is necessary to synchronize the output of the clock oscillator of the receiver with the phase of the clock frequency of the received data signal. The amble bit was added.

FIG. 3 is a frame structure diagram of a conventional system for transmitting a data signal in bursts. In FIG. 3, PRE is a preamble bit and is a bit for synchronizing a clock oscillator for discriminating a frame signal and a data signal. FR is a bit for a frame signal and plays a role of teaching the beginning of a data signal and always has the same code pattern. DATA is the data signal itself.

(Problems to be Solved by the Invention) As can be understood from FIG. 3, the preamble bit PR
Since E is required, the use efficiency of the transmission line (= (data signal bit DATA) / (preamble bit PRE + frame signal bit FR + data signal bit DATA)) was extremely low.

The present invention aims to improve this point.

(Means for Solving the Problems) In the present invention, a plurality of clock pulse trains having different phases are generated from an oscillator output having a frequency substantially equal to the clock frequency of the received data signal, and the received signal is sampled for each clock pulse. At the same time, analog / digital conversion is performed, the absolute values are integrated for a certain period of time, and the sign of the received signal is determined by the clock pulse train that maximizes the integrated result.

(Operation) In the frame structure of the present invention, the preamble bit PRE is eliminated and the frame signal bit FR and the data signal bit DATA are used. The received signal is discriminated by a series of clock pulse trains that are asynchronous with this, and the sum of the absolute values of the discrimination results by each clock pulse train gives the largest sum (corresponding to the smallest code error) of the received signal. Judgment is made.

(Embodiment) FIG. 1 is a circuit configuration example of the present invention, in which an output of a demodulator DEM of a receiver is distributed to n outputs by an n division distributor HYB. This output generates an n-phase clock pulse with the same frequency as the clock frequency created on the receiving side, and connects it to the analog / digital converters A / D1, A / D2, ..., A / Dn-1, A / Dn, respectively. Then
The received signal is sampled and encoded. As a method of generating this clock, for example, the output of a clock oscillator CLK that oscillates at a frequency substantially equal to the clock frequency of the received data signal is used as n-1 delay circuits DEL # 1, DEL # 2, ..., DEL # n-1.
To generate clock pulses # 1, # 2, ..., #n with different phases for one cycle of the clock oscillation frequency.
Generates a pulse n times the clock, divides it by n, and
There is a method of generating a pulse train of phases.

Sign bits representing positive and negative are removed from the digital signal obtained by encoding, and the remaining bits representing the absolute value are connected to respective integrators ACU1, ACU2, ..., ACUn−1, ACUn, and integrated for a predetermined time. The integrated result is connected to the maximum value detection circuit MAX.DET, and the clock sequence having the maximum integrated result is determined. This determination output is connected to the switch SW, and switches the same sequence as the clock pulse sequence having the maximum integration result so as to serve as the receiver. SR1, SR2, ..., S
Rn−1 and SRn are shift registers, and the passage time is selected so as to be equal to or longer than the integration time in the integrator ACU.
The analog / digital converter A / D output signal connected to the shift register SR is connected so that only the sign bit representing the positive / negative of the encoded digital signal is output.

The case where the integration result is maximum corresponds to sampling at the maximum point of the amplitude of the demodulation output, and in this case the code error is the smallest.

FIG. 2 is a diagram showing the timing relationship between the demodulator DEM output applied to each analog / digital converter A / D and sampling. Each analog / digital converter A / D1, A / D2,
, A / Dn−1, A / Dn and the demodulator DEM output that is added are only distributed by the distributor HYB and have the same phase. Therefore,
The DEM output waveform is shown as a representative. Clock pulses (sampling pulses) applied to each analog / digital converter A / D1, A / D2, ..., A / Dn-1, A / Dn are # 1, # 2, ..., # n-1, #.
Denote by n. As can be easily understood from the figure, the series sampled by the clock pulse #m gives the maximum integration result, and the result of the data signal determination in this series is output as the receiver output.

In the description of the present invention, the case where the data signal is transmitted in the burst form has been described, but it can be easily understood that the present invention can be applied not only when the data signal is in the burst form.

(Effects of the Invention) As described above, according to the present invention, it is not necessary to generate a clock pulse synchronized with a received signal, so that the preamble bit necessary for clock synchronization can be removed, and the efficiency of use of the transmission line can be improved. Can be greatly enhanced. It can also be used for demodulating not only burst data but also continuous data.

[Brief description of drawings]

FIG. 1 is an example of a circuit configuration of the present invention, FIG. 2 is a diagram showing a relationship between an analog / digital converter of the present invention and clock timing, and FIG. 3 is an example of a conventional data transmission frame configuration. PRE: Preamble bit, FR: Frame signal bit, D
ATA: Data signal bit, DEM: Demodulator, A / D1, A / D2, ..., A / D
n−1, A / Dn: Analog / digital converter 1, 2, ..., n−1,
n, HYB: Signal distributor, CLK: Clock oscillator, DEL # 1, DEL
# 2, ..., DEL # n−1: delay circuits 1, 2, ..., n−1, ACU1, ACU2,
…, ACUn−1, ACUn: Accumulators 1, 2,…, n−1, n, SR1, SR2,…, SR
n−1, SRn: shift registers 1, 2, ..., N−1, n, SW: switch.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-55-121761 (JP, A) JP-A-60-153245 (JP, A) JP-A-55-93350 (JP, A)

Claims (1)

[Claims] 1. A data transmission receiving unit generates a plurality of sequences of clock pulses having a repetition frequency which is approximately equal to a clock frequency of the received signal asynchronously with the received signal and generates clock pulse sequences having mutually different phases. It is characterized in that the sampling signal is encoded and encoded, the absolute value of the encoded signal is integrated for each clock pulse sequence for a predetermined time, and the received signal is discriminated and output by the clock pulse sequence that gives the maximum integrated value. A clock asynchronous data detection method.