JPH0681133B2 - Clock asynchronous data detection method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a clock asynchronous data detection system, and in particular, in a burst data signal reception, a clock oscillator output that is asynchronous with the clock signal of the received data signal. The present invention relates to an asynchronous data detection method for discriminating a data signal by using.

(Prior Art) Conventionally, in transmission of a burst data signal, it is necessary to synchronize the output of the clock oscillator of the receiver with the phase of the clock frequency of the received data signal. An amble bit was added. FIG. 3 is a frame structure diagram of a conventional system for transmitting a data signal in bursts. In Figure 3, PRE
Is a preamble bit for synchronizing a clock oscillator for discriminating a frame signal and a data signal. FR is a bit for a frame signal, which plays a role of teaching the beginning of a data signal and always has the same code pattern. DATA is the data signal itself.

(Problems to be solved by the invention) However, as can be understood from FIG. 3 in the conventional method, since the preamble bit PRE is required, the use efficiency of the transmission line (= (data signal bit DATA) / ( Preamble bit PRE + frame signal bit FR + data signal bit DATA)) was very low.

The present invention aims to improve this point.

(Means for Solving the Problems) In the present invention, the received signal is sampled at the output of an oscillator which is substantially equal to the frequency n times the clock frequency of the received data signal, analog / digital conversion is performed, and the converted pulse signal train is An analog / digitally converted digital signal is separated every n bits with respect to the sampling pulse, and n having a phase difference of every 1 bit.
A set of data strings is generated, and only the absolute value of each of the n sets of data strings is accumulated for a certain time corresponding to each sampling, and the sign of the received signal is determined by the sampling sequence having the largest integrated result. Determine.

(Operation) In the frame structure of the present invention, the preamble bit PRE is eliminated and the frame signal bit FR and the data signal bit DATA are used. The received signal is sampled and coded asynchronously with a pulse train of n times the clock frequency.
The absolute value of the encoded digital signal is separated into n sets of data strings having a phase difference every other bit, and the integration of the absolute values of the data of each set is taken for a predetermined time. The received signal is discriminated by the sampling sequence that maximizes the sum of products.

(Embodiment) In the circuit configuration example of FIG. 1, the output of the demodulator DEM of the receiver is connected to the analog / digital converter A / D. CLK is a clock oscillator that oscillates a frequency approximately equal to n times the clock frequency of the received signal, and this oscillation output is connected to the analog / digital converter A / D to sample the analog signal from the demodulator DEM and code it. Turn into. On the other hand, the output of the clock oscillator LCK is connected to the n-bit counter nCOUNT,
The output has a phase difference of one pulse with respect to the oscillator output pulse train, and n pulse distribution circuits PH1 and P that generate pulses every n pulses from the output pulse train of the oscillation CLK.
It is connected to H2, ..., PHn _-1 , PHn. Pulse distribution circuit PH1, PH
The outputs of 2, ..., PHn _-1 , PHn are gate circuits GAT1 and GAT, respectively.
2, ..., GATn ₋₁ , GATn are added to the digital signal encoded by the analog / digital converter A / D to be separated for each sampling and output. Each gate circuit GAT1, GAT2,
,, GATn _-1 ,, GATn outputs the remaining bits of the encoded digital signal except the sign bit representing the positive and negative of the sample value, respectively, by accumulators ACU1, ACU2, ..., ACUn _-1 ,, ACUn
Connect to and integrate for a certain time. The integrated result is connected to the maximum value detection circuit MAX.DET, and the series having the maximum integrated result is determined. This judgment output is connected to the switch SW, and the reception connected to the gate circuit GAT in the same series as the series in which the integration result is the maximum is switched to be output as the receiver output. SR1, SR2, ..., SRn _-1 , SRn are shift registers, and the passage time is selected so as to be equal to or longer than the integration time of the integrator ACU. The gate circuit GAT output signal connected to the shift register SR is connected so that only the sine bit representing the positive / negative of the sample value is output in the analog / digital converter A / D.

In addition, counter nCOUNT, pulse distribution circuits PH1 to PHn, gate circuits GAT1 to GATn, accumulators ACU1 to ACUn, maximum value detection circuit MA
The part of X.DET can be configured by a microprocessor, and the operation of each circuit can be realized by software. In that case, the present invention has the advantage that the A / D converter is sufficient.

FIG. 3 shows the relationship between the demodulator DEM output signal, the clock oscillator CLK and the pulse distributor PH output. Demodulator DEM
The output signal is sampled and encoded with the clock oscillator CLK output pulse. The coded signals differ in phase by one bit with respect to the clock pulse train, and clock distribution circuits PH1, PH2, ..., PHn that generate a pulse every n clocks.
_-1 , Separated by PHn output pulse. Of the separated pulses, the bits excluding the sine bit that indicates whether the DEM output signal is positive or negative when sampled are integrated by the integration circuit ACU1, ACU2, ..., ACUn _-1 , ACUn for a certain time. To be done. In this case, as can be easily understood from the figure, the output system of the pulse distributor PHm gives the maximum integration result. Therefore, the switch SW is connected so that the sine bit when sampled by the output system of the pulse distributor PHm is output as the receiver output.

In the present invention, the case where the data signal is transmitted in the burst form has been described, but it can be easily understood that the present invention can be applied not only when the data signal is in the burst form.

(Effect of the Invention) As described above, according to the present invention, since it is not necessary to generate the clock pulse synchronized with the received signal, the preamble bit necessary for the clock synchronization can be removed, and the use efficiency of the transmission line can be greatly improved. You can It can also be used for demodulating not only burst data but also continuous data.

[Brief description of drawings]

FIG. 1 is a circuit configuration example of the present invention, FIG. 2 is a diagram showing a phase relationship between a demodulator output waveform, a clock (sampling) pulse, and a pulse distributor output according to the present invention. FIG. 3 is a conventional data transmission. It is an example of a frame configuration. PRE: Preamble bit, FR: Frame signal bit, DAT
A: data signal bit, DEM: demodulator, A / D: analog / digital converter, CLK: clock oscillator, nCOUNT: n bit counter, PH1, PH2, ..., PHn _-1 , PHn: pulse distribution circuit 1, 2, ..., n
-1, n, GAT1, GAT2, ..., GATn _-1 ,, GATn: Gate circuit 1,2, ..., n
-1, n, ACU1, ACU2, ..., ACUn _-1 ,, ACUn: Accumulator circuit 1,2, ..., n-
1, n, SR1, SR2, ..., SRn _-1 ,, SRn: Shift register 1,2, ..., n−
1, n, MAX.DET: Maximum value detection circuit, SW: Switch

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-55-121761 (JP, A) JP-A-60-153245 (JP, A) JP-A-55-93350 (JP, A)

Claims (1)

[Claims] 1. A receiver for data transmission asynchronously with a received signal, the clock frequency of which is n times (n is 2).
The received signal is sampled and encoded at a clock frequency that is almost equal to the repetition frequency of the above integer), and the encoded received signal is separated into n sets of different phases by 1 bit extracted every n bits. The clock asynchronous data detection method is characterized in that the absolute value of the sample value is accumulated for each separated sequence for a predetermined time, and the sine bit of the sample value of the sequence having the maximum integration result is received and output.