JPH0681146B2 - Data bus circuit - Google Patents

Description

The present invention relates to a data bus circuit based on a semiconductor integrated circuit,
In particular, it relates to a data bus circuit using a CMOS circuit.

[Conventional technology]

Conventionally, when performing data transfer in synchronization with a plurality of clocks by sharing a single data bus, the data bus has been configured as a static bus. FIG. 5 is a circuit diagram showing an example of the data bus circuit, and FIG. 6 is a diagram showing an example of its operation timing. The circuit shown in FIG. 5 corresponds to one bit of the data bus. The data A is output to the data bus DB by the signal 53 in which the output enable signal E _A is synchronized with the clock Φ _A , and the data B is in the data bus by the signal 54 in which the output enable signal E _B is synchronized with the clock Φ _B. Output to DB. Clock Φ
_{Although A} and Φ _B are asynchronous with each other, E _A and E _B are arbitrated so that the data A and B do not compete on the data bus DB. DB becomes floating when both 53 and 54 signals are inactive. The circuit of 51,52 is
It is a commonly used 3-state output buffer.

[Problems to be solved by the invention]

The above-mentioned static bus configuration is characterized by relatively stable operation and easy design, but as shown in Figs. 51 and 52 of Fig. 5, the output buffer section becomes large in size and the load capacity of the bus becomes large. Has a drawback that it is not suitable for high speed operation.

In contrast to the above-described conventional data bus circuit having a static bus structure, the present invention has an original content of providing a data bus circuit that enables dynamic transfer even in data transfer synchronized with a plurality of asynchronous clocks.

[Means for solving problems]

The data bus circuit of the present invention comprises precharge means for raising the potential of a single data bus to a high level and data transfer means for transferring predetermined data to the data bus in synchronization with a predetermined clock signal. A data bus having a plurality of the data transfer means and for transferring the data in response to a plurality of output enable signals for controlling data output availability and asynchronous with each other and having a predetermined signal interval. In the circuit, the precharge means has a MOS transistor connected between a high-potential power supply potential and the data bus, and is supplied with a plurality of mutually asynchronous clock signals and a plurality of enable signals. Each of the signals selects the predetermined clock signal and a first level period of the clock signal A first configuration in which the MOS transistor is made conductive only during a period, and a MOS transistor connected between a high power supply potential and the data bus, and a single clock signal of the plurality of clock signals A plurality of the enable signals synchronized with the clock signal other than the clock signal are respectively supplied, and the plurality of enable signals are selected only during the first level period of the single clock signal to turn on the MOS transistor. The data output means includes one of the second configurations configured to be conductive, and one of the plurality of data is provided to one gate of two MOS transistors connected in series between the data bus and the low power supply potential. One of the enable signals is supplied to the other of the first clock signals of the predetermined clock signal. Of the first clock signal and this clock signal at the gate of the MOS transistor connected between the high-potential power source potential and the low-potential power source potential. The precharge means includes one of a second configuration in which one of the plurality of data is supplied when the logic of the enable signal synchronized with the one of the plurality of enable signals is matched. Of the first configuration of the data output means, the second configuration of the precharge means and the second configuration of the data output means, and the second configuration of the precharge means. And a first configuration of the data output means.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention, showing one bit of a data bus. FIG. 2 is a diagram showing an example of the operation timing. Signal E _A , E _B
Are signals synchronized with the falling edges of their asynchronous clocks Φ _A and Φ _B , but are assumed to be arbitrated so that transfer cycles of data and data do not overlap. First, when E _A becomes active, only the high level (hereinafter “H”) period of Φ _A overlapping with E _A by the control circuit 17 Becomes active. At this time, the output values of the output buffer circuits 11 and 12 are high impedance ("Hi-z"). The output value "Hi-z" of 11 is due to Φ _A input to the circuit 13, and the output value "Hi-z" of 12 is that the signal E _B input to the circuit 14 is inactive. It depends. Therefore, the data bus DB during this period Precharged to "H" by the P-channel type MOS transistor 18 which receives the active state. Next, when Φ _A becomes low level (hereinafter referred to as “L”), the transistor 18 becomes OF
Since the F signal 15 becomes active, when the data is "H", DB is pulled down by the output buffer circuit 11 to "L".
When the data is "L", the output of the circuit 11 is "Hi-
Since it becomes "z", DB is precharged to "H". When E _A becomes inactive and the transfer cycle ends, signal 15 becomes inactive and DB becomes floating. Even in the transfer cycle, exactly the same operation is performed based on the signal E _B and the clock Φ _B.

In the present embodiment, the precharge control circuit 17 has been described as a combination circuit having two AND gates for ease of description. However, in this type of circuit, the output buffer circuit 11 and
Since two or more 12's are usually used, in that case it is natural to increase the number of AND gates according to the number of output buffers.

FIG. 3 is a block diagram showing a second embodiment of the present invention, showing one bit of the data bus.
FIG. 4 is a diagram showing an example of the operation timing.
The clocks Φ _A and Φ _B are asynchronous as in the first embodiment, and the output enable signals E _A and E _B are arbitrated so that the transfer cycles of the data A and the data B do not overlap. And When the enable signal E _B is inactive, this data bus circuit operates as a dynamic data bus circuit based on Φ _A. If the enable signal E _B becomes active, the Φ _B latch and output signal 33 Becomes inactive unconditionally, and the precharge transistor 35 is turned off while the signal 33 is "H". On the other hand, at this time, the data B is DB by the 3-state output buffer 32.
Is output statically. In the present embodiment, the cycle time of 1 clock Φ _B is very slow, and the data retention by the DB is not sufficient, so that the present embodiment can be applied when the configuration of the first embodiment cannot be taken. This is an example of a workaround that solves the conventional problems.

[Effects of the Invention] As described above, the present invention, on a single data bus,
Even when data transfer is performed in synchronization with a plurality of asynchronous clocks, it has a MOS transistor connected between the high power supply potential and the data bus, and a plurality of mutually asynchronous clock signals and a plurality of enable signals are respectively provided. A first configuration in which the enable signals are supplied to select predetermined clock signals and the MOS transistors are made conductive only during a first level period of the clock signals; and a single clock of the plurality of clock signals A signal and a plurality of enable signals synchronized with the clock signal other than the clock signal are respectively supplied, and the plurality of enable signals are selected only during the first level period of a single clock signal to generate the MO signal.
A precharge means including one of the second configurations for making the S transistor conductive, and two MOSs connected in series between the data bus and the low potential power supply potential.
One of the plurality of data is supplied to one gate of the transistor, and one of the plurality of enable signals is supplied to the other of the transistor during the inversion level period of the first level of the predetermined clock signal. The gate of the MOS transistor connected between the high-potential power supply potential and the low-potential power supply potential has a single clock signal and one of a plurality of enable signals synchronized by the clock signal. A first configuration of the precharge means, the data output means including one of the second configurations in which one of the plurality of data is supplied when the logics of the two match. And a first configuration of the data output means, a second configuration of the precharge means and a second configuration of the data output means, and a second configuration of the precharge means. Since one of the combination with the first structure of the data output means is provided, a complete dynamic bus or a static-dynamic composite bus can be realized, and the output buffer circuit structure which is an advantage of the dynamic bus circuit is simple. , The capacity of the bus itself becomes small and high speed operation becomes possible.

[Brief description of drawings]

1 is a circuit diagram showing a first embodiment of the present invention, FIG. 2 is a diagram showing an example of the operation timing of FIG. 1, FIG. 3 is a circuit diagram showing a second embodiment of the present invention, FIG. 4 is a diagram showing an example of the operation timing of FIG. 3, and FIGS. 5 and 6 are circuit diagrams showing a conventional example and an example of the operation timing thereof. DB: Data bus, Φ _A , Φ _B: Clock, 17,34 …… Precharge control circuit, 18,35 …… Precharge transistor, 13,14 …… Data output control circuit, 11,1
2,31,32,51,52 ... Output buffer circuit.

Claims (1)

[Claims] 1. A precharge means for raising the potential of a single data bus to a high level, and a data transfer means for transferring predetermined data to the data bus in synchronization with a predetermined clock signal. A data bus circuit that uses a plurality of the data transfer means and that transfers the data in response to a plurality of output enable signals for controlling data output availability and asynchronous with each other and having a predetermined signal interval; The precharge means has a MOS transistor connected between a high power supply potential and the data bus, and is supplied with a plurality of clock signals and a plurality of enable signals that are asynchronous with each other, and these enable signals are respectively supplied. The predetermined clock signal is selected and the MOS transistor is operated only during the first level period of the clock signal. A first configuration for making a transistor conductive, and a single clock signal of the plurality of clock signals having a MOS transistor connected between the high power supply potential and the data bus and a clock signal other than the clock signal A plurality of the enable signals synchronized with the clock signal are respectively supplied, and the plurality of enable signals are selected only during the first level period of the single clock signal to turn on the MOS transistor. One of a plurality of data is supplied to the gate of one of the two MOS transistors connected in series between the data bus and the low power supply potential. And, on the other hand, one of the enable signals is an inversion of the first level of the predetermined clock signal. The first configuration adapted to be supplied during the level period, and the gate of the MOS transistor connected between the high power supply potential and the low power supply potential are synchronized with the single clock signal and this clock signal. A first configuration of the precharging means, including one of the second configurations in which one of the plurality of data is supplied when the logic matches one of the plurality of enable signals. A combination of a configuration and the first configuration of the data output means, a second configuration of the precharge means and a second configuration of the data output means, and a second configuration of the precharge means and the above A data bus circuit comprising one of a combination with the first configuration of the data output means.