JPH0681282B2 - Photo detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a photoelectric conversion element, which is a constituent element of an image reading image sensor or the like applied to an image reading apparatus, and more specifically, to a signal extraction electrode. The present invention relates to a photodetector circuit using a photoelectric conversion element having a charge generating function and a charge accumulating function according to the amount of incident light between two electrodes including, more specifically, application of a reference bias between the photoelectric conversion element electrodes or A reference bias switching element for switching the cutoff and a buffer amplifier circuit for outputting a signal at a level within the supply voltage range according to the signal output of the signal extraction electrode based on the charge storage state of the photoelectric conversion element are provided. The present invention relates to a photo detection circuit.

[Prior Art] Each cell of an image sensor made of a semiconductor material such as amorphous silicon constitutes a photoelectric conversion element, and its specific structure is, for example, as shown in FIG. A lower layer electrode 12 is formed, and a photoconductor 13 and an upper layer transparent electrode are formed.
14 are sequentially stacked.

The photoelectric conversion element having such a structure has an upper transparent electrode 14
Basically, it has a charge generation function according to the amount of light incident through the light source and a charge storage function. As shown in FIG. 7, the equivalent circuit configuration is such that the photocurrent source 15 corresponding to the charge generation function and the capacitance element 16 corresponding to the charge storage function are provided between the electrodes (the lower layer electrode 12 and the upper layer transparent electrode 14). Be connected in parallel. When using this photoelectric conversion element, a reference bias Vb is applied between the lower layer electrode 12 and the upper layer transparent electrode 14. In this case, the lower electrode
The potential of 12 is applied to be a high potential. For example, as shown in FIG. 8 (a), the lower layer electrode 12 is held at the ground level (0V) and -5V is applied to the upper layer transparent electrode 14. In the case (Vb = 5V), the output level of the lower layer electrode 12 as a signal extraction electrode drops by about 0.8V when no light is incident (effect of dark current) to about −0.8V, while light is incident. Due to the accumulated charge that sometimes occurs, the maximum voltage drops by about 2V −
It will be about 2V. Further, as shown in FIG. 8 (b), when 5V is applied to the lower layer electrode 12 and the upper layer transparent electrode 14 is held at the ground level (Vb = 5V), the output level of the lower layer electrode 14 is in the above case. The output level when the light is not incident is about 4.2V, while the maximum output level when the light is incident is about 3V.

In the conventional photodetector circuit using the photoelectric conversion element having the above characteristics, the accumulated charge corresponding to the amount of incident light in the photoelectric conversion element itself is minute, and it is difficult to detect the current corresponding to the generated charge. Therefore, the output signal from the photoelectric conversion element is amplified by the buffer amplifier (voltage detection method).

Specifically, for example, it is as shown in FIG. 9 (see Fuji Xerox Technical Report No. 1 1986 page 19). In this example, a −5V power supply is used as the bias voltage power supply for the photoelectric conversion element.

In FIG. 9, the reference bias Vb (= 5V) is applied between the electrodes of the photoelectric conversion element 10 composed of the photocurrent source 15 and the capacitive element 16 via the FET gate 18 as a switching element. There is. This bias application applies a ground level (0 V) via the FET gate 18 to the lower layer electrode 12 (hereinafter, referred to as the signal extraction electrode 12) which becomes the signal extraction electrode of the photoelectric conversion element 10, while the upper layer transparent electrode 14 has a voltage of -5 V. Is being applied. Then, the signal extraction electrode 12 of the photoelectric conversion element 10
Is connected to the input terminal (+) of the buffer amplifier 20 composed of a voltage follower by an operational amplifier. Due to such a connection structure of the photoelectric conversion element 10 and the buffer amplifier 20, a signal in the level range (0 to −2 V) as shown in FIG. 8A is input to the input terminal (+) of the buffer amplifier 20. . Here, in order to guarantee the linearity of the output of the buffer amplifier 20 with respect to the input of the signal in the level range, the input signal level range does not approach the upper limit value of the supply voltage range (power supply voltage) of the buffer amplifier 20. So, for example, −
Set to 5V to + 5v. This is because the normal amplifier loses its linearity when the output level approaches the supplied power supply voltage.

In the photodetector circuit having the above configuration, first, the FET gate 18 is turned on to precharge the signal extraction electrode 12 side of the capacitive element 16 of the photoelectric conversion element 10 to 0 V, and then the FET gate 18 is turned off, The electric charge (equivalent to that supplied from the photocurrent source 15) generated according to the amount of incident light is accumulated in the capacitance element 16, and the level of the signal extraction electrode 12 is lowered.
The output signal level from the signal extraction electrode 12 of the photoelectric conversion element 10 corresponds to the amount of incident light by making the off time constant during the on / off control of the FET gate 18.

The FET gate 18 and the buffer amplifier 20 as the switching elements are configured as elements in the image sensor LSI. A basic configuration example thereof is, for example, as shown in FIG.

In the figure, 100 is an image sensor in which the photoelectric conversion elements 10 as described above are unit cells and are sequentially arranged, and 200 is an image sensor LSI. In the image sensor LSI 200, the reference bias switching elements 18 (1), 18 (2), ..., 18 (n) (FET gates) corresponding to the photoelectric conversion elements of the image sensor 100 are provided.
In addition to the buffer amplifiers 20 (1), 20 (2), ..., 20 (n),
Switching element 21 for switching the output of each buffer amplifier
, 21 (n) and AND gates 22 (1), 22 (2), ..., 22 (n) for controlling the supply of switching signals related to on / off of each switching element. A shift register 23 that is configured and sequentially shifts a switching control bit from the control input terminal IA to the AND gate in synchronization with the clock CLK is configured. And
Every time a read pulse from the other control input terminal INH is input, the read pulse is sent to the switching element 21 via the AND gate 22 corresponding to the position where the switch bit is stored in the shift register 23 at that time. , And the detection signal from the photoelectric conversion element via the switching element 21 is output from the output terminal OUT. Therefore, with the shift operation of the switching bit in the shift register 23, a signal corresponding to the amount of incident light in each cell of the image sensor 100 is serially output from the output terminal OUT.

The image sensor 100 has a power supply voltage of −5, for example.
While V is applied, ± 5V is applied as a power supply voltage to the image sensor LSI 200. The CR terminal is an output reset terminal, and the VR terminal is a reset voltage supply terminal.

[Problems to be Solved by the Invention] By the way, in the conventional photodetector circuit as described above, it is difficult to drive with a single power source. That is, the reference bias to be supplied to the photoelectric conversion element and the power supply voltage to be supplied to the buffer amplifier circuit cannot be the same.

Since the signal extraction electrode of the photoelectric conversion element is directly connected to the input terminal of the buffer amplifier circuit, a signal of a level close to the bias potential of the photoelectric conversion element is input to the buffer amplifier circuit. This is because in order to guarantee the linearity of the output characteristics of the buffer amplifier circuit based on the signal, the power supply voltage supplied to the buffer amplifier circuit must be higher than the bias voltage of the photoelectric conversion element.

Then, the subject of this invention is reducing the input level with respect to the buffer amplifier circuit according to the signal output from the signal extraction electrode of a photoelectric conversion element.

[Means for Solving the Problems] As shown in FIG. 1, the present invention provides a charge generation function and a charge storage function according to the amount of incident light between two electrodes 1a and 1b including a signal extraction electrode 1a. The photoelectric conversion element 1 which it has, the reference bias switching element 2 which switches the application or interruption of the reference bias voltage Vb between the photoelectric conversion element electrodes 1a and 1b, and the signal extraction electrode 1a based on the charge accumulation state of the photoelectric conversion element 1 It is premised on a photodetector circuit provided with a buffer amplifier circuit 3 that outputs a signal at a level within the supply voltage range in accordance with the signal output of 1. The means arranges the capacitive element 4 in series between the signal extraction electrode 1a of the photoelectric conversion element 1 and the input terminal of the buffer amplifier circuit 3, and
The bias switching element 5 that switches between applying and blocking the bias Vo with respect to the input end of the buffer amplifier circuit 3 and the bias application state of the bias switching element 5 switches the reference bias switching element 2 from the bias application state to the interruption state. The switching control means 6 switches the bias switching element 5 to the bias cutoff state and the reference bias switching element 2 to the bias application state.

[Operation] When the bias switching element 5 is in the bias applied state, the output of the buffer amplifier circuit 3 is the bias Vo
Fixed to a level based on. In this state, when the switching control means 6 switches the reference bias switching element 2 from the bias application state to the bias cutoff state, the signal extraction of the photoelectric conversion element 1 preset by the reference bias Vb based on the charge storage function until that point. Electrode 1a
The level of the output signal from V fluctuates due to the action of accumulating charges generated according to the amount of incident light on the photoelectric conversion element 1. When this variation becomes Vs, the level of the capacitive element 4 at the photoelectric conversion element 1 side end is Vb-Vs, and the level of the buffer amplifier circuit 3 side end is fixed to the bias voltage Vo. In this state, when the switching control means 6 switches the bias switching element 5 to the bias cutoff state and the reference bias switching element 2 to the bias application state, respectively, the level of the end of the capacitance element 4 on the photoelectric conversion element 1 side becomes the reference bias potential Vb. Fixed to. Then, the level of the end of the capacitive element 4 on the buffer amplifier circuit 3 side becomes
Vb− (Vb−Vs−Vo) = Vs + Vo due to the action of holding the accumulated charge by itself. As a result, the input level of the buffer amplifier circuit 3 becomes Vs + Vo.

Here, the fluctuation value Vb of the signal extraction electrode 1a of the photoelectric conversion element 1
Is, for example, as shown in FIG.
At 5V, the maximum Vs is about 2V. Therefore, by appropriately selecting the performance of the photoelectric conversion element 1 and the bias voltage Vo to be applied to the input terminal of the buffer amplifier circuit 3, the signal level input to the buffer amplifier circuit 3 is the reference bias voltage Vb for the photoelectric conversion element 1. It will be even lower.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing a basic configuration example of an image reading apparatus using the photodetector circuit according to the present invention.

Image sensor 100 having a plurality of cells composed of photoelectric conversion elements, and image sensor LSI for processing signal output from each cell of image sensor 100 as an image signal
The connection relationship of 00 is the same as that shown in FIG. As described above, the image sensor LSI 200 corresponds to each cell of the image sensor 100 and corresponds to the reference bias switching element, the buffer amplifier, the output switching switching element, the signal supply control AND gate, and the AND gate gate control. It has elements such as a shift register for sequentially shifting bits (see FIG. 10), and elements to which new functions as described later are added are added.

Various control signals INH, IA and clock signal CLK are supplied from the control circuit 300 to the image sensor LSI 200, and the image sensor LSI 200 operates in each cell of the image sensor 100 according to the state of each supply signal. The image signal corresponding to the amount of incident light is output serially from the output terminal OUT.

A power supply voltage of 0 to + 5V is applied to the image sensor LSI 200, and a reference bias voltage of 5V is similarly applied between electrodes of each cell (photoelectric conversion element) of the image sensor 100. That is, the image sensor 100 and the image sensor LSI 200 are driven by a single power source (+ 5V).

In this way, the element for realizing the power supply drive of the same voltage as the inter-electrode bias voltage of each cell of the image sensor 100 is configured as a new element in the image sensor LSI 200. The specific structure is, for example, as shown in FIG.

Photoelectric conversion element 10 composed of photocurrent source 15 and capacitance element 16
A FET gate 18 as a switching element is similarly connected and arranged between the signal extraction electrode of each cell of the image sensor 100 and the power supply + 5V line, and + 5V is connected between the electrodes of the photoelectric conversion element 10 via the FET gate 18. Bias voltage is applied. Further, a capacitor 25 is arranged in series between the signal extraction electrode of the photoelectric conversion element 10 and the input terminal (+) of the buffer amplifier 20, and the input terminal (+) of the buffer amplifier 20 is connected via the FET gate 26. Grounded.

Image sensor 100 in image sensor LSI 200
Each buffer amplifier 20 corresponding to each cell (photoelectric conversion element)
The preceding stage has the same configuration as above.

Next, the operation will be described with reference to the timing chart shown in FIG.

Each FET gate is synchronized with the clock signal from the control circuit 300
18,26 ON / OFF switching control is performed.

When the FET gate 18 is turned on, a reference bias of + 5V is applied between the electrodes of the photoelectric conversion element 10, and the signal extraction electrode is fixed at approximately + 5V by precharging the capacitance element 16 with the bias. Voltage level at the point A on the photoelectric conversion element 10 side). When the FET gate 26 is turned on, the input terminal (+) of the buffer amplifier 20
Is biased to ground level (0V) and its output is fixed at 0V. In this state, when the FET gate 18 is switched to the off state (time t1), the voltage level of the signal extraction electrode sequentially decreases due to the action of accumulating the charge generated in accordance with the amount of incident light on the photoelectric conversion element 10 in the capacitive element 16. To go. That is, the voltage level at point A decreases. At time t2, the voltage level at the point A changes from + 5V to Vs.
When the FET gate 26 is switched to the off state and the FET gate 18 is switched to the on state in the state of being lowered by only (+ 5v-Vs), the voltage level at the point A is forcibly fixed to + 5V by the application of the reference bias. At the same time, the voltage level of the input terminal (+) of the buffer amplifier 20 is raised to + 5V-(+ 5v-Vs) = Vs in order to hold the voltage across the terminals of the capacitor 25.

The voltage level Vs applied to the input terminal (+) of the buffer amplifier 20 corresponds to the amount of incident light to the photoelectric conversion element 10, and its value is, for example, as shown in FIG.
It will be about 0.8V to 2V. As a result, the output voltage level of the buffer amplifier 20 becomes a level between 0.8 (no incident light) and 2 V (maximum incident light amount). This is lower than the power supply voltage of the image sensor LSI 200, that is, the power supply voltage + 5V supplied to the buffer amplifier 20.
Therefore, the linearity of the output characteristics of is sufficiently secured.

The clock CKL that becomes the synchronization signal for each of the above switching operations.
The frequency of 1MHz ~ 5MHz, image sensor 100
The sampling cycle (between times t1 and t2) for one cell is about 5 msec. Therefore, in this case, the image signal corresponding to all the cells forming the image sensor 100 is serially output from the output terminal OUT of the image sensor LSI 200 every 5 msec.

As described above, according to this embodiment, the image sensor LSI 2
FET that becomes the capacitor 25 and switching element at 00
Only by adding the gate 26, the input voltage level to the buffer amplifier can be reduced. Further, since the capacitor 25 is the only element that affects the bit-to-bit variation in the image signal level, the degree of the variation can be made sufficiently small.

FIG. 5 is a circuit configuration diagram showing another embodiment of the photodetector circuit according to the present invention.

This example compensates for a decrease in the input signal level of the buffer amplifier 20 due to parasitic capacitance in the LSI.

When a parasitic capacitance is formed between the input terminal (+) of the buffer amplifier 20 and the ground line, the signal level input to the input terminal (+) is the voltage level at point A divided by the capacitor 25 and the parasitic capacitance. Becomes Therefore, a capacitive element 27 that cancels unclear parasitic capacitance is connected and arranged between the input terminal (+) of the buffer amplifier 20 and the ground line, and an appropriate gain is provided to the buffer amplifier as the input level is reduced. The resistance elements R1 and R2 are connected and arranged so as to have the function. The gain GG in this case is (R1 + R2) / R1.

Then, the input voltage level to the buffer amplifier 20 becomes C1 / (C1 + C2) · Vs, and the output voltage level of the buffer amplifier 20 becomes {C1 / (C1 + C2) · Vs} × {(R1 + R2) / R1}.

[Effects of the Invention] As described above, according to the present invention, the signal level input to the buffer amplifier circuit is lowered,
Even if the power supply voltage supplied to the buffer amplifier circuit is the same as the bias voltage applied between the electrodes of the photoelectric conversion element, the linearity of the output characteristic of the buffer amplifier circuit can be ensured. Therefore, a photodetector circuit capable of being driven by a single power source can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of the present invention, FIG. 2 is a block diagram showing a basic configuration example of an image reading apparatus to which a photo detection circuit according to the present invention is applied, and FIG. 3 is a photo detection according to the present invention. FIG. 4 is a circuit diagram showing an example of the circuit, FIG. 4 is a timing chart showing the operation of the circuit shown in FIG. 3, FIG. 5 is a circuit diagram showing another example of the photodetector circuit according to the present invention, and FIG. FIG. 7 is a diagram showing a structure example of a conversion element, FIG. 7 is a circuit diagram showing an equivalent circuit of the photoelectric conversion element shown in FIG. 6, FIG. 8 is a diagram showing an example of output level characteristics of the photoelectric conversion element, and FIG. FIG. 10 is a circuit diagram showing a conventional photo detection circuit, and FIG. 10 is a diagram showing an example of a basic structure of an LSI in which elements of the conventional photo detection circuit are configured. [Explanation of Codes] 1, 10 ... Photoelectric conversion element 1a ... Signal extraction electrode 2 ... Reference bias switching element 3 ... Buffer amplifier circuit 4 ... Capacitance element 5 ... Bias switching element 6 ... Switching control means 15 ... Photocurrent source 16 ... Capacitance Element 18, 26 ... FET gate 20 ... Buffer amplifier 25 ... Capacitor 100 ... Image sensor 200 ... Image sensor LSI 300 ... Control circuit

Claims (1)

[Claims] 1. A photoelectric conversion element (1) having a charge generation function and a charge storage function according to the amount of incident light between two electrodes (1a, 1b) including a signal extraction electrode (1a), and a photoelectric conversion element electrode. Between the reference bias switching element (2) that switches between applying and blocking the reference bias voltage (Vb) between the two, and the signal output of the signal extraction electrode (1a) based on the charge accumulation state of the photoelectric conversion element (1). , Buffer amplifier circuit (3) for outputting a signal at a level within the supply voltage range
In the photodetector circuit including: a capacitive element (4) is connected in series between the signal extraction electrode (1a) of the photoelectric conversion element (1) and the input end of the buffer amplifier circuit (3), and a buffer is provided. A bias switching element (5) that switches between applying and blocking a bias (Vo) to the input terminal of the amplifier circuit (3) and a bias applying state by the bias switching element (5) biases the reference bias switching element (2). Switching control means (6) for switching from the applied state to the cutoff state, and thereafter switching the bias switching element (5) to the bias cutoff state and the reference bias switching element (2) to the bias application state, respectively. Photo detector circuit.